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DESIGN SPACE EXPLORATION FOR APPLICATION SPECIFIC ...

DESIGN SPACE EXPLORATION FOR APPLICATION SPECIFIC ...

DESIGN SPACE EXPLORATION FOR APPLICATION SPECIFIC

DESIGN SPACE EXPLORATION FOR APPLICATION SPECIFIC FPGAS IN SYSTEM-ON-A-CHIP DESIGNS Mark Hammerquist, Roman Lysecky Department of Electrical and Computer Engineering University of Arizona, Tucson, AZ, USA {hansolo, rlysecky}@ece.arizona.edu ABSTRACT The inclusion of field programmable gate arrays (FPGAs) within a system-on-a-chip (SOC) design offers programmability, flexibility, and reconfigurability not possible with application specific integrated circuits (ASIC) or fullcustom implementations. However, these benefits come at the expense of significant area, performance, and power consumption overheads compared to ASIC or full-custom circuits. As a typical SOC design will require fabrication of the final integrated circuit, rather than rely on a generic FPGA architecture, an FPGA integrated within an SOC design can be optimized for the specific intended application. In this paper, we present an initial design space exploration framework for generating an application specific FPGA (ASFPGA) by tailoring several FPGA architectural features for a specific hardware circuit to improve the area, delay, or energy consumption compared to traditional FPGA designs and reduce the overheads of utilizing an FPGA compared to ASIC and full custom implementations. I. INTRODUCTION The inclusion of field programmable gate arrays (FPGAs) within a system-on-a-chip (SOC) design offers many advantages over purely application specific integrated circuits (ASIC) or full-custom implementations. FPGAs can implement any hardware circuit simply by downloading bits for that hardware circuit, much in the same way that microprocessors can execute any software program simply by downloading an application binary. In this manner, FPGAs extend the flexibility of software design to hardware circuits, allowing constant hardware modifications, corrections, upgrades, etc. throughout the development cycle and even after device fabrication. For example, costly hardware design errors that would require a respin with an ASIC implementation can be fixed in hardware within the FPGA by downloading the corrected hardware circuit. Similarly, FPGAs enable rapid development in which the hardware implementation need not be finalized before fabrication. Instead, the physical SOC incorporating an FPGA can be fabricated earlier in the design process. The hardware design for those elements implemented within the FPGA can then be finalized after manufacturing. An FPGA can also be reconfigured at runtime to implement multiple hardware circuits throughout an application’s execution using the same physical resources. Hardware/software codesign approaches targeting FPGAs can also provide significant performance benefits and/or power savings compared to software only implementations. However, the reconfigurability and flexibility of FPGAs comes at the costs of significant area, performance, and power consumption overheads compared to ASIC circuits. Research has demonstrated that FPGAs require 10-40X greater area, 5-12X greater power consumption, and 3-4X greater critical path delays compared to their equivalent ASIC counterparts. While rapid increases in IC capacities can alleviate area concern, their significant power and performance overheads may present significant hurdles for allowing FPGAs to be integrated within an SOC design. While many platform-based SOC design options exist, typical SOC design will require the fabrication of an ASIC or full-custom design, and provides an opportunity to tailor the design of the FPGA itself to the specific target application. Rather than rely on a generic FPGA architecture, the FPGA integrated within an SOC design can be optimized for the intended application, thereby requiring less area with greater performance and lower energy consumption. In this paper, we present an initial design space exploration framework for generating an application specific FPGA (ASFPGA) by tailoring several FPGA architectural features for a specific hardware circuit. In Section II, we first discuss several related efforts that are primarily complementary to our proposed ASFPGA approach. In Section III, we present a brief overview of FPGAs and highlight the configurable FPGA architectural features considered in this paper. In Section IV, we present our design space exploration framework for ASFPGAs. Finally, in Section V, we summarize the area, performance, and power savings of ASFPGAs for several hardware circuits. II. RELATED WORK Significant research efforts have focused on providing automated methods for creating reconfigurable devices either within standard cell technologies or as custom physical layout. Several research and development efforts have focused on efficiently implementing FPGAs – or similar reconfigurable devices – using standard cell technologies. In [9], eASIC silicon technology is used to create coarsegrained reconfigurable elements connected through fixed routing channels to create a reconfigurable array. In [1], FPGA specific standard cells are proposed to enable more efficient implementation of FPGAs within standard cell technologies by imposing structure specific to the FPGA. In [7] and [10], researchers present a method for automatically generating a transistor level implementation of an FPGA starting from an architectural description of the FPGA with only a 36% area overhead compared to a full-custom implementation and have verified their automated process with the successful fabrication of the resulting FPGA implementation. In [4][5][6], Holland and Hauck presented an automated tool flow for creating domain-specific PLAs, PALs, and CPLDs. Within this proposed approach, a domain can be loosely defined as a set of similar applications, such as sequential, combinational, floating point, or encryptions domains. By analyzing the netlists of the applications within the target domain, the reconfigurable

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