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82600 DualPCI Embedded System Controller - Radisys

82600 DualPCI Embedded System Controller - Radisys

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82600 High Integration

Dual PCI System

Controller Data Book

07-01277-0002 • January 2003


The information contained in this document is

preliminary and subject to change. Please email

any questions, comments or requests for support

to chipset.support@radisys.com.

Information in this document is provided in

connection with RadiSys products. No license,

express or implied, by estoppel or otherwise, to

any intellectual property rights is granted by this

document. Except as provided in RadiSys Terms

and Conditions of Sale for such products, RadiSys

assumes no liability whatsoever, and RadiSys

disclaims any express or implied warranty,

relating to sale and/or use of RadiSys products

including liability or warranties relating to fitness

for a particular purpose, merchantability, or

infringement of any patent, copyright or other

intellectual property right. RadiSys products are

not intended for use in medical, life saving, or life

sustaining applications.

RadiSys may make changes to specifications and

product descriptions at any time, without notice.

Corporate Headquarters

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Phone: 503-615-1100

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Designers must not rely on the absence or

characteristics of any features or instructions

marked “reserved” or “undefined.” RadiSys

reserves these for future definition and shall have

no responsibility whatsoever for conflicts or

incompatibilities arising from future changes to

them.

The RadiSys 82600 may contain design defects

or errors known as errata that may cause the

product to deviate from published specifications.

Current characterized errata are available on

request.

I2C is a 2-wire communications bus/protocol

developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.

Implementations of the I2C bus/protocol may

require licenses from various entities, including

Philips Electronics N.V. and North American

Philips Corporation.

* Third party brands and names are the

property of their respective owners.

January 2003

Copyright ©199, 2000, 2001, 2002, 2003 by RadiSys Corporation.

All rights reserved.

EPC and RadiSys are registered trademarks of RadiSys Corporation. ASM, Brahma, DAI, DAQ, MultiPro, SAIB, Spirit, and ValuePro are

trademarks of RadiSys Corporation.

DAVID, MAUI, OS-9, OS-9000, and SoftStax are registered trademarks of RadiSys Microware Communications Software Division, Inc.

FasTrak, Hawk, and UpLink are trademarks of RadiSys Microware Communications Software Division, Inc.

† All other trademarks, registered trademarks, service marks, and trade names are the property of their respective owners.


82600 DualPCI Embedded System Controller

Product Features

Processor/Host • Bus Support

• Compatible with Intel ® Celeron, Pentium ® II

and Pentium® III processors

• GTL+ bus driver technology

• Optimized for 133MHz system bus frequency;

Support for 66MHz and 100MHz

• In-order transaction and dynamic deferred

transaction support

• Snoop Support

• Integrated SDRAM Controller

• Support for 512Mb technology

• 16MB to 2GB of main memory

• Supports up to 2 double sided DIMM SDRAM

modules

• 7.8, 15.6, and 125 microsecond refresh rates

supported.

• Support for registered and unbuffered DIMMs

• ECC support with automatic single bit error

“scrub”, multiple bit error detect

• Dual PCI Bus Architecture

• Independent local and backplane PCI buses with

an integrated virtual PCI to PCI bridge

• Provides isolation between local and backplane

peripherals

• Asynchronous operation of both PCI buses

• Supports concurrent CPU, local PCI and

backplane PCI transactions

• Local PCI Bus

• 33/66MHz interface

• 3.3V and 5V, PCI 2.2 compliant

• 5 BREQ/BGNT pairs

• Delayed transaction support for PCI-DRAM

reads

• Backplane PCI (BPCI) Bus

• PCI Rev. 2.2, 3.3V and 5V, 33/66MHz interface

compliant

• 7 BREQ/BGNT pairs

• Supplies all PCI Central Resource functions

• PCI Central Resource functions can be disabled

for I/O processor applications

• Doorbell interrupt support

• PCI “window” support for host initiated accesses

• Flexible mapping of main memory into PCI

address space

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• BPCI/SDRAM DMA Controller

• High throughput multi-channel architecture

• Fully FIFO buffered for maximum bandwidth

utilization

• Supports scatter/gather DMA command chaining

• Integrated pacing counters to throttle transfers

• Supports software DMA termination

• Local host interface controlled

• Direct Flash Support

• Glueless single X16 device interface

• Shared with SDRAM interface pins

• Page-Mode or asynchronous flash

• 64MB total flash capacity

• Supports Execute-in-Place

• Integrated Core PC Logic

• Includes all legacy PC/AT compatible peripherals

• Two 82C59 interrupt controllers

• Two 82C37 DMA controllers

• 82C54 timer/counter

• 74LS612 address mapper

• Real Time Clock

• 256 byte battery backed CMOS SRAM

• Integrated Peripherals

• Ultra DMA/66 EIDE Interface

• USB 1.1 host controller with 2 ports

• COM1 and COM2 support with 16550 compatible

UARTs

• PS/2 compatible keyboard and mouse ports

• SMBus host interface

• Power Management Support

• Ideal for small, battery powered applications

• Legacy power management/SMI support

• STPCLK support

• Integrated Watchdog Timer

• Detects system lockup

• Flexible hardware reset or interrupt on timeout

• General Purpose Digital I/O

• 32 bits

• Multiplexed with other pin functions

• 576 Pin BGA Package


Contents

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1 PRODUCT OVERVIEW ......................................................................................................................................13

1.1 REFERENCES...................................................................................................................................................15

2 SIGNAL DESCRIPTIONS ..................................................................................................................................16

2.1 SIGNAL TYPE ABBREVIATIONS..................................................................................................................16

2.2 CLOCK AND RESET SIGNALS.......................................................................................................................17

2.3 CPU/BUS SIGNALS........................................................................................................................................18

2.4 CPU SIGNALS NOT SUPPORTED BY THE 82600 .......................................................................................21

2.5 POWER MANAGEMENT SIGNALS................................................................................................................21

2.6 SDRAM INTERFACE SIGNALS.....................................................................................................................22

2.7 LOCAL PCI BUS INTERFACE SIGNALS.........................................................................................................23

2.8 BACKPLANE PCI BUS INTERFACE SIGNALS..............................................................................................25

2.9 REAL TIME CLOCK INTERFACE SIGNALS..................................................................................................28

2.10 KEYBOARD/USB INTERFACE SIGNALS......................................................................................................29

2.11 COM PORTS INTERFACE ..............................................................................................................................30

2.12 MISCELLANEOUS SIGNALS...........................................................................................................................32

2.13 EIDE SIGNALS.................................................................................................................................................33

2.14 POWER AND GROUND PINS..........................................................................................................................34

3 POWER-UP CONFIGURATION OPTIONS ...................................................................................................36

4 REGISTER DESCRIPTIONS .............................................................................................................................39

4.1 POWER MANAGEMENT REGISTER: A=0022, R=00...................................................................................40

4.2 KEYBOARD CONTROLLER DATA REGISTER: A=0060, R=X4.................................................................41

4.3 PORT B REGISTER: A=0061, R=X0...............................................................................................................41

4.4 KEYBOARD CONTROLLER STATUS/COMMAND REGISTER: A=0064, R=00.........................................42

4.5 RTC INDEX REGISTER: A=0070, R=80........................................................................................................42

4.6 RTC DATA PORT : A=0071, R=00 ................................................................................................................42

4.7 EXTENDED CMOS INDEX REGISTER: A=0072, R=00...............................................................................42

4.8 EXTENDED CMOS DATA PORT : A=0073, R=XX......................................................................................42

4.9 PORT A (PORT 92): A=0092, R=02 ..............................................................................................................43

4.10 ELCR1, EDGE/LEVEL CONTROL REGISTER 1: A=04D0, R=00.................................................................43

4.11 ELCR2, EDGE/LEVEL CONTROL REGISTER 2: R=04D1, R=00..................................................................44

4.12 LPCI/BPCI CONFIGURATION INDEX/DATA REGISTERS..........................................................................44

4.12.1 LPCI/BPCI Configuration Index Register: A=0CF8, R=0000_0000.......................................45

4.12.2 LPCI/BPCI Configuration Data Register: A=0CFC, R=xxxx_xxxx..........................................45

4.13 RC—RESET CONTROL REGISTER: A=0CF9, R=XX..................................................................................46

4.14 ALTERNATE BPCI CONFIGURATION INDEX/DATA REGISTERS............................................................46

4.14.1 Alternate BPCI Configuration Index Register: A=1CF8, R=0000_0000 ...............................47

4.14.2 Alternate BPCI Configuration Data Register: A=1CFC, R=xxxx_xxxx ..................................47

4.15 LPCI CONFIGURATION REGISTERS (DEVICE 0, FUNCTION 0,1, & 2) ....................................................47

4.15.1 LVID, Vendor Identification Register: A=0.0, R=1331...............................................................50

4.15.2 LDID, Device Identification Register: A=0.2, R=8200................................................................50

4.15.3 LPCICMD, LPCI Command Register: A=0.4, R=0006................................................................51

4.15.4 LPCISTS, LPCI Status Register: A=0.6, R=0220 .........................................................................52

4.15.5 LRID, Revision Identification Register: A=0.08, R=00...............................................................52

4.15.6 LCLASSC, Class Code Register: A=0.09, R=06_0000 ...............................................................53

4.15.7 LMLT, Master Latency Timer: A=0.0D, R=00...............................................................................53

4.15.8 LHT, Header Type: A=0.0E, R=80...................................................................................................53

4.15.9 LSUBVID, Sub-Vendor Identification Register: A=0.2C, R=0000............................................53


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4.15.10 LSUBDID, Sub-Device Identification Register: A=0.2E, R=0000 ........................................53

4.15.11 MLPC, Miscellaneous LPCI Control: A=0.4C, R=00.............................................................54

4.15.12 DRAMC, SDRAM Control Register: A=0.57, R=00................................................................55

4.15.13 PAM, Programmable Address Map Registers: A=0.59-0.5D, ................................................56

4.15.14 DRBA[0:3], SDRAM Row Boundary Address Register: A=0.60-0.63, R=00......................57

4.15.15 LMTT, Multi-Transaction Timer Register: A= 0.70, R=20.....................................................58

4.15.16 SMRAMC, System Management RAM Control Register: A=0.71, R=00.............................58

4.15.17 RPS - SDRAM Row Page Size Register: A=0.74, R=00 .........................................................59

4.15.18 SDRAMC, SDRAM Control Register: A=0.76, R=0000..........................................................60

4.15.19 PGPOL, Paging Policy Register: A=0.78, R=0000.................................................................61

4.15.20 MCTL, Miscellaneous Control Register: A=0.7A, R=00........................................................61

4.15.21 LAAR, Local Abort Address Register: A=0.7C, R=0000_0000.............................................61

4.15.22 EAP, Error Address Pointer Register: A=0.80, R=0000_0000.............................................62

4.15.23 POB, Power-On Option Bit Register: A=0.90, R={0,MA[14:0]}..........................................63

4.15.24 CPO, COM Port Option Register: A=0.92, R=12 ....................................................................63

4.15.25 PWRMGT/Extended Functions Configuration Register: A=0.94, R=0000 ........................63

4.15.26 MFE, Miscellaneous Function Enable Register: A=0.96, R=(see description) ................64

4.15.27 LIRQRC[A:D], LIRQX Route Control Registers: A=0.A0-0.A3, R=0x80.............................65

4.16 DEVICE 0, FUNCTION 1 REGISTERS (PCI EIDE CONFIGURATION REGISTERS).....................................65

4.16.1 VID1, Vendor Identification Register: A=1.0, R=1331...............................................................65

4.16.2 DID1, Device Identification Register: A=1.2, R=8201................................................................65

4.16.3 PCICMD1, PCI Command Register: A=1.4, R=0000..................................................................66

4.16.4 PCISTS1, PCI Status Register: A=1.6, R=0000............................................................................66

4.16.5 RID, Revision Identification Register: A=1.8, R=0000...............................................................66

4.16.6 CLASSC, Class Code Register: A=1.9, R=01_0180....................................................................66

4.16.7 MLT, Master Latency Timer: A=1.D, R=00....................................................................................66

4.16.8 HEDT1, Header Type Register: A=1.0E, R=00.............................................................................67

4.16.9 BMIBA1, Bus Master Interface Address: A=1.20, R=0000_0001 .............................................67

4.16.10 IDETIM, IDE Timing Register: A=1.40, R=0000......................................................................68

4.16.11 UDMACTL, Ultra DMA/66 Control Register: A=1.48, R=00................................................69

4.16.12 UDMATIM, Ultra DMA/66 Timing Register: A=1.4A, R=00..................................................69

4.17 IDE BUS MASTER CONTROLLER I/O SPACE REGISTERS.........................................................................69

4.17.1 BMICX, Bus Master IDE Command Register: A=IDE_BASE+0, R=00....................................70

4.17.2 BMISX, Bus Master IDE Status Register: A=IDE_BASE+2, R=00 ...........................................70

4.17.3 BMIDTPX, Bus Master IDE Descriptor Table Pointer Register:................................................71

4.18 DEVICE 0, FUNCTION 2 (USB) CONFIGURATION REGISTERS.................................................................71

4.18.1 VID2, Vendor Identification Register: A=2.0, R=1331...............................................................71

4.18.2 DID2, Device Identification Register: A=2.2, R=8202................................................................72

4.18.3 PCICMD2, PCI Command Register: A=2.4, R=0000..................................................................72

4.18.4 PCISTS2, PCI Status Register: A=2.6, R=0000............................................................................72

4.18.5 RID, Revision Identification Register: A=2.8, R=0000...............................................................72

4.18.6 CLASSC2, Class Code Register: A=2.9, R=0C_0300.................................................................72

4.18.7 MLT2, Master Latency Timer: A=2.D, R=00 .................................................................................73

4.18.8 HEDT2, Header Type Register: A=2.E, R=00 ...............................................................................73

4.18.9 USBBA, USB Base Address Register: A=2.20, R=0000_0001...................................................73

4.18.10 INTL, Interrupt Line Register: A=2.3C, R=00 ..........................................................................73

4.18.11 INTP, Interrupt Pin Register: A=2.3D, R=04............................................................................73

4.18.12 SBRNUM, Serial Bus Release Number: A=2.60, R=11...........................................................74

4.19 USB HOST CONTROLLER I/O SPACE REGISTERS.....................................................................................74

4.19.1 USBCMD-USB Command Register: A=USB_BASE+0, R=0000..............................................74

4.19.2 USBSTS, USB Status Register: A=USB_BASE+2, R=0000........................................................77

4.19.3 USBINTR, USB Interrupt Enable Register: A=USB_BASE+4, R=0000 ..................................78

4.19.4 FRNUM, Frame Number Register: A=USB_BASE+6, R=0000.................................................78

4.19.5 FLBASEADD, Frame List Base Address Register: ........................................................................78


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4.19.6 SOFMOD, Start of Frame (SOF) Modify Register: A=USB_BASE+C, R=40 .........................79

4.19.7 PORTSC, Port Status and Control Register:.................................................................................79

4.20 LOCAL I/O MAPPED FUNCTIONS................................................................................................................82

4.20.1 Power Management Support Registers ..........................................................................................82

4.20.1.1 PMSTS, Power Management Status Register: A=PWRBASE+0, R=0000...................................82

4.20.1.2 PMEN, Power Management Resume Enable Register: A=PWRBASE+2, R=0000......................83

4.20.1.3 PMCNTRL, Power Management Control Register: A=PWRBASE+4, R=0000..........................83

4.20.1.4 PMTMR, Power Management Timer: A=PWRBASE + 8, R=00_0000 ......................................84

4.20.1.5 GPSTS, General Purpose Status Register: A=PWRBASE+ C, R=0000 .......................................84

4.20.1.6 GPEN General Purpose Enable Register: A=PWRBASE+ E, R=0000 .........................................85

4.20.2 Legacy Power Management Support Registers ............................................................................85

4.20.2.1 PCNTRL, Processor Control Register: A=PWRBASE+10, R=00................................................85

4.20.2.2 GLBTIM, Global Standby Timer Register: A=PWRBASE+12, R=0000.....................................86

4.20.2.3 WTCHDG, Watchdog Timer Register: A=PWRBASE+ 14, R=0000...........................................87

4.20.2.4 GLBTIMCTRL, Global Standby Timer Control Register: A=PWRBASE+16, R=00 .................88

4.20.2.5 SMICTRL, SMI Status/Control Register: A=PWRBASE+18, R=0000 .......................................89

4.20.2.6 DGCTRL, Watchdog Control/Status Register: A=PWRBASE+1A, R=00...................................90

4.20.2.7 LDEV0, Local Device Decode 0 Register: A=PWRBASE+1C, R=0000_0000.............................91

4.20.2.8 LDEV1, Local Device Decode 1 Register: A=PWRBASE+20, R=0000_0000..............................92

4.20.3 Digital I/O Control/Data Registers.................................................................................................92

4.20.3.1 DIOO, Digital I/O Output Register: A=PWRBASE + 24, R=0000_0000 ....................................92

4.20.3.2 DIOD, Digital I/O Direction Register: A=PWRBASE+28, R=0000_0000 ...................................93

4.20.3.3 DIOI, Digital I/O Input Register: A=PWRBASE + 2C, R=0000_0000 ........................................93

4.20.4 SMBus Status/Control Registers......................................................................................................94

4.20.4.1 SMBus Transmit/Status/Control Register: A=PWRBASE + 30, R=0000 ....................................94

4.20.4.2 SMBus Input/Control/Status Register: A=PWRBASE+32, R=0000............................................95

4.20.4.3 IRQ9SRC Status Register: A=PWRBASE+34, R=0000 ...............................................................96

4.20.4.4 PCI Interrupt Status Register: A=PWRBASE+36, R=Pin Levels .................................................97

4.20.5 BPCI/SDRAM DMA Control Registers ...........................................................................................97

4.20.5.1 ODMACS0 - Outgoing DMA Control/Status 0: A=PWRBASE+38, R=0000.............................97

4.20.5.2 ODMACS1 - Outgoing DMA Control/Status 1: A=PWRBASE+3A, R=0000............................97

4.20.5.3 IDMACS0 - Incoming DMA Control/Status 0: A=PWRBASE+3C, R=0000..............................97

4.20.5.4 IDMACS1 - Incoming DMA Control/Status 1: A=PWRBASE+3E, R=0000..............................97

4.20.5.5 ODMAPA0, Outgoing DMA BPCI Address Register 0:..............................................................99

4.20.5.6 ODMAPA1, Outgoing DMA BPCI Address Register 1:..............................................................99

4.20.5.7 IDMAPA0, Incoming DMA BPCI Address Register 0: ...............................................................99

4.20.5.8 IDMAPA1, Incoming DMA BPCI Address Register 1: ...............................................................99

4.20.5.9 ODMAHA0, Outgoing DMA Host Address Register 0:............................................................100

4.20.5.10 ODMAHA1, Outgoing DMA Host Address Register 1:............................................................100

4.20.5.11 IDMAHA0, Incoming DMA Host Address Register 0:..............................................................100

4.20.5.12 IDMAHA1, Incoming DMA Host Address Register 1:..............................................................100

4.20.5.13 ODMATL0, Outgoing DMA Transfer Length Register 0:..........................................................101

4.20.5.14 ODMATL1, Outgoing DMA Transfer Length Register 1:..........................................................101

4.20.5.15 IDMATL0, Incoming DMA Transfer Length Register 0: ...........................................................101

4.20.5.16 IDMATL1, Incoming DMA Transfer Length Register 1: ...........................................................101

4.20.5.17 ODMANDA0, Outgoing DMA Next Descriptor Address Register 0:.......................................102

4.20.5.18 ODMANDA1, Outgoing DMA Next Descriptor Address Register 1:.......................................102

4.20.5.19 IDMANDA0, Incoming DMA Next Descriptor Address Register 0:.........................................102

4.20.5.20 IDMANDA1, Incoming DMA Next Descriptor Address Register 1:.........................................102

4.20.6 Virtual PCI to PCI (P2P) Bridge Configuration Registers. .....................................................102

4.20.6.1 VID, Vendor Identification Register: A=0, 1.0.0, R=1331...........................................................104

4.20.6.2 DID, Device Identification Register: A=2, 1.0.2, R=8210...........................................................104

4.20.6.3 PCICMD, PCI Command Register: A=4, 1.0.4, R=0000............................................................105

4.20.6.4 PCISTS, PCI Status Register: A=6, 1.0.6, R=0000 .....................................................................106


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4.20.6.5 RID, Revision Identification Register: A=08, 1.0.8, R=00 ..........................................................106

4.20.6.6 CLASSC, Class Code Register: A=09, 1.0.9, R=06_0400...........................................................106

4.20.6.7 CLS, Cache Line Size Register: A=0C, 1.0.C, R=08....................................................................106

4.20.6.8 MLT, Master Latency Timer: A=0D, 1.0.D, R=00 ....................................................................107

4.20.6.9 HT, Header Type: A=0E, 1.0.E, R=01........................................................................................107

4.20.6.10 PBN, Primary Bus Number: A=18,1.0.18, R=00 ........................................................................107

4.20.6.11 SBN, Secondary Bus Number: A=19,1.0.19, R=00.....................................................................107

4.20.6.12 SUBN, Subordinate Bus Number: A=1A,1.0.1A, R=00..............................................................108

4.20.6.13 SLT, Secondary Latency Timer: A=1B,1.0.1B, R=00.................................................................108

4.20.6.14 IOBL, I/O Base and Limit Register: A=1C,1.0.1C, R=0000........................................................108

4.20.6.15 SSTS, Secondary Status Register: A=1E, 1.0.1E, R=0230...........................................................109

4.20.6.16 MBL0, Memory Base and Limit Register 0: A=20,1.0.20, R=0000_0000 .................................110

4.20.6.17 MBL1, Memory Base and Limit Register 1: A=24,1.0.24, R=0000_0000 .................................110

4.20.6.18 MUB, Memory Upper Base: A=28,1.0.28, R=0000_0000 ........................................................110

4.20.6.19 MUL, Memory Upper Limit Register: A=2C,1.0.2C, R=0000_0000 ........................................111

4.20.6.20 IOUBL, I/O Upper Base and Limit Register: A=30,1.0.30, R=0000_0000 ................................111

4.20.6.21 ILIP, Interrupt Line/Pin Register: A=3C,1.0.3C, R=0000...........................................................111

4.20.6.22 Bridge Control Register: A=3E,1.0.3E, R=0000 ..........................................................................111

4.20.6.23 HBPCIR, Host to BPCI Remap Register: A=40,1.0.40, R=E4..................................................112

4.20.6.24 BIRQRC[A:D], BPIRQx Route Control Registers: A=60-63, 1.0.60-1.0.63, R=80...................112

4.20.6.25 BMTT, Backplane Multi-Transaction Timer Register: A=70, 1.0.70, R=20..............................113

4.21 BACKPLANE PCI CONFIGURATION REGISTERS - BACKPLANE VIEW.................................................113

4.21.1 BVID, Vendor Identification Register: A=0, 1.0.80, R=1331...................................................115

4.21.2 BDID, Device Identification Register: A=2, 1.0.82, R=8210 ...................................................115

4.21.3 BPCICMD, BPCI Command Register: A=4, 1.0.84, R=0000...................................................116

4.21.4 BPCISTS, BPCI Status Register: A=6, 1.0.86, R=0230.............................................................117

4.21.5 BRID, Revision Identification Register: A=8, 1.0.88, R=00.....................................................117

4.21.6 BCLASSC, Class Code Register: A=9, 1.0.89:............................................................................118

4.21.7 BCLS, Cache Line Size Register: A=C, 1.0.8C, R=08 ...............................................................118

4.21.8 BMLT, Master Latency Timer: A=D, 1.0.8D, R=00 ....................................................................118

4.21.9 BHT, Header Type: A=E, 1.0.8E, R=00 ........................................................................................118

4.21.10 BBIST, BIST Register Timer: A=F, 1.0.8F, R=00....................................................................119

4.21.11 BAR0, Base Address Register 0: A=10, 1.0.90, R=0000_0000 ...........................................120

4.21.12 BAR1, Base Address Register 1: A=14, 1.0.94, R=0000_0000 ...........................................121

4.21.13 BSUBVID, Sub-Vendor Identification Register: A=2C, 1.0.AC, R=0000..........................121

4.21.14 BSUBDID, Sub-Device Identification Register: A=2E, 1.0.AE, R=0000 ...........................121

4.21.15 RBAR, ROM Base Address Register: A=30, 1.0.B0, R=0000_0000....................................122

4.21.16 CPR, Capabilities Pointer Register: A=34,1.0.B4, R=50 ....................................................122

4.21.17 ILIP, Interrupt Line/Interrupt Pin Register: A=3C,1.0.BC, R=0000..................................123

4.21.18 PGNTLAT, BPCI Arbitration Grant/Latency Register: A=3E,1.0.BE, R=0000................124

4.21.19 MRBAR0, Memory Remap Base Address Register 0: A=40, 1.0.C0, R=0000_0000 .......124

4.21.20 MRBAR1, Memory Remap Base Address Register 1: A=44, 1.0.C4, R=0000_0000 .......125

4.21.21 RRBAR, ROM Remap Base Address Register: A=48, 1.0.C8, R=0000_0000 ...................125

4.21.22 MBPC, Miscellaneous BPCI Control: A=4C,1.0.CC, R=00................................................126

4.21.23 HSC, Hot Swap Capability Register: A=50,1.0.D0, R=0000_0006...................................127

4.21.24 LPID, Local to BPCI Interrupt Doorbell Register: A=60,1.0.E0, R=0000_0000............127

4.21.25 PLID, PCI to Local Interrupt Doorbell Register: A=64,1.0.E4, R=0000_0000...............128

4.21.26 BAAR, Backplane Abort Address Register: A=7C,1.0.FC, R=0000_0000 ......................128

4.22 EMBEDDED 16550 UART REGISTER DESCRIPTIONS:.............................................................................128

4.22.1 RBR/THR, Receiver Buffer Register/Transmitter Holding Register.........................................129

4.22.2 DLL, Divisor Latch Lower: A=2F8 & 3F8 (DLAB = 1), R=xxxx.............................................130

4.22.3 IER, Interrupt Enable Register: A=2F9 & 3F9 (DLAB = 0), R=xx.........................................130

4.22.4 FCR, FIFO Control Register: A=2FA & 3FA, R=xx..................................................................131

4.22.5 IIR, Interrupt Identification Register: A=2FA & 3FA, R=xx....................................................132


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4.22.6 LCR, Line Control Register: A=2FB & 3FB, R=xx....................................................................133

4.22.7 MCR, Modem Control Register: A=2FC & 3FC, R=xx.............................................................134

4.22.8 LSR, Line Status Register: A=2FD & 3FD, R=xx.......................................................................134

4.22.9 FTR, Factory Test Register: A=2FD&3FD, R=xx ......................................................................135

4.22.10 MSR, Modem Status Register: A=2FE & 3FE, R=xx.............................................................135

4.22.11 SPR, Scratch Pad Register, A=2FF/3FF, R=xx....................................................................135

4.23 EMBEDDED 82C206 PERIPHERAL REGISTER DESCRIPTIONS:...............................................................136

4.23.1 TCW - Timer Control Word Register: A=43, R=xx .....................................................................137

4.23.2 Read Back Command.......................................................................................................................138

4.23.3 Counter Latch Command ................................................................................................................139

4.23.4 Interval Timer Status Byte Format Register,................................................................................140

4.23.5 Counter Access Ports Register, ......................................................................................................141

4.24 8259 COMPATIBLE INTERRUPT CONTROLLER I/O REGISTERS...........................................................141

4.24.1 ICW1 - Initialization Command Word 1 Register: A=20 (Master), A0 (Slave),...................142

4.24.2 ICW2 - Initialization Command Word 2 Register: A=21 (Master), A1 (Slave),...................143

4.24.3 ICW3 - Master Controller Initialization Command Word 3 Register: A=21, R=xx.............143

4.24.4 ICW3 - Slave Controller Initialization Command Word 3 Register: A=A1, R=xx ...............144

4.24.5 ICW4 - Initialization Command Word 4 Register: A=21 (Master), A1 (Slave),...................144

4.24.6 OCW1 - Operational Control Word 1 (Interrupt Mask) Register: ..........................................144

4.24.7 OCW2 - Operational Control Word 2 Register: A=20 (Master), A0 (Slave),.......................145

4.24.8 OCW3 - Operational Control Word 3 Register: A=20 (Master), A0 (Slave),.......................146

4.24.9 ELCR1 - Master Controller Edge/Level Triggered Register: A=4D0, R=00 ........................147

4.24.10 ELCR2 - Slave Controller Edge/Level Triggered Register: A=4D1, R=00.......................147

4.25 8237 COMPATIBLE DMA I/O REGISTERS................................................................................................148

4.25.1 DMA Base and Current Address Registers...................................................................................150

4.25.2 DMA Base and Current Count Registers......................................................................................151

4.25.3 DMA Memory Low Page Registers ................................................................................................151

4.25.4 DMA Command Register .................................................................................................................152

4.25.5 DMA Status Register ........................................................................................................................152

4.25.6 DMA Request Register .....................................................................................................................153

4.25.7 DMA Write Single Mask Register ..................................................................................................154

4.25.8 DMA Channel Mode Register.........................................................................................................155

4.25.9 DMA Clear Byte Pointer Register..................................................................................................156

4.25.10 DMA Master Clear Register .......................................................................................................156

4.25.11 DMA Clear Mask Register..........................................................................................................156

4.25.12 DMA Write All Mask Register ....................................................................................................157

4.26 RTC I/O REGISTERS.....................................................................................................................................157

4.26.1 RTC Indexed Registers.....................................................................................................................158

4.26.2 Configuration/Control Registers...................................................................................................159

4.26.2.1 Register A, RTC Index = 0A........................................................................................................159

4.26.2.2 Register B - General Configuration, RTC Index = 0B, R=X0000XXXb.....................................160

4.26.2.3 Register C - Flag Register, RTC Index = 0C, R=00......................................................................161

4.26.2.4 Register D - Flag Register, RTC index = 0D ................................................................................161

5 FUNCTIONAL DESCRIPTION .......................................................................................................................162

5.1 HIGH THROUGHPUT DATA FLOW TOPOLOGY.......................................................................................162

5.2 DUAL PCI BRIDGE CAPABILITIES.............................................................................................................162

5.2.1 Backplane PCI Modes .....................................................................................................................162

5.2.2 Backplane PCI Arbiter Modes .......................................................................................................163

5.2.2.1 Central Resource Mode.....................................................................................................................163

5.2.2.2 Peripheral Bridge Mode ....................................................................................................................164

5.2.3 Views of Backplane PCI Bridge Modes........................................................................................165

5.2.4 Backplane PCI Alternate Configuration .....................................................................................166

5.3 BPCI PERIPHERAL BRIDGE CAPABILITIES..............................................................................................167


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5.4 BPCI TARGET SUPPORT .............................................................................................................................167

5.5 DOORBELL INTERRUPT SUPPORT ...........................................................................................................170

5.6 HOT SWAP FRIENDLY SUPPORT ..............................................................................................................171

5.7 BPCI/SDRAM 4-CHANNEL DMA CONTROLLER...................................................................................172

5.7.1 Direct-Host Control Mode ..............................................................................................................172

5.7.2 DMA chaining mode.........................................................................................................................174

5.8 LPCI BRIDGE CAPABILITIES......................................................................................................................174

5.9 LPCI TARGET SUPPORT .............................................................................................................................174

5.10 HOST PROCESSOR BUS INTERFACE ...........................................................................................................176

5.11 36 ADDRESS-BIT REFERENCES...................................................................................................................177

5.12 SDRAM REFERENCES.................................................................................................................................177

5.13 BACKPLANE PCI REFERENCES..................................................................................................................177

5.14 LPCI REFERENCES.......................................................................................................................................177

5.15 INTERNAL REGISTERS.................................................................................................................................178

5.16 SPECIAL CYCLES.........................................................................................................................................178

5.17 DMA AND PCI INITIATED SDRAM CYCLES.........................................................................................178

5.18 LOCKED CYCLES..........................................................................................................................................178

5.19 SDRAM MEMORY CONTROLLER............................................................................................................178

5.20 BOOT ROM/FLASH ROM INTERFACE .....................................................................................................182

5.21 ULTRA DMA/66 ENHANCED IDE INTERFACE........................................................................................183

5.22 ENHANCED UNIVERSAL SERIAL BUS (USB) CONTROLLER..................................................................183

5.23 CORE PC LOGIC............................................................................................................................................184

5.24 INTERRUPT CONTROLLERS.......................................................................................................................184

5.25 8259 OVERVIEW ...........................................................................................................................................184

5.25.1 Interrupt Controller I/O Register Location .................................................................................185

5.25.2 Interrupt Handling ...........................................................................................................................186

5.25.2.1 Generating Interrupts ...................................................................................................................186

5.25.2.2 Acknowledging Interrupts............................................................................................................187

5.25.2.3 Hardware/Software Interrupt Sequence........................................................................................187

5.25.3 Initialization Command Words (ICW) ..........................................................................................187

5.25.3.1 ICW1 ............................................................................................................................................188

5.25.3.2 ICW2 ............................................................................................................................................188

5.25.3.3 ICW3 ............................................................................................................................................188

5.25.3.4 ICW4 ............................................................................................................................................188

5.25.4 Operation Command Words (OCW) ..............................................................................................188

5.25.5 Modes of Operation..........................................................................................................................188

5.25.5.1 Fully Nested Mode ......................................................................................................................188

5.25.5.2 Special Fully Nested Mode..........................................................................................................189

5.25.5.3 Automatic Rotation Mode (Equal Priority Devices) ...................................................................189

5.25.5.4 Specific Rotation Mode (Specific Priority)..................................................................................189

5.25.5.5 Poll Mode.....................................................................................................................................189

5.25.5.6 Cascade Mode ..............................................................................................................................190

5.25.5.7 Edge and Level Triggered Mode ...................................................................................................190

5.25.5.8 End of Interrupt Operations.........................................................................................................190

5.25.5.9 Normal End of Interrupt...............................................................................................................190

5.25.5.10 Automatic End of Interrupt Mode...............................................................................................190

5.25.6 Masking Interrupts...........................................................................................................................191

5.25.6.1 Masking on an Individual Interrupt Request................................................................................191

5.25.6.2 Special Mask Mode......................................................................................................................191

5.25.7 Steering PCI Interrupts....................................................................................................................191

5.26 SERIAL IRQ (SERIRQ) SUPPORT ..............................................................................................................191

5.26.1 SERIRQ Protocol ..............................................................................................................................191

5.26.1.1 Quiet (Active) Mode Start Frame ................................................................................................192

5.26.1.2 Continuous (Idle) Mode Start Frame ...........................................................................................192


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5.26.1.3 Data Frame ...................................................................................................................................192

5.26.1.4 Stop Frame ...................................................................................................................................192

5.27 8237 COMPATIBLE DMA...........................................................................................................................193

5.27.1 8237 Compatible DMA Overview..................................................................................................194

5.27.2 DMA Channel Arbitration ..............................................................................................................194

5.27.3 Special Cases in Address / Count..................................................................................................195

5.27.3.1 Address Overrun / Under-run.......................................................................................................195

5.27.3.2 16 Bit Channels ............................................................................................................................195

5.27.4 Theory of Operation for PC/PCI....................................................................................................195

5.27.4.1 Overview ......................................................................................................................................195

5.27.4.2 Protocol ........................................................................................................................................195

5.27.4.3 PC/PCI DMA Cycles...................................................................................................................198

5.27.4.3.1 Overview ..................................................................................................................................198

5.27.4.3.2 DMA Addresses ......................................................................................................................198

5.27.4.3.3 DMA Data / Byte Enable Generation......................................................................................198

5.27.4.3.4 DMA Cycle Termination.........................................................................................................199

5.27.4.3.5 Normal DMA Cycles...............................................................................................................199

5.27.4.3.6 Normal DMA Cycles with Terminal Count ............................................................................200

5.27.4.3.7 Verify DMA Cycles ................................................................................................................201

5.28 8254 COMPATIBLE TIMER/COUNTER......................................................................................................202

5.28.1 Counter 0, System Timer..................................................................................................................203

5.28.2 Counter 1............................................................................................................................................203

5.28.3 Counter 2, Speaker Tone.................................................................................................................203

5.28.4 Timer Programming..........................................................................................................................203

5.28.5 Reading from the Interval Timer ....................................................................................................204

5.28.5.1 Simple Read..................................................................................................................................204

5.28.5.2 Counter Latch Command..............................................................................................................204

5.28.5.3 Read Back Command....................................................................................................................205

5.29 REAL TIME CLOCK......................................................................................................................................205

5.29.1 RTC Overview....................................................................................................................................205

5.29.2 Update Cycles....................................................................................................................................206

5.29.3 Interrupts............................................................................................................................................206

5.30 PC SPEAKER INTERFACE ...........................................................................................................................206

5.31 MISCELLANEOUS LOGIC (PORT A, PORT B, & NPX)...............................................................................206

5.32 INTEGRATED PERIPHERALS......................................................................................................................206

5.33 16C550 UARTS.............................................................................................................................................206

5.34 DIGITAL I/O..................................................................................................................................................207

5.35 WATCHDOG TIMER SUPPORT ..................................................................................................................207

5.36 SMBUS...........................................................................................................................................................208

5.37 KEYBOARD/MOUSE CONTROLLER...........................................................................................................208

5.37.1 Keyboard Controller Command Descriptions............................................................................209

5.37.2 GATEA20 and RESET ......................................................................................................................211

5.37.3 Keyboard and Mouse Interface......................................................................................................211

5.38 POWER MANAGEMENT ..............................................................................................................................212

5.39 POWER MANAGEMENT SUPPORT ............................................................................................................212

5.40 LEGACY POWER MANAGEMENT/SMI SUPPORT ...................................................................................214

6 82600 SYSTEM DESIGN CONSIDERATIONS ...........................................................................................216

6.1 CLOCKING CONSIDERATIONS....................................................................................................................216

6.2 3.3V/5V OPERATION ...................................................................................................................................216

6.3 RESET LOGIC................................................................................................................................................216

6.4 BIOS NOTE....................................................................................................................................................216

6.5 RTC OSCILLATOR RECOMMENDED CONFIGURATION..........................................................................217

6.6 NMI PIN IMPLEMENTATION NOTE.........................................................................................................218


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7 ELECTRICAL CHARACTERISTICS .............................................................................................................219

7.1 MAXIMUM RATINGS .....................................................................................................................................219

7.2 DC CHARACTERISTICS: 2.5 VOLT (VDD = 2.5V ? 10%, TC = -40?C TO +85?C) ..............................219

7.3 AC CHARACTERISTICS.................................................................................................................................223

7.3.1 Clock Timing .....................................................................................................................................223

7.3.1.1 HCLK................................................................................................................................................224

7.3.1.2 BPCLK and LPCLK Clocks .............................................................................................................224

7.3.1.3 Other Clocks .....................................................................................................................................224

7.3.2 SDRAM Timing..................................................................................................................................225

7.3.3 Host Interface Timing.......................................................................................................................225

7.3.4 BPCI Interface Timing......................................................................................................................226

7.3.5 LPCI Interface Timing......................................................................................................................227

7.3.6 EIDE Interface Timing......................................................................................................................228

7.3.7 Ultra DMA/33 Timing ......................................................................................................................228

7.3.8 USB Interface Timing .......................................................................................................................228

7.3.9 SMBUS Interface Timing .................................................................................................................229

7.3.10 Miscellaneous Timing......................................................................................................................230

7.4 AC TIMING DIAGRAMS ................................................................................................................................231

8 PINOUT AND PACKAGE INFORMATION..................................................................................................241

8.1 PIN LIST BY PIN NAME...............................................................................................................................243

8.2 PIN LIST BY PAD NUMBER.........................................................................................................................251

THERMAL SPECIFICATIONS.................................................................................................................................260


1 Product Overview

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The RadiSys 82600 High Performance System Controller is a member of the RadiSys family of long-life embedded PC

compatible core logic. The 82600 is designed specifically to support the Intel Celeron, Pentium II and Pentium III

processors with 66MHz, 100MHz and 133MHz system bus frequencies. It is a highly integrated single chip

implementation of all requirements of a high performance Compact PCI Central Resource and Peripheral Bridge

including the North Bridge, PCI to PCI Bridge, South Bridge and a selected set of Super I/O functions targeted at

embedded, PC-compatible systems.

The functional design of the 82600 is based on the familiar and widely understood PC architecture with extensions

required for a cost-effective implementation of an embedded CompactPCI Central Resource or Peripheral Bridge

Processor. The innovative dual PCI bus architecture allows integration of 5 PCI bus based system peripherals such

as a LAN controller, Graphics controller or SCSI controller on a local PCI bus, as well as the interface to up to 7

external peripherals on a completely independent backplane CompactPCI bus, without the performance degradation

encountered in a standard PCI to PCI bridge based system. The integrated Ultra DMA/66 EIDE interface allows

direct connection of 2 EIDE devices such as a disk drive, CD-ROM, DVD-ROM or flash disk. The EIDE interface

communicates with the processor and memory over an internal dedicated I/O path and eliminates loading the PCI bus.

The integrated SDRAM controller supports up to 2GB of main memory to handle large applications and support

quick access to large databases in memory. This memory capacity can eliminate disk swap overhead for data

intensive applications. In addition, the SDRAM controller also incorporates direct flash support on the SDRAM bus.

With the capability to address up to 64MB of flash memory, the BIOS, applications and the embedded OS can all

reside in flash. High performance page mode flash access makes Execute-In-Place practical.

Many embedded CompactPCI applications require the efficient movement of large blocks of data quickly and

efficiently. The 82600 eliminates the data transfer bottleneck inherent in multiple device chipset implementations

utilizing a conventional PCI-to-PCI bridge. To handle data efficiently the 82600 features a star topology data transfer

design. Each device or bus that may need to supply or demand large data transfers has an independent internal bus

connection to the processor and other I/O devices and buses. The devices and buses with their own dedicated data

transfer bus include: the local PCI bus, the backplane PCI bus, EIDE, USB, main memory, and the PC/AT compatible

peripherals. To maintain compatibility with legacy software, the register structure and configuration programming of

the backplane PCI bus looks as if it is behind a transparent PCI-to-PCI bridge that appears to span the Local PCI bus

and the Backplane PCI bus.

To offer complete PC-compatibility, the 82600 contains an integrated 82C206 to implement the PC core logic. This

includes all the legacy PC/AT compatible peripherals including: interrupt controllers (8259s), DMA controllers

(8237s), timer/counter (8254), address mapper (74LS612), and a battery backed RTC. To allow expansion to fullembedded

PC functionality with a minimum of external components and development time, the 82600 includes

complete interfaces for PS/2 mouse and keyboard, COM1 and COM2 ports, and a USB hub with 2 ports.

Embedded designs are often subject to extreme thermal conditions and restricted cooling. For these systems, total

power dissipation is of paramount importance. In an embedded Intel Architecture I/O system, the 82600 replaces 4

components: North Bridge, South Bridge, PCI-to-PCI Bridge and Super I/O. The power dissipation for these devices

is 7.7W typical, while the power dissipation of the 82600 is 2.0W typical for a savings in power dissipation of 5.7W.

In an embedded PC design the 82600 offers a lower cost alternative to conventional PC chipset based systems with

several performance enhancements and no sacrifice in required functionality. With its high level of integration the

82600 offers a significant savings in component cost. The integration of this functionality into a single package

results in significant savings in board space and power. Integration of all the system controller functions into a

single device reduces system development and debug time resulting in a faster time to market as well as improved

system reliability through reduced part count and interconnects.

Advance Information Subject to Change 13


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Figure 1 82600 Block Diagram

Celeron

Pentium II

Pentium III

Processor

Interface

Watchdog

timer

USB Port

SM

Bus

Local PCI

Interface

8254

PS2

Ports

8237s

Standard PC Support

8259s

EIDE interface

Ultra-DMA

GPIO

Clocks, Reset,

Test, Pwrmgt

BP PCI

Interface

SDRAM

Ctrl

14 Subject to Change Advance Information

RTC

COM1

COM2

ECC


Figure 2 Typical 82600 System Block Diagram

LAN #2

Controller

(opt)

Peripherals

EIDE

USB

SMBus

Keyboard/

Mouse

Local PCI bus

LAN #1

Controller

(opt)

1.1 References

Graphics

(opt)

PCI Local Bus Specification Revision 2.2

CompactPCI Specification PICMG 2.0 D3.0

Processor

PSB

82600

Virtual PCI to PCI

Bridge

SCSI

Controller

(opt)

CompactPCI Hot Swap Specification PICMG 2.1 R1.0

System Management Bus Specification Rev 1.1

Universal Serial Bus Specification Rev 1.1

Flash

Backplane PCI bus

COM2/ECC

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Advance Information Subject to Change 15

CompactPCI Slot #2

CompactPCI Slot #3

CompactPCI Slot #4

CompactPCI Slot #5

CompactPCI Slot #6

COM1

CompactPCI Slot #7

CompactPCI Slot #8

SDRAM


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2 Signal Descriptions

2.1 Signal Type Abbreviations

trailing # The named signal is active low.

GTL+ I/O GTL+ input and output (Vref = 1.0V, Vterm = 1.5V)

GTL+ O GTL+ output.

GTL+ I GTL+ input.

lvttl

lvttl in

lvttl out

lvttl I/O

CMOS

CMOS in

CMOS out

CMOS I/O

open drain

Ox

3.3V LVTTL level inputs and outputs (3.3V output swing)

2.5V CMOS level inputs and outputs

Open drain output buffer. Actively drives low. Requires an external pull-up resistor.

x denotes the sink current capability in mA.

Schmitt The input has a Schmitt trigger.

Power Power pin.

PCICLMP

tolerant

Clamped to the PCICLMP power pin.

16 Subject to Change Advance Information


2.2 Clock and Reset Signals

Signal Type Description

HCLK lvttl in Host Clock Input:

BPCLK lvttl in

PCICLMP

tolerant

LPCLK lvttl in

PCICLMP

tolerant

This clock is used to clock the host bus interface and the SDRAM

interface. It is also divided down to provide the clocking for the internal

keyboard controller and the internal UARTs. This clock can be

asynchronous to the PCI clock inputs BPCLK and LPCLK.

Backplane PCI Clock Input:

This is used to clock the BPCI bus interface.

Local PCI Clock Input:

OSCIN lvttl in 14.31818 MHz Clock Input:

PWRGOOD CMOS in

schmitt

TEST# lvttl in

schmitt

This is used to clock the LPCI bus interface including the SERIRQ input.

It is also divided by 2 and used to clock the internal 8237, the legacy

DMA controller.

This clock is divided by 12 to provide a clock to the internal 8254 timers.

This input is also used to generate the 3.5795MHz clock for the Power

Management Timer.

Power Good:

The assertion of this input indicates that system power is stable and that

normal operation may begin. While PWRGOOD is negated, the internal

Real Time Clock megacell is placed in standby, CPURST# is asserted, and

LRST# is asserted.

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When the 82600 is acting as the BPCI Central Resource, negation of

PWRGOOD also causes the BPCI BRST# signal to be asserted.

PWRGOOD must be asserted and the BPCI BRST# signal must be

negated before the 82600 internal reset is negated. To support a hot-swap

capability, PWRGOOD or BPCI BRST# 3-state the BPCI bus output

drivers directly, even if no clocks are applied to the 82600.

The 82600 internally latches its power-up configuration from MA[14:0]

pins as PWRGOOD becomes asserted.

The PWRGOOD input buffer is powered by RTC_VCC and is always

monitoring the state of PWRGOOD even when system power is off.

Test Input:

When pulled low, this pin places the 82600 in a special test mode. This

signal has no user functionality and requires a 10K? pull-up resistor.

Advance Information Subject to Change 17


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2.3 CPU/BUS Signals

Signal Type Description

ADS# GTL+ I/O Address Strobe:

BNR# GTL+ I/O Block Next Request:

BPRI# GTL+ O Priority Bus Agent:

HREQ[4:0]# GTL+ I/O Request Commands:

Connect directly to the corresponding processor output. Indicates that

the processor is driving the first of a two-cycle bus request phase. The

82600 tracks the state of the local bus by monitoring this input at all

times.

This signal is used to control the bus pipeline depth. It is asserted to

stop a bus owner from issuing a new bus request.

Asserted by the 82600 to gain control of the CPU bus. This signal has

priority over CPU bus requests, but cannot override a request that is

necessary to complete a locked access.

These signals encode the basic bus transaction type and are connected

directly to the corresponding signals on the CPU. They are only valid

during the request phase of each transaction. During the first cycle

(ADS# asserted) of each request phase, they encode the transaction as

follows (“a” indicates 36 bit address agents when 1; otherwise 32 bit

address agents are assumed)

00000 Deferred Reply

01000 Special cycles (HREQb[4:0]# and HA[15:8]# must be interpreted)

00001 Reserved (ignored)

01001 Branch Trace message

0a010 Read and Invalidate

0a011 Reserved (treated as memory write if received)

0a100 Code fetch

0a101 Memory write (no retry)

0a110 Memory read

0a111 Memory write (retry allowed)

10000 IO read

10001 IO write

1001x Reserved (ignored)

101xx Reserved (ignored)

11xxx Reserved (ignored)

BR[0]# GTL+ O Symmetric Agent Bus Request:

This signal is only driven low when CPURST# is asserted. It is released

two host clocks after CPURST# is negated.

18 Subject to Change Advance Information


Signal Type Description

DBSY# GTL+ I/O Data Bus BUSY#:

DEFER# GTL+ O Defer:

HLOCK# GTL+ I LOCK:

DRDY# GTL+ I/O Data Ready:

HITM# GTL+ I Hit Modified:

HIT# GTL+ I Hit:

HTRDY# GTL+ I/O Target Ready:

RS[2:0]# GTL+ I/O Response Signals:

Driven by the data bus owner when it requires using the data bus in

burst mode.

Driven by the 82600 to indicate that the current bus transaction will not

be serviced immediately. This allows other accesses to proceed without

waiting for the response to this bus cycle.

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This signal allows semaphores to be implemented in SDRAM. When

asserted, accesses from other DMA sources to the SDRAM are delayed.

Asserted by the initiator each cycle that data is transferred (accepted or

sourced) by the initiator on the data bus.

Indicates that the CPU holds a modified version of the requested data.

Indicates that a non-modified version of the requested data is cached.

Driven by the 82600 as a “target” to indicate that it is ready to

receive/source data. Also viewed as an input when the 82600 is the

access initiator.

Driven by the 82600 as a “target” as follows:

RS[2:0]

000 Idle state

001 Retry response

010 Deferred response

011 Reserved (not driven by the 82600)

100 Hard failure (not driven by the 82600)

101 No data response

110 Implicit writeback

111 Normal data response

Advance Information Subject to Change 19


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Signal Type Description

HA[31:3]# GTL+ I/O Address Bus:

HD[63:0]# GTL+ I/O Data Bus:

CPURST# GTL+ O CPU Reset:

FERR# GTL+ I Floating Point Error:

IGNNE# open drain

O6

A20M# open drain

O6

INIT# open drain

O6

These are the processor’s address lines. These lines are driven by the

82600 during PCI and DMA snoop accesses and are used as inputs at all

other times

These lines are connected to the local processor bus data lines. The

82600 will drive these lines with the read data whenever the 82600 is

servicing the read access to I/O or memory and will accept write data as

input.

This signal is always asserted for a minimum of 1ms beyond the negation

to assertion edge of the PWRGOOD pin. The 82600 will also assert

CPURST# in response to a “warm” LPCI LRST# when the Reset Control

Register at I/O address 0xCF9 enables this. When the 82600 is not

serving as the BPCI Central Resource, CPURST# is always asserted in

response to the BPCI BRST# signal.

This signal is driven active by the CPU to indicate that a floating-point

error has occurred and causes IRQ13 to be generated. IRQ13 is negated

in response to an I/O write to 0xF0 or 0xF1. This signal does not need to

be terminated at a GTL+ level, but will use the 1.0V GTL+ reference level

to determine the 0/1 input level.

Ignore Numeric Error:

This signal is driven active by the 82600 during I/O writes to 0xF0, 0xF1,

if FERR# is active. It remains asserted until FERR# is driven inactive by

the CPU.

A20 Mask:

This signal should be tied directly to A20M# pin of the processor. The

82600 drives this pin from the OR of its internal keyboard controller’s

GATEA20 signal with the Port 92 GATE A20 bit. A20M# is also forced

inactive (high) when the CPU is in SMM mode and is also set inactive

after a INIT# assertion (see INIT# pin description) and will continue to

be forced inactive until the first code execution below 2GB occurs, at

which time the Port92 and keyboard controller bits take effect.

Initialize CPU Only:

This signal should be tied directly to CPU’s INIT pin. This pin is driven

by the 82600 from the OR of its internal keyboard controller’s RESETCPU

pin with the Port 92 Reset CPU bit. This signal is driven active for a

minimum of 64 LPCI clocks.

20 Subject to Change Advance Information


Signal Type Description

NMI(LINT1) open drain

O6

INTR(LINT0) open drain

O6

Non Maskable Interrupt:

This is an active high output that is used to signal to the CPU that either

a non-correctable SDRAM parity error has occurred, or an IOCHCK,

BSERR#, or LSERR# has been detected. This signal is asserted

synchronously to the HCLK and is asserted for a minimum of 2 HCLK

cycles.

Interrupt:

2.4 CPU Signals Not Supported by the 82600

Signal Function Description

This is an active high output that is used to signal an interrupt to the

CPU. This signal is output from the cascaded internal 8259 interrupt

controllers.

HA[35:32]# Address Extended addressing over 4GB

AERR# Address Parity Error Parity protection on the address bus

AP[1:0]# Address Parity Parity protection on the address bus

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BINIT# Bus Initialization Checking for bus protocol violation and protocol recovery mechanism

DEP[7:0]# Data Bus ECC/Parity Enhanced data bus integrity

IERR# Internal Error Direct internal error observation

BERR# Bus Error Unrecoverable error without a bus protocol violation

RP# Request Parity Parity protection on ADS# and PREQ[4:0]#

RSP# Response Parity

Signal

2.5 Power Management Signals

Signal Type Description

STPCLK# open drain

O6

Parity protection on RS[2:0]#

Stop Clock:

This output is driven active by the 82600 to signal to stop the clock to

the CPU. The actual clock frequency change occurs after the 82600 sees

a Stop Grant acknowledge bus cycle. STPCLK# remains asserted for at

least 1ms after clocking has been re-enabled and stabilized to allow the

processor PLL to lock back onto the host clock frequency.

Advance Information Subject to Change 21


R

Signal Type Description

SMI# open drain

O6

PWRBTN# lvttl in PWRBTN#:

2.6 SDRAM Interface Signals

Signal Type Description

System Management Interrupt:

CS[3:0]# lvttl out SDRAM Chip Selects:

BIOSCE# lvttl out BIOS Chip Enable:

BIOSOE# lvttl out BIOS Output Enable:

DQM[7:0]/

FA[8:1]

Connect directly to the corresponding CPU input. This output is

asserted whenever any system management event occurs, or when the

PWRBTN# input is asserted and it is enabled as an external SMI#

expansion pin.

When asserted, this pin can cause an SCI interrupt, an SMI interrupt, a

standby resume event or it can reload the Global Standby Timer. The

exact function is defined by the bits in the Power Management I/O

registers. In each case, this pin is falling edge triggered. To generate the

event, the signal must make be negated and then driven low again.

SDRAM chip selects to support up to four modules of SDRAM.

If MA4 is sampled low during power-on-reset, this output becomes

active when an access falls within the top 512KB, or top 64MB if enabled

by a power on option bit, of the 4GB address range. When this is

asserted, DQM[7:0] and MA14-MA0 carry demultiplexed addresses that

connect directly to a x16 flash device that hooks its data bits to the lower

16 data bits of the SDRAM data bus.

This signal is asserted during a read to a flash device on the SDRAM

bus.

lvttl out SDRAM Data Qualifier Mask:

These signals qualify both reads (as an output enable) and writes (as a

per byte write mask). When a DQMx is low, the corresponding byte lane

is enabled to be read/written. When a DQMx is high, the corresponding

byte lane is “masked” and reading and writing to the byte lane is

disabled.

For a flash device, these signals carry A8-A1 address information.

22 Subject to Change Advance Information


Signal Type Description

MA[14:0]/

FA[23:9]

lvttl out Multiplexed Address:

WE# lvttl out DRAM Write Enable:

SRAS#/FA25 lvttl out SDRAM Row Address Strobe:

SCAS#/FA24 lvttl out SDRAM Column Address Strobe

CKEA,CKEB lvttl out SDRAM Clock Enable:

MD[63:0] lvttl I/O Memory Data:

MDP[7:0] lvttl I/O Memory Data Parity:

2.7 Local PCI bus interface Signals

Signal Type Description

LAD[31:0] lvttl I/O

PCICLMP

tolerant

IO18

R

These signals directly drive the address inputs of the SDRAM

subsystem. When accessing a RAS bank configured for a x16 flash

device, these signals become A23-A9. Additionally, during a hardware

reset, these signals are 3-stated immediately and a power-up option latch

is loaded from these signals. The options can be defined by using 2.2K

pull-ups or pull-downs external to the 82600 to define the appropriate

power-up/reset behavior.

The 82600 asserts this signal during a write to SDRAM or a flash device

on the SDRAM bus.

For SDRAM accesses, this signal is asserted to latch the SDRAM’s row

address. For a boot block flash device, these signals carry A25 address

information.

When asserted this latches the SDRAM’s column address. For a boot

block flash device, these signals carry A24 address information.

These pins are negated to place the SDRAM into a power down mode.

These signals connect to the memory data bus. These signals include

internal pull-downs

These 8 bits carry an ECC code for the 64-bit memory data bus. When

ECC is enabled, the 82600 memory controller converts partial writes (7

bytes or less) into a read-modify-write cycle. These signals are

multiplexed with the COM2 port signals.

Local Address and Data:

These are the local PCI bus’s multiplexed address and data lines.

Address is driven with LFRAME# assertion. Data is written or received

on subsequent cycles.

Advance Information Subject to Change 23


R

Signal Type Description

LC/BE[3:0]# lvttl I/O

PCICLMP

tolerant

IO18

LFRAME# lvttl I/O

PCICLMP

tolerant

IO18

LDEVSEL# lvttl I/O

PCICLMP

tolerant

IO18

LIRDY# lvttl I/O

PCICLMP

tolerant

IO18

LTRDY# lvttl I/O

PCICLMP

tolerant

IO18

LSTOP# lvttl I/O

PCICLMP

tolerant

IO18

LPAR lvttl out

PCICLMP

tolerant

IO18

LSERR# lvttl out

PCICLMP

tolerant

IO18

Local Command/Byte Enables

These signals are interpreted as a PCI command when LFRAME# is first

asserted. They qualify the LPCI data byte lanes that are valid in

subsequent cycles. LC/BE[0]# is associated with LAD[7:0], LC/BE[1]# is

associated with LAD[15:8], LC/BE[2]# is associated with LAD[23:16],

LC/BE[3]# is associated with LAD[31:24].

Local Frame:

During the cycle that LFRAME# is first asserted, the LPCI initiator

drives an address/command combination onto the LAD and LC/BE lines.

This signal stays asserted during a burst data transfer until the last data

transfer phase at which time it is negated. This signal is also negated

when the LPCI bus is idle.

Local Device Select:

This signal is asserted by the 82600 using “medium” timing if an LPCI

memory access matches an address mapped to the host’s SDRAM.

Local Initiator Ready:

The 82600 asserts this when it is ready to drive (write) or accept (read)

more data on an 82600 initiated access. As a target, this input causes the

82600 to wait until this signal is asserted to accept new data (write) or to

drive the next piece of data (read).

Local Target Ready:

As a target of a LPCI access, the 82600 asserts this when it is ready to

drive (read) or accept (write) more data. On an 82600 initiated access, this

input causes the 82600 to wait until this signal is asserted to accept new

data (read) or to drive the next piece of data (write).

Both LTRDY# and LIRDY# must be asserted in the same cycle to

advance a LPCI bus access to the next piece of data or to terminate the

access.

Local Stop:

This signal is a asserted by the LPCI target to stop the current

transaction.

Local Parity:

This is a parity bit that checks LAD[31:0] and LC/BE[3:0]#. The 82600

drives even parity onto this signal whenever it is driving the LAD and

LC/BE lines. The 82600 does not check LPAR.

Local System Error:

The 82600 can generate an NMI in response to an LSERR# assertion if

enabled by bit 2 of the PortB Register (0x61).

24 Subject to Change Advance Information


Signal Type Description

LREQ[4:0]# lvttl in

PCICLMP

tolerant

LGNT[4:0]# lvttl I/O

O9

LRST# lvttl out

O18

LPIRQ[A:D]# lvttl in

PCICLMP

tolerant

SERIRQ lvttl I/O

open drain

Local PCI Request:

These signals are input only to the 82600 internal bus arbiter. The 82600

local PCI target will not respond to any LPCI configuration cycles

(IDSEL from the LPCI interface is not supported in this mode). LREQ3#

can also be configured to support an ISA bridge REQ# function.

Local PCI Grant:

These signals are output only from the 82600 internal bus arbiter and are

asserted to grant access to the LPCI bus in response to the respective

bus request signals (LREQ[4:0]#). LGNT3# can also be configured to

support the ISA bridge GNT# function. These pins are not 5V tolerant.

Local PCI Reset:

In response to hardware reset (see Reset Logic section), this signal is

driven asserted by the 82600 and remains asserted for a minimum of 1ms

past the assertion edge of PWRGOOD. The 82600 may also reset the

LPCI interface through the use of the Reset Control Register, 0xCF9.

These pins are not 5V tolerant.

Local PCI Interrupt Requests:

R

All four signals are treated as level sensitive LPCI interrupt inputs that

can be individually steered to one or more interrupt request inputs of the

embedded 8259.

Serialized Interrupt Request:

2.8 Backplane PCI Bus Interface Signals

Signal Type Description

BAD[31:0] lvttl I/O

PCICLMP

tolerant

IO18

BC/BE[3:0]# lvttl I/O

PCICLMP

tolerant

IO18

All ISA bus interrupts are multiplexed into this one pin using a protocol

described in the serial interrupt section. This signal is sampled in the

LPCLK domain and is only driven at the beginning of an interrupt

“frame” to signal its start.

Backplane Address and Data:

These are the backplane PCI bus’s multiplexed address and data lines.

Address is driven with BFRAME# assertion. Data is written or received

on subsequent cycles.

Backplane Command/Byte Enables:

These signals are interpreted as a BPCI command when BFRAME# is

first asserted. They qualify the BPCI data byte lanes that are valid in

subsequent cycles. BC/BE[0]# is associated with BAD[7:0], BC/BE[1]#

is associated with BAD[15:8], BC/BE[2]# is associated with BAD[23:16],

BC/BE[3]# is associated with BAD[31:24].

Advance Information Subject to Change 25


R

Signal Type Description

BFRAME# lvttl I/O

PCICLMP

tolerant

IO18

BDEVSEL# lvttl I/O

PCICLMP

tolerant

IO18

BIRDY# lvttl I/O

PCICLMP

tolerant

IO18

BTRDY# lvttl I/O

PCICLMP

tolerant

IO18

BSTOP# lvttl I/O

PCICLMP

tolerant

IO18

BPAR lvttl out

PCICLMP

tolerant

BSERR# lvttl I/O

Open Drain

PCICLMP

tolerant

O18

Backplane Frame:

During the cycle that BFRAME# is first asserted, the BPCI initiator

drives an address/command combination onto the BAD and BC/BE lines.

This signal stays asserted during a burst data transfer until the last data

transfer phase at which time it is negated. This signal is also negated

when the BPCI bus is idle.

Backplane Device Select:

This signal is asserted by the 82600 using “medium” timing if a BPCI

memory access matches a BPCI BAR and the translated address falls in

the host’s SDRAM address space.

Backplane Initiator Ready:

The 82600 asserts this when it is ready to drive (write) or accept (read)

more data on a 82600 initiated access. As a target, this input causes the

82600 to wait until this signal is asserted to accept new data (write) or to

drive the next piece of data (read).

Backplane Target Ready:

As a target of a BPCI access, the 82600 asserts this when it is ready to

drive (read) or accept (write) more data. On an 82600 initiated access, this

input causes the 82600 to wait until this signal is asserted to accept new

data (read) or to drive the next piece of data (write).

Both BTRDY# and BIRDY# must be asserted in the same cycle to

advance a BPCI bus access to the next piece of data or to terminate the

access.

Backplane Stop:

This signal is a asserted by the BPCI target to stop the current

transaction

Backplane Parity:

This is a parity bit that checks BAD[31:0] and BC/BE[3:0]#. The 82600

drives even parity onto this signal whenever it is driving the BAD and

BC/BE lines. The 82600 does not check BPAR.

Backplane System Error:

The 82600 can generate an NMI in response to a BSERR# assertion if the

BSERRNMI enable bit is set in the P2P Bridge Control Register. The

82600 will drive BSERR# asserted when it detects a multi-bit SDRAM

parity error in response to any SDRAM request type (Host, DMA, LPCI

or BPCI), if enabled by bit 3 of the Error Address Register.

26 Subject to Change Advance Information


Signal Type Description

BREQ[6:3]#/

DI[19:16]

BREQ[2]#/

EJECTSTS

BREQ[1]#/

IDSEL

BREQ[0]#/

REQ#

BGNT[6:3]#/

DIO[23:20]

BGNT[2]#/

LEDOUT

BGNT[1]#/

ENUM#

BGNT[0]#/

GNT#

lvttl in

PCICLMP

tolerant

lvttl I/O

O9

PCICLMP

tolerant

BRST# lvttl I/O

PCICLMP

tolerant

IO18

Backplane PCI Request:

R

When the 82600 is acting as the BPCI Central Resource, these signals are

inputs to the 82600 internal bus arbiter. When the 82600 is configured as

the Peripheral Bridge:

1) The internal arbiter is disabled

2) The BREQ0# pin becomes the REQ# output signal that is serviced

by the external bus arbiter, indicating that the 82600 is requesting

bus mastership

3) The BREQ1# pin becomes the IDSEL input that should be tied to a

unique (per PCI system) PCI AD line for PCI configuration purposes

4) The BREQ2# pin becomes a “hot swap” Ejector status signal,

EJECTSTS. A high on the EJECTSTS pin indicates that the ejector

is closed/locked. A low on the EJECTSTS pin indicates that the

ejector is unlocked/open.

When configured as the Central Resource, the 82600 will not respond to

any BPCI configuration cycles because IDSEL from the BPCI interface is

not supported in this mode.

Backplane PCI Grant:

When the 82600 is acting as the BPCI Central Resource, these signals are

outputs from the 82600 internal bus arbiter and are asserted to grant

access to the BPCI bus in response to the respective bus request signals

(BREQ[6:0}#). When the 82600 is configured as the Peripheral Bridge, its

internal arbiter is disabled and the BGNT0# is configured to be a BPCI

bus grant input signal (GNT#). When REQ# is asserted by the 82600 to

gain ownership of the BPCI bus, it waits for a GNT# signal before

initiating a BPCI bus master cycle. In Peripheral Bridge mode BGNT2#

and BGNT1# also take on the Hot Swap Friendly pin functions LEDOUT

and ENUM#. LEDOUT is driven active (high) by the logical OR of three

signals: PWRGOOD being inactive. BRST# being active, or the LED

On/Off bit being set in the Hot Swap Capabilities register. ENUM# acts

as an open drain pin and is driven low whenever the ENUM Insert or

ENUM Extract Status bits are set in conjunction with the ENUM Mask

being 0.

Backplane PCI Reset:

When the 82600 is configured as the BPCI Central Resource, this signal

is driven asserted by the 82600 for a minimum of 1ms in response to a

hardware reset. It is configured as input when the 82600 is configured as

a BPCI Peripheral Bridge. In this latter case, BRST# always resets the

82600 and causes a CPURST to be asserted to the local processor. As a

BPCI Central Resource, the 82600 may also reset its BPCI interface

through the use of the Reset Control Register, 0xCF9.

Advance Information Subject to Change 27


R

Signal Type Description

BPIRQ[A:D]#/

UIRQ[A:D]#

lvttl in

lvttl I/O

PCICLMP

tolerant

IO18

Backplane PCI Interrupt Requests:

2.9 Real Time Clock Interface Signals

Signal Type Description

RTCX1 XTALIN Crystal Input:

RTCX2 CMOS I/O

drives

crystal only

When the 82600 is configured as the BPCI bus Central Resource, all four

signals are treated as inputs for the level sensitive PCI interrupts that

can be individually steered to one or more interrupt request inputs of the

embedded 8259.

When configured as the Peripheral Bridge, one of the UIRQ lines

becomes a PIRQx output (see Interrupt Line/Interrupt Pin Register, 0x3C)

that the 82600 can assert from an internal register. The remaining three

pins are treated as utility level sensitive interrupts that may be steered to

one or more interrupt request inputs of the embedded 8259.

This pin is only used as input to drive the output stage of the RTCX2

pin. This pin, taken together with the RTCX2 pin, is used to generate a

32.768 KHz crystal oscillator for the internal Real Time Clock megacell.

When using an external oscillator, this pin should be connected to the

oscillator and the RTCX2 pin should be a “no-connect”.

This input buffer is powered by RTCVDD and is active even when

system power is off.

Crystal Output:

This pin is the output side of the 32.768 KHz crystal oscillator for the

internal Real Time Clock megacell. This output should only be connected

to a crystal, since it doesn’t have the ability to drive other loads. To

supply an external 32.768 KHz clock, RTCX2 should be a “no-connect”

and the external clock should instead be connected to the RTCX1 input

pin.

The 82600 requires a 32.768 KHz clock even if using an external RTC

chip. This clock is needed for watchdog timing, SMBus (I 2 C) operation

and as the clock for the Global Standby/SMI timer. When not using the

internal RTC, a 50.0 KHz or lower frequency must still be supplied to this

pin while the system is powered on.

This output buffer is powered by RTCVDD and is active even when

system power is off.

28 Subject to Change Advance Information


Signal Type Description

RTCPS CMOS in

IC

Real Time Clock Power Sense:

2.10 Keyboard/USB Interface Signals

Signal Type Description

KCLK CMOS I/O

open drain

IO6

Schmitt

KDATA CMOS I/O

open drain

IO6

Schmitt

MCLK CMOS I/O

IO3

Schmitt

MDATA CMOS I/O

IO3

Schmitt

R

This input, when negated, clears the VRT bit in Register D of the internal

Real Time Clock megacell. In addition it clears the RTC RAM. This

indicates that RTC battery power has failed, and that the RTC no longer

has valid RAM or time.

This input buffer is powered by RTCVDD and is active even when

system power is off.

Keyboard Clock:

This bi-directional open drain signal implements the IBM PS/2 protocol

for the keyboard clock.

Keyboard Data:

This bi-directional open drain signal implements the IBM PS/2 protocol

for keyboard data.

Mouse Clock:

This bi-directional open drain signal implements the IBM PS/2 protocol

for the mouse clock.

Mouse Data:

CLK48 CMOS in 48Mhz Clock:

USBP1+,USBP1- CMOS I/O

IO3

This bi-directional open drain signal implements the IBM PS/2 protocol

for mouse data.

This input is used to clock the Universal Serial Bus block.

Universal Serial Bus Data:

These are the USB differential signaling data lines for USB port 1.

USBOC1# CMOS in Universal Serial Bus Over Current:

USBP0+,USBP0- CMOS I/O

IO3

This signal when asserted disables the USBP1+ and USBP1- signals and

USB port 1.

Universal Serial Bus Data:

These are the USB differential signaling data lines for USB port 0.

Advance Information Subject to Change 29


R

Signal Type Description

USBOC0# CMOS in Universal Serial Bus Over Current:

2.11 COM ports interface

Signal Type Description

TXD1/IRTX/

DIO[24]

RXD1/IRRX/DIO[

25]

RTS1#/

DIO[26]

CTS1#/

DIO[27]

DCD1#/

DIO[28]

This signal when asserted disables the USBP0+ and USBP0- signals and

USB port 0.

lvttl I/O Transmit Data:

The transmitter uses this pin to shift serial data out. Data is transmitted

least significant bit first. In this mode, the pin is an output only.

When configured for infrared operation (IRTX), the 82600 modulates the

serial output connection of the internal 16C550 and outputs this to the

pin. Data is transmitted least significant bit first.

lvttl I/O Receive Data:

When COM1 is disabled, this pin is configured as DIO[24].

The receiver uses this pin to shift serial data in. Data is received least

significant bit first. In this mode, the pin is an input only.

When configured for infrared operation (IRRX), this pin receives the

infrared modulated version of a serial bit stream. The 82600 demodulates

this and presents it to the internal 16C550 serial input connection. Data is

received least significant bit first.

When COM1 is disabled, this pin is configured as DIO[25].

lvttl I/O Request To Send:

Indicates to the modem or data set that the UART is ready to exchange

data. In this mode, the pin is an output only.

lvttl I/O Clear to Send:

When COM1 is disabled, this pin is configured as DIO[26].

Indicates that the modem or data set is ready to exchange data with

UART.

When COM1 is disabled, this pin is configured as DIO[27].

lvttl I/O Data Carrier Detect:

Indicates that modem or data set is ready to establish the

communications link with the UART. In this mode, the pin is an input

only.

When COM1 is disabled, this pin is configured as DIO[28].

30 Subject to Change Advance Information


Signal Type Description

RI1#/

DIO[29]

DTR1#/

DIO[30]

DSR1#/

DIO[31]

lvttl I/O Ring Indicator:

Indicates that the modem or data set has detected a telephone-ringing

signal. In this mode, the pin is an input only.

When COM1 is disabled, this pin is configured as DIO[29].

lvttl I/O Data Terminal Ready:

Indicates to the modem or data set that the UART channel is ready to

establish a communications link. In this mode the pin is an output only.

When COM1 is disabled, this pin is configured as DIO[30].

lvttl I/O Data Set Ready:

RXD2/MDP0 lvttl I/O Receive Data:

TXD2/MDP1 lvttl I/O Transmit Data:

CTS2#/MDP2 lvttl I/O Clear to Send:

RTS2#/MDP3 lvttl I/O Request To Send:

Indicates that the modem or data set is ready to establish the

communications link with the UART. In this mode the pin is input only.

When COM1 is disabled, this pin is configured as DIO[31].

The receiver uses this pin to shift serial data in. Data is received least

significant bit first. In this mode, the pin is an input only.

When COM2 is disabled and ECC is enabled, this pin serves as ECC

parity bit 0, MDP0.

The transmitter uses this pin to shift serial data out. Data is transmitted

least significant bit first. In this mode, the pin is an output only.

When COM2 is disabled and ECC is enabled, this pin serves as ECC

parity bit 0, MDP1.

Indicates that the modem or data set is ready to exchange data with

UART. In this mode the pin is an input only.

When COM2 is disabled and ECC is enabled, this pin serves as ECC

parity bit 0, MDP2.

Indicates to the modem or data set that the UART is ready to exchange

data. In this mode, the pin is an output only.

When COM2 is disabled and ECC is enabled, this pin serves as ECC

parity bit 0, MDP3.

R

Advance Information Subject to Change 31


R

Signal Type Description

DCD2#/MDP4 lvttl I/O Data Carrier Detect:

RI2#/MDP5 lvttl I/O Ring Indicator:

DSR2#/MDP6 lvttl I/O Data Set Ready:

DTR2#/MDP7 lvttl I/O Data Terminal Ready:

2.12 Miscellaneous Signals

Signal Type Description

SPKROUT CMOS out

O12

SMBDATA CMOS I/O

open drain

SMBCLK CMOS I/O

open drain

Indicates that modem or data set is ready to establish the

communications link with the UART. In this mode the pin is an input

only.

When COM2 is disabled and ECC is enabled, this pin serves as ECC

parity bit 0, MDP4.

Indicates that the modem or data set has detected a telephone-ringing

signal. In this mode, the pin is an input only.

When COM2 is disabled and ECC is enabled, this pin serves as ECC

parity bit 0, MDP5.

Indicates that the modem or data set is ready to establish the

communications link with the UART. In this mode the pin is an input

only.

When COM2 is disabled and ECC is enabled, this pin serves as ECC

parity bit 0, MDP6.

Indicates to the modem or data set that the UART channel is ready to

establish a communications link. In this mode, the pin is an output only.

When COM2 is disabled and ECC is enabled, this pin serves as ECC

parity bit 0, MDP7.

Speaker Out:

This output is bit 1 of the 82600 PortB register ANDed with the

TMROUT2 input from 8254 timer 2. The AND is an enable function

defined by the AT architecture.

System Management Data:

Serial data line used to transfer data on SMBus (I 2 C derivative)

System Management Clock:

Used to synchronize the SMBus.

32 Subject to Change Advance Information


Signal Type Description

IEN CMOS in

schmitt

50K Pullup

2.13 EIDE signals

Input Enable:

Signal Type Description

EIOR#/

RDMARDY#/

WSTROBE

EIOW#/

STOP

EIORDY/

RSTROBE/

WDMARDY#

lvttl out

O9

lvttl out

O9

EA[2:0] lvttl out

O9

ECS1#,ECS3# lvttl out

O9

R

When low, this pin disables the GTL inputs and USB ports for IDDQ

measurements and also disables the VCO in the PLL used to align the

internal HCLK network to the external HCLK pin. In system designs, this

pin can be used to hold off the PLL from locking until a stable clock

appears at the HCLK input.

EIDE I/O Read Strobe:

For PIO IDE modes, this strobe enables data from the disk drive onto the

data bus. Data is latched by the 82600 on the rising edge.

In an Ultra DMA/66 read cycle, this signal is used as a signal by the

82600 to pause DMA/66 transfers. In an Ultra DMA/66 write cycle, this

signal is used as the STROBE signal, with the drive latching data on

both edges of this signal.

EIDE I/O Write Strobe:

For PIO IDE modes, this signal is used to strobe the write data into the

disk drive from the data bus. Data is latched by the drive on the falling

edge.

In an Ultra DMA/66 read cycle, this signal is used as a signal by the

82600 to terminate (STOP) DMA/66 transfers.

lvttl in EIDE I/O READY:

For PIO IDE modes, this signal, when pulled low, extends the EIOR# or

EIOW# strobes. In an Ultra DMA/66 read cycle, this signal is driven by

the disk drive and is used by the 82600 to latch data from the EIDE data

bus on both edges. In an Ultra DMA/66 write cycle, this signal is used

as the DMARDY# that is negated by the drive to pause the DMA/66

transfers.

EIDE Register Select Address:

EA[2:0] are address signals that select 1 of 8 EIDE registers when ECS1#

is asserted and 1 of 2 registers when ECS3# is asserted.

EIDE Chip Select 0x1FX and 0x3FX:

ECS1# is asserted by the 82600 for I/O accesses in the range of 0x01F0-

01F7.

ECS3# is asserted by the 82600 for I/O accesses in the range of 0x03F6-

03F7.

Advance Information Subject to Change 33


R

Signal Type Description

ED[15:0]/

DIO[15:0]

lvttl I/O

IO9

EIDE Data Bus/ DIO Pins:

EDREQ lvttl in EIDE DMA Request

EDACK# lvttl out EIDE DMA Acknowledge

IRQ14 lvttl in IRQ14 Input

2.14 Power and Ground Pins

Signal Type Description

GTL+REF V GTL Reference Supply:

VTT V GTL+ Supply:

VDD V Core Logic Power Supply:

This bus transfers disk drive data to/from the 82600 when either ECS1#

or ECS3# are asserted or an Ultra DMA/66 transfer is in progress.

When configured as DIO pins with a power-on option bit, these pins can

be used as general purpose digital I/O pins.

This signal, when asserted, causes the 82600 to complete an Ultra

DMA/66 transfer.

When asserted by the 82600, this signal indicates that the EIORDY,

EIOR#, and EIOW# should be interpreted as performing Ultra DMA/66

functions.

This pin is sourced to the IRQ14 input of the internal 8259.

This should be tied to the local processor bus GTL+ reference voltage

(nominally 1.0V).

This should be tied to the GTL+ termination voltage (nominally 1.5V)

This should be tied to 2.5V

VDDIO V I/O Power Supply:

This should be tied to 3.3V

RTCVDD V Real Time Clock Voltage Supply:

Provides power only to the internal Real Time Clock megacell, its

associated battery-backed CMOS RAM and a few associated input and

output buffers. If using the internal RTC, connect this pin to a power

management circuit that switches between system core VDD (2.5V) and a

backup battery. If not using the internal RTC, connect this pin directly to

the system core VDD plane.

34 Subject to Change Advance Information


Signal Type Description

R

PCICLMP V Tied to either 5V or 3.3V, depending upon whether the BPCI bus and/or

LPCI bus needs to support 5V PCI or 3.3V PCI clamping. If either bus

needs to be operated at 5V then this pin must be tied to 5V. If this is tied

to 5V, then this 5V power should temporarily track or lead the application

of the 3.3V VDD for the periphery power pins.

VSS V Ground

AVDD V Analog Vdd

DVDD V Digital Vdd

This is the signal return path for all signals and supplies

This is the analog power supply pin for the internal 82600 PLL. It

requires special care in decoupling. Please see the reference design

schematics for an example implementation for the decoupling of this pin.

This is the digital power supply pin for the internal 82600 PLL. It should

be supplied with core VDD power (2.5V).

Advance Information Subject to Change 35


R

3 Power-up Configuration Options

The 82600 is highly configurable. While PWRGOOD is negated, the memory address pins are used as configuration

inputs that select various operating modes as described in Table 1. External pull-up or pull-down resistors are

required to set the options. 10K? resistors are recommended on all the option pins except MA2. For MA2 a 1.5K?

resistor is recommended. To accommodate “warm” push-button resets (i.e. a reset after initial power-on reset) using

the PWRGOOD signal, the loading of this register is delayed until PWRGOOD has been sampled low for 16

consecutive HCLKs. By reading the Power-up Options register, an application can also determine how the board is

configured at power-up. Once operating, additional modes are selected through the use of configuration register

bits.

MA0

MA1

MA2

MA3

MA4

L

H

L

H

L

H

L

H

L

H

EIDE/DIO Configuration:

Table 1: Power-Up Configuration Options

Configure EIDE/DIO shared pins as EIDE data bus pins.

Configure EIDE/DIO shared pins as DIO[15:0] pins.

The inversion of this bit is loaded into the Enable PCI Configuration Function 1

(EIDE Registers) bit of the Miscellaneous Function Enable Register.

ARB/DIO Configuration:

Configure ARB/DIO pins as BGNT[6:3]# and BREQ[6:3]# pins

Configure ARB/DIO pins as DIO[23:20] and DI[19:16] pins.

The inversion of this bit is loaded into the BPCI Extended Arbitration bit of the

Miscellaneous Function Enable Register.

IOBRIDGE: 82600 Bridge Functionality:

Full PCI Central Resource functionality is enabled for the BPCI bus: the arbiter is

enabled, all four level sensitive interrupt pins are treated as BPCI interrupt inputs,

etc.

PCI Peripheral Bridge functionality is enabled for the BPCI bus: the arbiter is

disabled, one level sensitive interrupt pin becomes a BPCI output interrupt, the

other interrupts become “local” level sensitive interrupts, IDSEL comes from the

BREQ1# shared pin, etc.

DISRTC: Internal Real Time Clock Enable:

RTC is enabled.

Disabled. RTC, if required, must be supplied externally. Note that the NMI enable

bit is always supplied inside the 82600 even if the internal RTC is disabled. An RTC

clock must be provided even when the internal RTC is not used.

BIOSPCI-ISA: BIOS Location - SDRAM bus or LPCI bus:

BIOS is located on the SDRAM bus

BIOS is located on the LPCI bus

36 Subject to Change Advance Information


MA5

MA6

MA7

MA8

L

H

L

H

L

H

L

H

Enable PrPMC Monarch Mode of the BPCI Bus.

MA2 controls the mode of operation of the 82600 PCI-to-PCI Bridge.

When MA5 is sampled high and MA2 is sampled low indicating Central Resource

mode at power-up, the BPCI bus arbiter of the 82600 will be disabled , but all other

central resource functions remain enabled. This mode makes the 82600 compatible

with PrPMC carrier cards. Please note that sampling MA5= high along with

MA2=high is not a legal combination and may cause unpredictable operation of the

PCI-to-PCI bridge in the 82600.

ECC/COM2 Configuration:

COM2 port is configured to use the ECC/COM2 port pins. ECC is disabled

DRAM ECC function is configured to use the shared ECC/COM port pins. To use

ECC, the ECC Enable bit in the SDRAM Control Register must also be set.

The inversion of this bit is loaded into the COM2 Enable bit of the Miscellaneous

Function Enable Register.

COM1/DIO Configuration:

COM1 port is configured to use the COM1/DIO pins.

DIO[31:24] are configured to use the COM1/DIO pins.

The inversion of this bit is loaded into the COM1 Enable bit of the Miscellaneous

Function Enable Register.

I/O Queue Depth:

In-Order queue depth is set to 8.

In-Order queue depth is set to 1 (causes A7# to be driven low during reset)

MA9 Reserved (requires a pull-down resistor).

MA11:10

xL

LH

HH

Host Frequency Select:

These settings affect SDRAM refresh timing, EIDE ultra DMA timings, and flash

timings.

Host clock operation at 66Mhz

Host clock operation at 133Mhz

Host clock operation at 100Mhz

R

Advance Information Subject to Change 37


R

MA14-11 FSB/Internal Processor Clock Ratio:

These bits are driven onto the following 82600 signals while CPURST# is being

asserted: LINT1 (MA14), LINT0 (MA13), IGNNE# (MA12), A20M# (MA11). For

processors that do not determine their internal clock rates from these four processor

input signals the power-on option bits MA14-12 can be used to define system

build-time options. Note that MA11 also is used to determine host clock frequency

(only 100 or 133) into the 82600. This limits the processor’s divider ratios to ½ of the

available selections in the case that an older 100MHz processor or an engineering

sample of a newer processor is used that still requires the ratio to be set by these

power-up options bits.

38 Subject to Change Advance Information


4 Register Descriptions

R

There are two types of internal registers in the 82600: PC compatible registers that are directly I/O mapped and PCI

configuration registers. A fully decoded 16-bit I/O address is used to access both types of registers. PC compatible

registers are defined by the PC/AT architecture and are addressable at standard I/O addresses. This includes the

RTC registers, the keyboard controller registers, PortA and the PortB registers, the 8259 registers, the 8254 registers,

the 8237 registers, the EIDE registers, the 16550 registers and the 74LS612 DMA page registers. Table 2 shows all of

the fixed I/O addresses that are decoded internally by the 82600. Unless otherwise noted, access to these registers is

enabled by setting the Miscellaneous Function Enable Register (MFE) bit 4 (Disable South Bridge Features) = 0. The

register descriptions specify the address and reset value as A = , R = . In addition, the

USB, Ultra DMA IDE functions and Power Management functions, when enabled, have I/O regions that are decoded

as pointed to by their PCI configuration registers. The 82600 will forward accesses to disabled I/O regions to the

appropriate PCI bus.

Table 2: Fixed I/O Register Addresses

I/O Address (hex) Register(s) Enabled By

0000-000F DMA controller 1 – 8237A MFE[4] = 0

0020-0021 Master 8259A MFE[4] = 0

0022 Power Management MFE[4] = 0

0040-0043 8254A timer/counter MFE[4] = 0

0060/0064 Keyboard controller data and control registers, if

enabled.

MFE[4] = 0

0061 PortB MFE[4] = 0

0070-0071 146818 RTC – NMI mask

Note: bit 7 of register 0070 (NMI enable) is shadowed

inside the 82600 even when the internal RTC is disabled.

MFE[4] = 0

or MA3 strap = H

0072-0073 Extended CMOS RAM access (72 index, 73 data) MFE[4] = 0

0080-008F 74LS612 style DMA page registers MFE[4] = 0

0092 PortA MFE[4] = 0

00A0-00A1 Slave 8259A MFE[4] = 0

00C0-00DF DMA controller 2 – 8237A MFE[4] = 0

00F0 Clear math coprocessor busy MFE[4] = 0

00F1 Reset math coprocessor MFE[4] = 0

01F0-01F7 EIDE Chip select 0 region MFE[6] = 1

Advance Information Subject to Change 39


R

I/O Address (hex) Register(s) Enabled By

02F8-02FF COM2 registers MFE[2] = 1

03F6 EIDE Chip select 1 region MFE[6] = 1

03F8-03FF COM1 registers MFE[3] = 1

04D0-04D1 INT1/INT2 edge/level control MFE[4] = 0

0CF8 (Dword) LPCI/BPCI configuration index always enabled

0CF9 (byte) Reset control MFE[4] = 0

0CFC-0CFF LPCI/BPCI configuration data registers. always enabled

0CF9 (byte) Reset Control always enabled

1CF8-1CFF Alternate BPCI configuration index and data registers always enabled

PWRBASE - +0x7F Power management/SMBus base register/DMA MFE[4] = 1

BMIBA1[15:4] - +0xF EIDE Bus master DMA registers BMIBA1[15:4] ? 0

USBBA[15:4] +0x1F USB I/O space USBBA[15:4] ? 0

4.1 Power Management Register: A=0022, R=00

This register contains a single read/write bit that controls the 82600 arbitration function. All other bits are always read

as 0. Writing the other bits in this register has no effect on the 82600.

Bit Description

7:1 Reserved. Read as 0. Writing these bits has no effect.

0 Arbiter Disable – R/W. When ARB_DIS is set to a 1, the 82600 does not respond with a grant to any

BREQ# or LREQ# signals until this bit is cleared. This bit is used to disable bus master accesses prior

to placing the CPU in a stop clock state. Please note that this bit does not stop the internal USB host

controller nor the EIDE UDMA controller from generating host bus accesses that need to be

snooped.

40 Subject to Change Advance Information


4.2 Keyboard Controller Data Register: A=0060, R=x4

Bit Description

R

7:0 Data Register – R/W. Writes to this register either update the internal keyboard controller’s registers

or are passed to the external keyboard controller via the keyboard’s serial link. Reads from this

register return the internal keyboard controller’s register contents or return scan codes passed by the

external keyboard controller via the keyboards serial link. Stream Commands written to the Keyboard

Controller Status/Command Register prior to access to this register determine the target of the

access.

4.3 PortB Register: A=0061, R=x0

The PortB register supports NMI generation, timer/counter2, and speaker control.

Bit Description

7 Parity Check/SERR - RO. Writing this bit has no effect.

This bit is set if bit 2 of this register = 0 and:

1) A non-correctable parity error has occurred or

2) A correctable parity error has occurred and bit 2 if the EAP Register is enabled or

3) LSERR# has been asserted or

4) BSERR# has been asserted and bit 1 of the Bridge Control Register = 1

Writing bit 2 of this register to 1 clears this bit.

6 IOCHCK - RO. Writing this bit has no effect. This bit reflects the status of the IOCHCK# signal

from the SERIRQ bit stream. This bit is set if bit 3 of this register is 0 and the IOCHCK# interrupt

request was received. Writing bit 3 of this register to a 1 clears this bit.

5 Timer/Counter Out2 - RO. Writing this bit has no effect. This bit reflects the state of the

TIM2_OUT signal.

4 Refresh Status - RO. Writing this bit has no effect. Refresh Status is a bit that toggles every time a

SDRAM refresh occurs. This bit is cleared during hardware reset.

3 Enable IOCHCK NMI – R/W. When set to 0, this bit enables NMI from an IOCHCK# interrupt

request received from the SERIRQ. Bit 7 of the RTC Index Register must also be set to allow NMI to

be signaled.

2 Enable Parity NMI – R/W. This bit enables the parity feature when set to 0. When enabled, parity

errors can cause an NMI to be generated. Bit 7 of the RTC Index Register must also be set to allow

NMI to be signaled. When bit 2 is written to a 1, bit 7 is cleared.

1 Speaker Data Enable – R/W. The logical AND of this bit with the Counter 2 OUT signal drives the

SPKROUT output signal.

0 Timer Counter 2 Enable – R/W. When set, this bit enables counting by Timer/Counter 2. This bit

controls the GATE input to Counter 2. This bit is cleared on hardware reset.

Advance Information Subject to Change 41


R

4.4 Keyboard Controller Status/Command Register: A=0064, R=00

Bit Description

7:0 Status/Command – R/W. Writes to this register cause the internal keyboard controller’s command

register to be updated. Reads from this register return the status of the keyboard controller

4.5 RTC Index Register: A=0070, R=80

The RTC and CMOS RAM are accessed via an eight bit wide index/data register pair of I/O addresses. This register

holds the address of the location to be accessed within the RTC and CMOS RAM.

Bit Description

7 Disable NMI – R/W. When set, this bit disables the NMI function. Note that this bit is shadowed

even when the internal RTC is disabled.

6:0 RTC/CMOS RAM Register Address – R/W. When a reference to the RTC Data Port occurs, these

bits are used to determine which RTC or CMOS RAM register is written. Values of 0x0-0xD cause

RTC Data Port accesses to be routed to the RTC and values 0xE-0x7F cause accesses to the 114

byte CMOS RAM

4.6 RTC Data Port: A=0071, R=00

Bit Description

7:0 RTC/RAM Data Port – R/W. The location in the RTC/CMOS RAM pointed to by RTC Index

Register is accessed when an I/O read or I/O write operation to this byte location occurs. While

RTCPS is low, all RAM locations are cleared.

4.7 Extended CMOS Index Register: A=0072, R=00

The extended CMOS RAM is accessed via an eight bit wide index/data register pair of I/O addresses. This register

holds the address of the location to be accessed within the extended CMOS RAM.

Bit Description

7 Reserved. Hardwired to 0.

6-0 Extended CMOS RAM Register Address - WO. When a reference to the RTC Data Port occurs,

these bits are used to determine the address in extended CMOS RAM that is to be read or written.

4.8 Extended CMOS Data Port: A=0073, R=xx

Bit Description

7:0 Extended CMOS RAM Data Port – R/W. The location in the extended CMOS RAM pointed to by

Extended CMOS Index Register is accessed when an I/O read or I/O write operation to this byte

location occurs.

42 Subject to Change Advance Information


4.9 Port A (Port 92): A=0092, R=02

R

This register is PS/2 compatible and is used to support backward compatibility with the 286 PCAT without having to

use the slower keyboard controller mechanism.

Bit Description

7-2 Reserved. These bits return 0 when read.

1 A20 Mask (A20M) – R/W. The A20M# pin is the logical OR of:

1) This A20M register bit

2) The keyboard controller GATEA20 signal

3) A status bit that tracks whether the processor is in SMM

4) A state bit that is asserted by INIT# and negated after the first code fetch from below 2GB.

A value of 1 in this bit will mask the ability of the other 3 signals to assert the A20M# to a low.

0 SRESET – R/W. This bit provides a fast software executed processor reset function. This function

provides an alternate means to reset the system processor to effect a mode switch from Protected

Virtual Address Mode to the Real Address Mode. This provides a faster means of reset than is

provided by the Keyboard controller. When SRESET transitions from a 0 to a 1, the INIT# pin is

asserted on the 82600 for a minimum of 64 LPCI cycles. This is only initiated once when this bit

transitions from a 0 to a 1 state. Before another transition can be recognized, this bit must be written

back to a 0.

4.10 ELCR1, Edge/Level Control Register 1: A=04D0, R=00

This register allows the IRQ[7:3] inputs to the embedded 8259 to be edge or level programmable on an interrupt by

interrupt basis. To provide this control on an interrupt by interrupt basis the LTIM bit of register ICW1 of the

embedded the 8259s is disabled and the bits in this register define each interrupt as a level sensitive or edge triggered

interrupt. If a LPCI or BPCI interrupt is mapped onto one of these interrupts, then the corresponding bit must be set

to level triggered mode. The internal 8259 interrupt controller requires a positive level when programmed as a level

sensitive input or a positive edge when programmed as an edge triggered input.

Bit Description

7 IRQ7 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode

6 IRQ6 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode

5 IRQ5 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode

4 IRQ4 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode

3 IRQ3 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode

2:0 Reserved. Hardwired to 0.

Advance Information Subject to Change 43


R

4.11 ELCR2, Edge/Level Control Register 2: R=04D1, R=00

This register allows the IRQ[15:9] inputs to the embedded 8259 to be edge or level programmable on an interrupt by

interrupt basis. To provide this control on an interrupt by interrupt basis the LTIM bit of register ICW1 of the

embedded the 8259s is disabled and the bits in this register define each interrupt as a level sensitive or edge triggered

interrupt. . If a LPCI or BPCI interrupt is mapped onto one of these interrupts, then the interrupts corresponding bit

must be set to level triggered mode. The internal 8259 interrupt controller requires a positive level when programmed

as a level sensitive input or a positive edge when programmed as an edge triggered input.

Bit Description

7 IRQ15 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode

6 IRQ14 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode

5 IRQ13 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode. This bit is normally set to 0

to allow the PC-compatible floating-point error interrupt signaling to occur correctly.

4 IRQ12 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode

3 IRQ11 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode

2 IRQ10 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode

1 IRQ9 ECL – R/W. 0 = Edge triggered mode; 1 = Level triggered mode

0 Reserved. Hardwired to 0.

4.12 LPCI/BPCI Configuration Index/Data Registers

These registers form an index/data register pair for accessing LPCI configuration space registers. This register pair

may be used to access BPCI configuration space registers when the 82600 is configured as the Central Resource of

the BPCI bus. A Dword I/O access must be made to the Configuration Index Register (0CF8). Accesses to the data

register may be byte, word, or Dword in length and return/modify the register that is selected indirectly by the 32 bit

Configuration Index Register content.

Attempting to write to a single byte of the Configuration Index Register will result in no bytes of the Configuration

Index Register being written. The Configuration Index Register I/O address spans 0CF8 through 0CFB. Note that a

write to only address 0CF9 will access the Reset Control Register.

If the 82600 is configured as a BPCI Peripheral Bridge, the Alternate Index/Data Registers must be used to access the

BPCI configuration registers.

44 Subject to Change Advance Information


4.12.1 LPCI/BPCI Configuration Index Register: A=0CF8, R=0000_0000

Bit Description

31 Configuration Enable – R/W. 1 = Enable, 0 = Disable

30:24 Reserved. Hardwired to 0.

23:16 Bus Number – R/W. When 0, this field will cause either an 82600 configuration register access or

a LPCI bus configuration cycle (type 0) to be executed in response to an access to the

Configuration Data Register. If the Bus Number is non-zero, a type 1 PCI configuration cycle is

generated in response to a Configuration Data Register access. This cycle will occur on the LPCI

bus if directed by the internal virtual PCI-to-PCI bridge configuration registers. This cycle will

occur on the BPCI bus if the 82600 is configured as the BPCI Central Resource and if directed by

the internal virtual PCI-2-PCI bridge configuration registers. For a type 1 configuration access, bits

31-24 are driven to 0 onto the PCI bus, bits 1 to 0 are driven with "01" code and the remaining bits

are driven from the respective bit position in this register.

R

15:11 Device Number – R/W. This field is used to select a single PCI bus agent. When the 82600 is in

Central Resource mode and this field is not zero or one, an external configuration cycle will be

generated in response to an access to the Configuration Data Register. When this field is zero (or

one when the 82600 is configured in Central Resource mode) and the bus number field is zero, then

an access to the Configuration Data Register is directed to the addressed internal configuration

register.

10:8 Function Number – R/W. This field is mapped to LAD[10:8] or BAD[10:8] during LPCI or BPCI

configuration cycles unless the bus number = device number = 0 (self access). The 82600 responds

to function numbers 0 to 2. Any other function numbers will generate a master abort.

7:2 Register Number – R/W. This field selects a register within a particular Bus, Device, and Function

as specified by the other fields in the Configuration Index Register

1:0 Reserved. Hardwired to 0

4.12.2 LPCI/BPCI Configuration Data Register: A=0CFC, R=xxxx_xxxx

Bit Description

31:0 Configuration Data Window – R/W. If bit 31 of the Configuration Index Register is 1, then I/O

references that fall inside this window are mapped to internal or external PCI configuration registers.

If bit 31 of the Configuration Index Register is 0 then writes to this register have no effect.

Advance Information Subject to Change 45


R

4.13 RC—Reset Control Register: A=0CF9, R=xx

Bits 1 and 2 in this register are used by the 82600 to generate a hard reset or a soft reset. During a hard reset, the

82600 asserts CPURST# and LPRST# and resets its own core logic. BPRST# is also asserted if the 82600 is

configured as the BPCI Central Resource. During a soft reset, the 82600 only asserts INIT#.

Bit Description

7:3 Reserved.

2 Reset CPU (RCPU) – R/W. A transition of this bit from a 0 to a 1 initiates a reset. The type of reset

is determined by bit 1. This bit cannot be read as a 1.

1 System Reset (SRST) – R/W. This bit is used to select the type of reset generated when bit 2 in this

register transitions to a 1. A value of 1 selects a hard reset and 0 selects a soft reset

0 Reserved.

4.14 Alternate BPCI Configuration Index/Data Registers

These registers form an index/data register pair for accessing BPCI configuration registers. A Dword I/O access must

be made to the Alternate Configuration Index Register (1CF8). Accesses to the data register may be byte, word, or

Dword in length and return/modify the register that is selected indirectly by the 32 bit index register content.

Attempting to write to a single byte of the index register (e.g. writing a single byte to only 1CF9) will result in no

bytes of the configuration index register being written. When the 82600 is configured in BPCI Peripheral Bridge

mode, it can use these registers to generate BPCI configuration cycles to all BPCI devices except for a device with a

bus number and device number of 0. This is typically the Central Resource of the BPCI bus. The 82600 uses

alternate configuration cycles to bus #0, device #0 to perform internal configuration cycles to its virtual PCI-to-PCI

bridge configuration registers. The Alternate BPCI Configuration Index/Data Registers can also be used to access

the BPCI bus when the 82600 is configured as the Central Resource of the backplane bus; however, the standard

Configuration Index/Data registers (@0CF8 and 0CFC) would normally be used when in this mode.

46 Subject to Change Advance Information


4.14.1 Alternate BPCI Configuration Index Register: A=1CF8, R=0000_0000

Bit Description

31 Configuration Enable – R/W. 1 = Enable, 0 = Disable

30:24 Reserved. Hardwired to 0.

23:16 Bus Number – R/W. When 0 this field will cause either a BPCI configuration register access or an

external, type 0 BPCI bus configuration cycle to be executed in response to an access to the

Alternate BPCI Configuration Data Register. A non-zero Bus Number field causes a type 1 BPCI

configuration cycle to be generated in response to an Alternate BPCI Configuration Data Register

access if directed by the internal virtual PCI-2-PCI bridge configuration registers.

R

15:11 Device Number – R/W. This field is used to select a single BPCI bus agent. When this field is not

zero, an external configuration cycle will be generated in response to accesses to the Alternate

BPCI Configuration Data Register. When this field and the Bus Number field are both zero, then an

access to the Alternate BPCI Configuration Data Register will generate an internal configuration

register access.

10:8 Function Number – R/W. This field is mapped to BAD[10:8] during BPCI configuration cycles

unless the bus number = device number = 0 (self access). For device 0 references, all non-zero

functions return a master abort.

7:2 Register Number – R/W. This field selects a register within a particular Bus, Device, and Function

as specified by the other fields in the Configuration Index Register

1:0 Reserved. Hardwired to 0

4.14.2 Alternate BPCI Configuration Data Register: A=1CFC, R=xxxx_xxxx

Bit Description

31:0 Configuration Data Window – R/W. If bit 31 of the Alternate BPCI Configuration Index Register is

1, then I/O references that fall inside this window are mapped to internal or external BPCI

configuration registers. If bit 31 of the Configuration Index Register is 0 then writes to this register

have no effect.

4.15 LPCI Configuration Registers (Device 0, Function 0,1, & 2)

These configuration registers are accessed by the local host processor by generating I/O accesses to the LPCI/BPCI

Configuration Data Register after first specifying the exact register with a 32 bit I/O write cycle to the LPCI/BPCI

Configuration Index Register. The register descriptions in Table 3 specify the address using only the LPCI

configuration function number and register number as: A = . , R = . The local host processor accesses these registers without generating an LPCI bus cycle by setting the

LPCI/BPCI Configuration Index Bus Number and Device Number fields to 0. None of the registers in Table 3 are

accessible from either PCI interface.

Advance Information Subject to Change 47


R

Address

Offset

Register

Symbol

Function 0: 82600/LPCI Bridge Registers

Table 3: LPCI Configuration Registers

Register Name Access:

00-01 LVID Vendor Identification RO

02-03 LDID Device Identification RO

RO = Read-Only,

R/W = Read/Write,

R/WC = Read/Write-Clear

04-05 LPCICMD LPCI Command Register See register description

06-07 LPCISTS PCI Status Register See register description

08 LRID Revision Identification RO

09-0B LCLASSC Class Code Register RO

0C Reserved

0D LMLT Master Latency Timer R/W

0E LHT Header Type RO

2C-2D LSUBVID Subvendor Identification R/W

2E-2F LSUBDID Subvendor Device Identification R/W

4C MLPC Miscellaneous LPCI Control R/W

57 DRAMC DRAM Control Register R/W

59-5D PAM[0:4] Programmable Address Map Registers R/W

60-63 DRBA[0:3] SDRAM Row Boundary Address Register R/W

70 LMTT Multi-Transaction Timer Register R/W

71 SMRAMC System Management RAM Control Reg. R/W

74 RPS SDRAM Row Page Size register R/W

76-77 SDRAMC SDRAM Control Register R/W

78-79 PGPOL Paging Policy Register R/W

7A MCTL Miscellaneous Control Register R/W

48 Subject to Change Advance Information


Address

Offset

Register

Symbol

Register Name Access:

7C-7F LAAR Local Abort Address Register RO

80-83 EAP Error Status Register R/WC

90-91 POB Power-on Option Bits Register RO

92 CPO COM Port Option Register R/W

94 PWRBASE PWRMGT/SMBus Configuration Register R/W

96 MFE Miscellaneous Function Enable Register R/W

A0-A3 LIRQRC[A:D] LIRQx Route Control Register R/W

Function 1: EIDE Configuration Registers

00-01 VID Vendor Identification RO

02-03 DID Device Identification RO

04-05 PCICMD PCI Command Register R/W

06-07 PCISTS PCI Status Register RO

08 RID Revision Identification RO

09-0B CLASSC Class Code RO

0D MLT Master Latency Timer R/W

0E HT Header Type RO

20-23 BMIBA Bus Master Interface Address R/W

40-41 IDETIM IDE Timing Register R/W

48 UDMACTL Ultra DMA Control Register R/W

4A UDMACTL Ultra DMA timing Register R/W

Function 2: USB Configuration Registers

0-1 VID Vendor Identification RO

2-3 DID Device ID RO

RO = Read-Only,

R/W = Read/Write,

R

R/WC = Read/Write-Clear

Advance Information Subject to Change 49


R

Address

Offset

Register

Symbol

Register Name Access:

04-05 PCICMD PCI Command Register R/W

06-07 PCISTS PCI Status Register RO

08 RID Revision Identification RO

09-0B CLASSC Class Code RO

0D MLT Master Latency Timer R/W

0E HT Header Type RO

20-23 USBBA USB I/O B Space Base Address R/W

3C INTL Interrupt Line R/W

3D INTP Interrupt Pin RO

60 SBRNUM Serial Bus Release Number RO

RO = Read-Only,

R/W = Read/Write,

R/WC = Read/Write-Clear

Device 0, Function 0 Registers (Local Host to LPCI Bridge)

4.15.1 LVID, Vendor Identification Register: A=0.0, R=1331

Bit Description

15:0 Vendor Identification Register - RO. This is hardwired to RadiSys’ vendor ID: 1331.

4.15.2 LDID, Device Identification Register: A=0.2, R=8200

Bit Description

15:0 Device Identification Register - RO. The 82600 ID is 8200.

50 Subject to Change Advance Information


4.15.3 LPCICMD, LPCI Command Register: A=0.4, R=0006

Bit Description

15:10 Reserved. Hardwired to 0.

9 Fast Back-to-Back. Hardwired to 0. As a master, the 82600 will not initiate fast back to back LPCI

accesses.

8 LSERR Enable Bit – R/W. This bit is R/W but has no effect on the 82600.

7 Address and Data Stepping Enable. Hardwired to 0

6 Parity Error Enable – R/W. This bit is R/W but has no effect on the 82600.

5 Video Pallet Snooping. Hardwired to 0

4 Memory Write and Invalidate Enable. Hardwired to 0

3 Special Cycle Enable. Hardwired to 0. The 82600 ignores LPCI generated special cycles

2 Bus Master Enable. Hardwired to 1. The 82600 always serves as the LPCI bus master.

1 Memory Access Enable. Hardwired to 1. The LPCI bus can always access the 82600 SDRAM. The

82600 automatically maps the SDRAM into the bottom of the LPCI address space.

0 I/O Access Enable. Hardwired to a 0. The 82600 does not respond to LPCI I/O cycles.

R

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4.15.4 LPCISTS, LPCI Status Register: A=0.6, R=0220

Bit Description

15 Detected Parity Error – R/WC. 1=LPCI address or data parity error has been detected. An

application may clear this bit by writing a 1 to this bit position. Writing a 0 has no effect. This

function is not affected by the PERE bit.

14 Reserved. Hardwired to 0.

13 Received Master Abort Status - R/WC. When the 82600 generates a LPCI master-abort, then this

status bit is set. In addition, the Local Abort Address Register latches the abort address whenever

the “OR” of the 2 “abort” status bits (see Received Target Abort Status bit in this register) is

asserted. If both abort bits are set, the Local Abort Address Register will contain the address of

the first (in time) abort address. Writing a 1 to this bit position clears this bit. Writing a 0 has no

effect on this status bit.

12 Received Target Abort Status - R/WC. When the 82600 initiates a LPCI bus transaction and

receives a target abort, this bit is set. In addition, the Local Abort Address Register latches the

abort address whenever the “OR” of the 2 “abort” status bits (see Received Master Abort Status)

is asserted. If both abort bits are set, the Local Abort Address Register will contain the address of

the first (in time) abort address. Writing a 1 to this bit position clears this bit. Writing a 0 has no

effect on this status bit.

11 Signaled Target Abort Status. Hardwired to a 0

10:9 DEVSEL# Timing. This 2 bit field indicates the timing of the DEVSEL# signal when the 82600

responds as a target on the LPCI bus, and indicates the time when a valid DEVSEL# can be

sampled by the initiator of the LPCI cycle. Hardwired to 01 (medium timing).

8 PERR# Response. Hardwired to 0.

7 Target Fast Back to Back. This bit is hardwired to 0. The 82600 as a target does not support fast

back to back transactions on the LPCI bus.

6 Reserved. Hardwired to 0.

5 66MHz Capable. Hardwired to 1 to indicate 66MHz capability.

4:0 Reserved. Hardwired to 0.

4.15.5 LRID, Revision Identification Register: A=0.08, R=00

Bit Description

7:0 Revision Identification Register. The 82600 RID is 00. This value is read-only. Stepping A-0 = 00

52 Subject to Change Advance Information


4.15.6 LCLASSC, Class Code Register: A=0.09, R=06_0000

Bit Description

23:16 Base Class Code. This is hardwired to 06 indicating a Bridge Device.

15:8 Sub Class Code. This is hardwired to 00 indicating a Host Bridge.

7:0 Programming Interface. This is hardwired to 00.

4.15.7 LMLT, Master Latency Timer: A=0.0D, R=00

Bit Description

R

7:3 Master Latency Timer Count Value. The value placed in these bits form the upper 5 bits of an 8bit

count value. The lower 3 bits are always 0. This count value defines the number of LPCI clocks

given to the 82600 before it must surrender mastership of the LPCI bus if other LPCI agents are

requesting access to the bus. The default value of 00 disables this function.

2:0 Reserved. Hardwired to 0.

4.15.8 LHT, Header Type: A=0.0E, R=80

Bit Description

7:0 Header Type. This is hardwired to 80: standard configuration register space with multifunction

capability (e.g. EIDE).

4.15.9 LSUBVID, Sub-Vendor Identification Register: A=0.2C, R=0000

Bit Description

15:0 Sub-Vendor Identification Register. This register is used to identify the vendor of the subsystem.

The initial LSUBVID is 0000. The local host should write this field during boot-up.

4.15.10 LSUBDID, Sub-Device Identification Register: A=0.2E, R=0000

Bit Description

15:0 Sub-Device Identification Register. This register is used to identify a particular subsystem. The

initial LSUBDID is 0000. The local host should write this field during boot-up.

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4.15.11 MLPC, Miscellaneous LPCI Control: A=0.4C, R=00

Bit Description

7 Arbiter Timeout, R/WC. This bit is set by the 82600 when the LPCI arbiter does not see FRAME#

asserted within 16 clocks of asserting a GNT# to a bus master. When this occurs the GNT# is

negated and the REQ# signal is ignored. Writing a 1 to this bit position clears this bit.

6 Shutdown Status – R/WC. This bit is set when a shutdown cycle is detected and the shutdown

response (bit 0 of this register) is also set. This bit may be cleared by writing a 1 to this bit position.

5:4 Reserved. Hardwired to 0.

3 LPCI Reset. This bit when set to a 1 causes the LPCI reset signal to be asserted. Clearing this bit

negates the LPCI reset signal.

2:1 Target Prefetch Control.

0x 82600 immediately invalidates any read data prefetched and not used by a LPCI access.

10 82600 retains prefetched data for all read commands until invalidated by a host bus write or

consumed by a LPCI memory operation.

11 82600 retains prefetch data for read-multiple and read-line commands, but immediately

invalidates bytes not consumed by a LPCI “memory read” command.

0 Shutdown Response - RW. When 0, a hardware reset (CPURST#, LRST#, and if in central resource

mode BRST#) is issued in response to a host processor generated “shutdown” cycle. When 1, a

warm reset (INIT#) is asserted and the shutdown status bit is set in response to a host processor

shutdown cycle.

54 Subject to Change Advance Information


4.15.12 DRAMC, SDRAM Control Register: A=0.57, R=00

Bit Description

R

7 SDRAM ISA Hole Enable – R/W. If set, a 2MB SDRAM ISA hole is enabled in the host address

map starting at 14MB (0x0E0_0000 -0x0FF_FFFF). Non-SMI accesses to this address region from

the host processor are forwarded to the LPCI bus. DEVSEL# is not asserted for LPCI accesses that

reference these addresses. SDRAM “behind” the hole is accessible in SMI mode. When clear, the

SDRAM hole is disabled and host accesses to this address region are forwarded to the SDRAM.

6 Flash Page Mode Enable – R/W. If set, read accesses to the resident flash that span a 16-bit

boundary within a quad-word boundary, will use page mode -3-3-3 HCLK timing to fetch up to 3

subsequent 16-bit quantities. If clear, subsequent 16-bit flash accesses will use the full 11 (22 for

100/133Mhz) HCLK timing of >150ns access time.

5 ECC Enable – R/W. If this bit is set it causes main memory to be accessed using an ECC protocol.

Writes of less than 8 bytes are always sequenced as full 8 byte read-modify-write cycles.

Hardware scrubbing of any correctable ECC errors is also enabled. For correct functioning of ECC

power-up configuration strapping of MA6 is also required.

4 DRAM DIMM Type – R/W. 1 = registered or buffered. 0 = unbuffered. When set to 1, the

SDRAM controller gives all control signals an extra cycle to allow for registered SDRAM DIMM

latency. All DIMMs must contain a one-clock register buffer for all of the DIMMs control signals.

Data is not buffered. When set to 0, control and data timing is generated for unbuffered DIMMs

and a direct connection between the 82600 and the SDRAM memory chips is required.

3 BIOS Alias Disable – R/W. 1 = Disable BIOS aliasing below 1MB. 0 = Enable BIOS aliasing for

SDRAM read accesses between the addresses 0x000C0000- 0x000FFFFF. Write accesses to this

address region will always be sequenced to SDRAM. The PAM registers take precedence over

this bit. That is, if the PAM register is set to steer the access to the LPCI bus, the access will go to

LPCI, independent of the state of the BIOS Alias Disable bit.

2 SDRAM BIOS Flash WE – R/W. When this bit is set it enables writes to the flash address region

(address > 0xFC00_0000). When this bit is clear the flash is write protected by disabling the

SDRAM bus WE# signal for these addresses. If flash does not reside on the SDRAM bus this bit

is ignored. The presence of flash on the SDRAM bus is indicated by power-up option bit MA4.

1:0 SDRAM Refresh Rate – R/W.

00 Disable refresh

01 7.8 microseconds (256Mbit SDRAMs)

10 15.6 microseconds

11 125 microseconds

Advance Information Subject to Change 55


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4.15.13 PAM, Programmable Address Map Registers: A=0.59-0.5D,

R=0x33 (BIOS on SDRAM bus); R=0x00 (BIOS on LPCI bus)

The 82600 allows programmable memory attributes on 10 Legacy memory segments of various sizes in the 640KB to

1MB address range as defined in Table 5. Five Programmable Attribute Map (PAM) Registers are used to support

these features. Cacheability of these areas is controlled via the MTRR registers in the local processor. Two bits are

used to specify memory attributes for each memory segment. These bits apply to both host accesses and LPCI or

BPCI initiated accesses to the PAM areas. These attributes are:

? RE Read Enable. When RE = 1, the host read accesses to the corresponding memory segment are claimed by the

82600 and directed to main memory. When RE = 0, the host read accesses are directed to the LPCI bus.

? WE Write Enable. When WE = 1, the host write accesses to the corresponding memory segment are claimed by

the 82600 and directed to main memory. When WE = 0, the host write accesses are directed to the LPCI bus.

The RE and WE attributes permit a main memory segment to be Read Only, Write Only, Read/Write, or disabled. For

example, if a memory segment has RE = 1 and WE = 0, the main memory segment is Read Only. Each PAM Register

controls two regions, typically 16 KB in size. Each of these regions has a 4-bit field. The four bits that control each

region have the same encoding and are defined in Table 4.

The 82600 also supports an additional ISA Hole Enable register. This is defined in the SDRAM Control Register.

This “HOLE Enable” register allows one other address range within the SDRAM address space to be mapped to the

LPCI bus. The host SDRAM address space is directly mapped to the LPCI address space with no address translation.

For LPCI accesses to the PAM region, the 82600 will only assert DEVSEL and claim the access if both read enable

and write enable bits are set for that region so that SDRAM is mapped for both read and write in the address region.

When both normal read and write accesses to an area of SDRAM are disabled, this SDRAM area may be reclaimed

for use by the host for accesses in SMM mode, if the SMI SDRAM Reclaim bit is set in the System Management

RAM Control Register.

Bits[7,3]

Reserved

Bits[6,2]

Reserved

Bits [5,1]

WE

Table 4: PAM Register Attribute Bit Assignment

Bits[4,0]

RE

Description

X X 0 0 Disabled. SDRAM is disabled and all accesses are

directed to the LPCI bus. The 82600 will not respond as a

local or backplane PCI target in this area.

X X 0 1 Read Only. Reads are forwarded to SDRAM and writes

are forwarded to the LPCI bus for termination. The

SDRAM in this area is write protected and non-cacheable.

X X 1 0 Write Only. Writes are forwarded to SDRAM and reads

are forwarded to the LPCI bus for termination. This mode

is useful for PCI ROM “copy in place” shadow operations

x X 1 1 Read/Write. This is the normal mode of operation of main

memory. Both reads and writes from the local processor

are forwarded to SDRAM. The SDRAM area is cacheable.

The 82600 will respond as a local or backplane PCI target

in this area.

56 Subject to Change Advance Information


Table 5: PAM Registers and Associated Memory Segments

PAM Register and Bits Associated Memory Region

59[3:0] 0A0000-0BFFFF

59[7:4] 0F0000-0FFFFF.

5A[3:0] 0C0000-0C7FFF

5A[7:4] 0C8000-0CFFFF

5B[3:0] 0D0000-0D3FFF

5B[7:4] 0D4000-0D7FFF

5C[3:0] 0D8000-0DBFFF

5C[7:4] 0DC000-0DFFFF

5D[3:0] 0E0000-0E7FFF

5D[7:4] 0E8000-0EFFFF

4.15.14 DRBA[0:3], SDRAM Row Boundary Address Register: A=0.60-0.63, R=00

R

The 82600 supports four 64 bit wide SDRAM rows. A row can contain a minimum of 16MB and a maximum of 512MB.

The DRBA registers describe the size of each row by defining the last 16MB region accessed by each row. For

example, for a 16MB first row the first DRBA would contain 0x01 meaning that the last address 0x00FF_FFFF is the

last byte in the first row. The SDRAM row sizes are defined in 16MB quantas. The size of a row is the last address of

this row minus the last address of the previous row. The register at address 0x60 represents row 0 or RAS0# and

CS0#, 0x61 represents row 1 or RAS1# and CS1#, etc. The values of these registers must be programmed in

ascending order. That is, row 3’s register must be = row 2= row1= row 0. When row n+1 is set to the same

boundary value as row n, this indicates that row n+1 is not populated and RASn+1#/CSn+1# will never be generated

for row n+1. All unpopulated rows must be set to the same value as the previous row. A row will be accessed when

it is the lowest numbered row for which the address being accessed falls below its boundary address. For example,

an address of 0 will fall within the boundary address of all rows, but the access will only access memory in row 0 if

row 0 is populated. For all memory accesses address bit A31 must be zero.

Bit Description

7:0 Row Boundary Address – R/W. This 8 bit value is compared against address lines HA[30:24] to

determine the upper address limit of a row. If these address lines are less than the value in this

register and this is the lowest number register that meets this criteria, then the RAS# line

associated with this row will be activated for the access

Advance Information Subject to Change 57


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4.15.15 LMTT, Multi-Transaction Timer Register: A= 0.70, R=20

Bit Description

7:2 MTT Count Value – R/W. The value programmed here represents the guaranteed time slice, in

LPCI clocks, allotted to the current agent. Once expired, the 82600 will grant the bus as soon as

another LPCI agent requests the bus. The count value is a multiple of 4 LPCI clocks since bits 1

and 0 are hardwired to 0.

1:0 Reserved. Hardwired to 0.

4.15.16 SMRAMC, System Management RAM Control Register: A=0.71, R=00

Bit Description

7 Reserved. Hardwired to 0.

6 SMM SPACE Open – R/W. When set, this bit overrides PAM, ISA hole enable, and SMRAM

high space enable bits of this register, and forces accesses to these regions to go to SDRAM.

This bit can be used to install SMM handlers in these regions without having to be in SM Mode.

It can also be used to give a clean, “no-memory-holes” SDRAM image to the processor. When

used to install SMM handlers, once the handlers have been installed, this bit should be cleared to

allow accesses to these regions to go to PCI (e.g. video memory at 0xBXXXX), if the PAM, ISA

hole enable or SMRAM high space enable bits are set accordingly.

5:2 Reserved. Hardwired to 0.

1 SMI SDRAM Reclaim – R/W. 1 = Enable. 0 = Disable. When enabled, accesses in SMM mode

will override the ISA hole enable and the PAM register settings to force the memory accesses to

these regions to the SDRAM controller. When disabled, accesses to the ISA hole and PAM

regions are governed by the ISA hole enable bit and the PAM register bits, respectively.

0 SMRAM High Space Enable – R/W. 1 = Enable. 0 = Disable. When enabled, only SMI accesses

from the host processor will be able to access the top 1MB of SDRAM space pointed to by

DRBA3. Also, when enabled, LPCI DEVSEL will not be asserted for this memory region when

accessed by either PCI interface. When disabled, any access, including SMI accesses, to the top

1MB of SDRAM space will be forwarded/serviced by the SDRAM controller and DEVSEL will be

asserted from the LPCI.

58 Subject to Change Advance Information


4.15.17 RPS - SDRAM Row Page Size Register: A=0.74, R=00

Bit Description

7:0 Page Size (PS) – R/W. Each pair of bits indicate the page size that the 82600 supports for the

respective row as follows:

Bits[1:0] Page Size

00 2KB

01 4KB

10 8KB

11 Reserved

Bits 7:6 define the page size for row 3 (DRBA3). Bits 5:4 define the page size for row 2 (DRBA2) …

etc.

R

Advance Information Subject to Change 59


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4.15.18 SDRAMC, SDRAM Control Register: A=0.76, R=0000

Bit Description

15:8 Reserved.

7:5 Special SDRAM Mode Select – R/W. These bits select 1 of 5 SDRAM operating modes that allow

testing, initialization, and normal operation. Only a single row is selected when operating in Normal

mode (selected by the upper address bits). In all other modes, any SDRAM access (any address)

will assert all 4 chip selects at once and perform the same operation to all four banks at once.

000 Normal SDRAM mode (default)

001 NOP Command Enable (NOPCE). This mode forces all CPU cycles to SDRAM to generate

an SDRAM NOP command on the memory interface.

010 All Banks Precharge Command Enable (ABPCE). This setting causes all SDRAM

accesses to be converted to an All Banks Precharge Command.

011 Mode Register Command Enable (MRCE). In this mode all CPU cycles to SDRAM result in

a mode register set command on the SDRAM interface. The Command is driven on the

MA[13:0] lines. MA[2:0] must always be driven to 010 for burst of 4 mode. MA3 must be

driven to 1 for interleave wrap type. MA[4] needs to be driven to the value programmed in

the CAS# Latency bit in this register. MA[6:5] should always be driven to 01. MA[12:7]

must be driven to 000000. BIOS must calculate and drive the correct host address for each

row of memory such that the correct command is driven on the MA[12:0] lines.

100 CBR Cycle Enable (CBRE). When set to this mode, all CPU cycles to SDRAM are

converted to SDRAM CBR refresh cycles on the memory interface.

101 Reserved.

11- Reserved

4 Force ECC – R/W. 1 = drive all ECC bits to 0 during SDRAM write cycles. This is useful to allow

the ECC checking hardware to be automatically checked. 0 = normal operation, write drive normal

ECC bits. This bit has no effect on SDRAM read cycles.

3 Enhanced Paging Enable – R/W. 0 = close SDRAM rows after each access is performed. 1 = keep

rows open until a refresh occurs.

2 CAS# Latency (CL) – R/W. 0 = CAS Latency is 3 SDRAM clocks. 1 = CAS Latency is 2 SDRAM

clocks

1 SDRAM RAS# to CAS# Delay – R/W. This bit controls the number SDRAM clocks from a Row

Activate command to a read or write command.

0 = 3 clocks will be inserted

1 = 2 clocks will be inserted

0 SDRAM RAS# Precharge – R/W. This bit controls the number of SDRAM clocks for RAS#

precharge.

0 = 3 clocks of RAS# precharge

1 = 2 clocks of RAS# precharge.

60 Subject to Change Advance Information


4.15.19 PGPOL, Paging Policy Register: A=0.78, R=0000

Bit Description

15:12 Reserved. Hardwired to 0.

R

11:8 Banks per Row (BPR) – R/W. Each bit in this field corresponds to one row of the memory array.

For example, bit 11 corresponds to row 3, bit 10 corresponds to row 2, etc. Each bit specifies what

type of base SDRAM is being used in the row: 2-bank or 4-bank parts. The 82600 can support up

to four pages being open in rows that contain SDRAM chips that are internally organized with four

banks.

0 = 2 bank parts

1 = 4 bank parts.

7:0 Reserved. Hardwired to 0.

4.15.20 MCTL, Miscellaneous Control Register: A=0.7A, R=00

Bit Description

7 Reserved. Hardwired to 0.

6 Power Management Control Register Enable – R/W. When set to 0, any local processor access

to I/O address 0x22 will not access the Power Management Register. Instead, if the South Bridge

features are enabled in the Miscellaneous Function Enable Register, a BRDY# will be issued to

terminate the access without any register being accessed. When set to 1, the “Arbiter Disable” bit

may be set in the Power Management Register at I/O address 0x22 provided the South Bridge

features are enabled in the Miscellaneous Function Enable Register. If the South Bridge features

are disabled an access to I/O address 0x22 is always sequenced to the LPCI bus.

5:0 Reserved. Hardwired to 0.

4.15.21 LAAR, Local Abort Address Register: A=0.7C, R=0000_0000

Bit Description

31-0 Abort Address - RO. The Abort Address Register latches the appropriate abort address whenever

the “OR” of the two “abort” status bits (the Received Master and Received Target Abort Status

bits in the LPCI Status Register) is asserted. If both abort bits are set, the Local Abort Address

register will contain the address of the “first” (in time) abort address that occurred. This register is

read-only and is only valid when at least one of the two abort status bits are set. A new abort

address can be loaded only after clearing the abort status bits in the LPCI Status Register before a

new LPCI abort occurs. If a memory transfer was in progress when the abort occurred a Dword

aligned address will be loaded into this register. If an I/O transfer was in progress the true address

will be loaded into this register.

Advance Information Subject to Change 61


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4.15.22 EAP, Error Address Pointer Register: A=0.80, R=0000_0000

Bit Description

31 Disable Hardware Scrubbing – R/W. When this bit is clear, a single bit error detected on a

SDRAM memory read will be automatically corrected by the hardware by writing the corrected 8byte

word back to memory. When this bit is set, the hardware returns corrected read data to the

processor in response to the original read request but does not update memory with the corrected

word. When set, software may determine if a hard single bit error occurred and then can optionally

scrub the location.

30:12 Error Address Pointer - RO. This field stores the upper 19 bits of the 32 bit memory address that

caused a single or multiple bit error to be detected by the SDRAM controller. Once this field is

latched, it cannot record another ECC error occurrence until multiple and single bit error status bits

(bits 1 and 0 of this register) have been cleared.

11:4 ECC Syndrome Bits. This field stores the 8-bit syndrome for the ECC single or multiple bit error

that was by the SDRAM controller. Once this field is latched, it cannot record another ECC error

occurrence until multiple and single bit error status bits (bits 1 and 0 below) have been cleared.

3 Enable BSERR# on Multiple Bit Error – R/W. 1 = Enable. 0 = Disable. When enabled, BSERR# is

asserted independent of whether the access was initiated from the local host, a DMA controller, or

one of the PCI buses. NMI is also signaled to the local host if enabled by the Disable NMI bit in the

RTC Index Register and the Enable Parity NMI bit in the PortB Register.

2 Enable NMI on Single Bit Error – R/W. 1 = Enable signaling NMI on any single bit ECC error. The

Disable NMI bit in the RTC Index Register and the Enable Parity NMI bit in the PortB Register must

also enable NMI for NMI to be signaled. 0 = Disable.

1 Multiple Bit Error (MBE). R/WC. 1 = An uncorrectable multiple bit error has occurred and the

Error Address Pointer contains the offending address. 0 = multiple bit error address has not been

latched into the Error Address Pointer. If the Single Bit Error (SBE) status bit is set, a multiple bit

error will not be recorded and the Error Address Pointer will continue to latch the address that was

present when the single bit error occurred. Writing a 1 to this bit position clears the status bit, if it

is set. Writing a 0 has no effect.

0 Single Bit Error (SBE). R/WC. 1 = A correctable single bit error has occurred and the Error

Address Pointer contains the offending address. 0 = A single-bit error address has not been

latched into the Error Address pointer. If the Multiple Bit Error (MBE) status bit is set, a single bit

error will not be recorded and the Error Address Pointer will continue to latch the address that was

present when the multiple bit error occurred. Writing a 1 to this bit position clears the status bit, if it

is set. Writing a 0 has no effect. This bit and the Multiple Bit Error bit must be cleared to allow the

next ECC error occurrence to update the error address pointer.

62 Subject to Change Advance Information


4.15.23 POB, Power-On Option Bit Register: A=0.90, R={0,MA[14:0]}

Bit Description

15 Reserved. Hardwired to 0.

R

14:0 Power-On Option Bits - RO. Many of these bits are used to control 82600 pin configurations. These

bits are latched by PWRGOOD from the SDRAM address bus MA[14:0] respectively. For a

description of the bit functions refer to Table 1.

4.15.24 CPO, COM Port Option Register: A=0.92, R=12

Bit Description

7 IRDA Enable – R/W. When set, this bit enables IRDA encoding/decoding on the COM1 RX/TX

pins. It also disables the other COM1 inputs by setting the inputs to the inactive or negated state.

6 Reserved. Reserved for a test function. This bit should always be written to 0.

5:0 HCLK Divisor– R/W. The HCLK clock is divided down by the value in this register multiplied by 2

to form the COM clock inputs. The value in this register is used by a preloadable count down

counter. When the counter reaches 1, it toggles the internal COMCLK signal and reloads the

counter from COMCLK divisor register. COMCLK = HCLK/(divisor*2). A value of 3 or less in this

register will cause an IRDA internal loopback check to be performed. For normal operation a value >

3 needs to be supplied.

4.15.25 PWRMGT/Extended Functions Configuration Register: A=0.94, R=0000

This register is used to locate the power management, SMBus, and Digital I/O functions in a 128 byte block of I/O

space. In addition it is used to configure SMBus features. The reset value of this register should be overwritten

before the power management function is enabled in the Miscellaneous Function Enable Register.

Bit Description

15:7 I/O Address Base (PWRBASE) – R/W. These bits are compared against I/O address bits 15:7 to

determine where the Power Management and Extended Function Registers map into the I/O

address space.

6:2 Reserved. Hardwired to 0.

1 IRQEN – R/W. When set, IRQ9 (level sensitive) will be asserted when any of the following SMBus

events occur: transmit done, negative acknowledge, lost arbitration, time-out, or SMB data is

available to be read.

0 Reserved. Hardwired to 0.

Advance Information Subject to Change 63


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4.15.26 MFE, Miscellaneous Function Enable Register: A=0.96, R=(see description)

Bit Description

15:10 Reserved. Hardwired to 0.

9 Test Counters. When set this bit allows multiple counters within the 82600 to be easily tested.

This bit should be cleared for normal system operation.

8 Disable Internal Keyboard Controller – R/W. 1 = Disable. 0 = Enabled. When disabled, accesses

to the internal keyboard controller are ignored and sent to the LPCI bus. This affects the Keyboard

Controller Data Register and the Keyboard Controller Status/Command Register. Reset to 0.

7 Enable PC/PCI DMA Support – R/W. 1 = Enabled. 0 = Disabled. When enabled, the LREQ3# pin

becomes an ISA REQ# pin and LGNT3# becomes an ISA GNT# pin to support an ISA bridge

PC/PCI DMA Protocol. When disabled, the LREQ3# and LGNT3# serve as a LPCI request and

grant pair. Reset to 0.

6 Enable PCI Configuration Function 1 (EIDE Registers) – R/W. When clear, this disables access

to both the EIDE PCI configuration registers as well as the hardwired (0x1F0-0x1F7 and 0x3F6) I/O

addresses. In this mode the EIDE pins are available for use as general-purpose digital I/O. When

disabled, IRQ14 for other external peripheral functions must still be connected. At power-on, the

inversion of power-on option bit MA0 is loaded into this bit when PWRGOOD is negated.

5 Enable PCI Configuration Function 2 (USB Registers) – R/W. When clear, this disables access to

the USB configuration and I/O access spaces. When set, the function 2 registers can be accessed.

Reset to 0.

4 Disable South Bridge Features – R/W. 1 = Disabled, 0 = Enabled. When disabled, this bit

disables routing I/O accesses at addresses 0x0 - 0x0100 and 0x04D0 - 0x4D1, 0xCF9 to the 82600

internals. These accesses are instead sent to the LPCI interface. Reset to 0.

3 COM1 Enable – R/W. 1 = Enabled, 0 = Disabled. When enabled, COM1 I/O (0x3F8-0x3FF)

addresses are directed toward the internal 16550 and the internal COM1 port may generate IRQ4

interrupts. When disabled, the internal COM1 port is not accessible and the I/O address and IRQ

resources are available to be assigned elsewhere. When the COM1 port is disabled the pins are

available for use as general purpose digital I/O. The inversion of power-on option bit MA7 is

loaded when PWRGOOD is negated.

2 COM2 Enable – R/W. 1 = Enable, 0 = Disable. When enabled COM2 I/O (0x02F8-0x02FF)

addresses are directed toward the internal 16550 and the internal COM2 port may generate IRQ3

interrupts. When disabled, the internal COM2 port is not accessible and the I/O address and IRQ

resources are available to be assigned elsewhere. When COM2 is enabled ECC is automatically

disabled. When COM2 is disabled the pins are available for use as SDRAM ECC pins. The

inversion of power-on option bit MA6 is loaded when PWRGOOD is negated.

1 Enable Power Management and SMBus I/O Decode – R/W. 1 = Enable, 0 = Disable. This enables

the internal decode of the internal Power Management and SMBus I/O registers beginning at any

128 byte I/O address boundary specified by bits [15:7] of the PWRBASE configuration register.

Reset to 0.

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Bit Description

0 Enable BPCI Extended Arbitration – R/W. 1 = Enable, 0 = Disable. This enables the BREQ[6:3]#

and BGNT[6:3]# pins in/out of the BPCI arbiter. When clear the BREQ inputs into the arbiter are

negated and the external pins may be used for Digital I/O functions. The inversion of power-on

option bit MA1 is loaded when PWRGOOD is negated.

4.15.27 LIRQRC[A:D], LIRQX Route Control Registers: A=0.A0-0.A3, R=0x80

R

These registers define the LPCI interrupt pin routing to the internal IRQ lines supported by the 8259s. Register 0.A0

defines the routing for LPIRQA#, 0.A1 defines the routing for LPIRQB#, etc. Two or more of the LPCI interrupt pins

can be routed to the same 8259 interrupt input. In this case the LPCI interrupt pins are ORed at the 8259 interrupt

input. All 8259 interrupt inputs that are connected to LPCI interrupt pins using these registers must be set to accept

level sensitive interrupts in the Edge/Level Control Registers. BPCI interrupt pins may also be routed to the same

8259 interrupt inputs used by the LPCI interrupt pins. In this case, the BPCI interrupt pins are ORed with the LPCI

interrupt pins sharing the same 8259 interrupt input.

Bit Description

7 Interrupt Routing Enable – R/W. 0 = Enable, 1 = Disable.

6:4 Reserved. Hardwired to 0.

3:0 Interrupt Routing – R/W. When bit 7 = 0, these bits select the routing of one of the LPIRQx

interrupt input pins to one of the 8259 interrupt inputs. The four bits encode the 8259 IRQx input

as 4-bit binary number (e.g. a 1111 entry means that the LPCI interrupt will be routed to IRQ15).

0,1,2,8,13 and 14 encodings are reserved and should not be used.

4.16 Device 0, Function 1 Registers (PCI EIDE Configuration Registers)

These configuration registers can only be accessed from the local host by generating I/O accesses to the LPCI/BPCI

Configuration Data Register after first specifying the exact register with a 32 bit I/O write cycle to the LPCI/BPCI

Configuration Index Register. The register descriptions below specify the address using only the LPCI configuration

function number and register number as follows: A = . , R = . If

the EIDE function is enabled in Miscellaneous Function Enable Register, the local host processor can access these

registers without generating a PCI bus cycle by setting its PCI Configuration Index Bus Number and Device Number

fields to 0 and its function number field to 1. The 82600 does not allow access to these registers from either PCI

interface.

4.16.1 VID1, Vendor Identification Register: A=1.0, R=1331

Bit Description

15:0 Vendor Identification Register - RO. This is hardwired to the RadiSys vendor ID: 1331.

4.16.2 DID1, Device Identification Register: A=1.2, R=8201

Bit Description

15:0 Device Identification Register - RO. This is hardwired to 8201.

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4.16.3 PCICMD1, PCI Command Register: A=1.4, R=0000

Bit Description

15:3 Reserved. Hardwired to 0.

2 Bus Master Enable – R/W. Setting/clearing does not effect 82600 operation.

1 Memory Access Enable. This bit is hardwired to 0.

0 I/O Access Enable (IOAE) – R/W. This bit controls access to the I/O space registers. When IOAE

= 1, access to the primary EIDE ports is enabled. The base address register for the EIDE I/O

Registers in the Bus Master Interface Address Register should be programmed before this bit is set

to 1

4.16.4 PCISTS1, PCI Status Register: A=1.6, R=0000

Bit Description

15:0 All bits. Hardwired to a 0.

4.16.5 RID, Revision Identification Register: A=1.8, R=0000

Bit Description

7:0 Revision Identification Register - RO. The EIDE RID is 00.

4.16.6 CLASSC, Class Code Register: A=1.9, R=01_0180

This register is read-only from the host interface. This register is not accessible from either PCI interface.

Bit Description

23:16 Base Class Code. This is hardwired to 01(Mass storage)

15:8 Sub Class Code. This is hardwired to 01 (IDE).

7:0 Programming Interface. This is hardwired to 80 (Capable of DMA operation)

4.16.7 MLT, Master Latency Timer: A=1.D, R=00

Bit Description

7:3 Master Latency Timer Count Value – R/W. These bits have no effect on the hardware since the

EIDE Ultra DMA goes directly to the SDRAM and does not use the LPCI bus.

2:0 Reserved. Hardwired to 0.

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4.16.8 HEDT1, Header Type Register: A=1.0E, R=00

This register defines the 82600 IDE controller as a single function device.

Bit Description

7:0 Device Type. Hardwired to 00.

4.16.9 BMIBA1, Bus Master Interface Address: A=1.20, R=0000_0001

R

This register selects a 16 byte I/O address space for the IDE Bus Master Interface registers. Programmed I/O

operations are independent of this address space and use I/O address 0x1F0-0x1F7 and 0x3F6 as the operational

registers.

Bit Description

31:16 Reserved. Hardwired to 0.

15:4 Bus Master Interface Address (IDE_BASE) – R/W. These bits provide the base address for the

Bus Master Interface Register and are compared to I/O address bits AD[15:4].

3:1 Reserved. Hardwired to 0.

0 Resource Type Indicator. Hardwired to 1 to indicate that the base address field in this register

maps to I/O space.

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4.16.10 IDETIM, IDE Timing Register: A=1.40, R=0000

This register controls the timing of PIO modes and standard bus master transfers. Drive 0 and 1 denote master and

slave IDE drives respectively.

Bit Description

15:14 Reserved. Hardwired to 0.

13:12 IORDY Sample Point (ISP) – R/W. This field defines the number of LPCI clocks inserted between

the EIOx# signal assertion and the first IORDY sample point.

Bits[13:12] Number of Clocks PIO Mode

00 5 1

01 4 2

10 3 3

11 2 4

11:10 Reserved. Hardwired to 0.

9:8 Recovery Time (RCT) – R/W. This field selects the minimum number of LPCI clocks between the

last IORDRY# sample point and the EIOx# strobes assertion in the next cycle.

Value Number of Clocks PIO Mode

00 4 1

01 3 2

10 2 3

11 1 4

7:6 Reserved. Hardwired to 0.

5 Drive 1 IORDY Sample Point Enable (IE1) – R/W. When IE1 = 0, IORDY sampling is disabled for

drive 1. The internal IORDY is forced asserted at the first sample point specified by the ISP field in

this register. When IE1 = 1 and the drive 1 is selected (via a copy of bit 4 of 0x1F6), all accesses to

0x1F0-0x1F7 or 0x3F6 sample IORDY. The ISP field in this register specifies the IORDY sample

point.

4 Drive 1 Fast Timing Select– R/W. 1 = Enable, 0 = Disable. When enabled, accesses to drive 1

(copy of bit 4 of 0x1F6) use the PIO mode timing specified by the IORDY Sample Point and

Recovery Time fields of this register for I/O accesses to 0x1F0. When 0, PIO mode 0 timings are

used for accesses to 0x1F0. This bit does not effect the timing of accesses to 0x1F1-0x1F7 and

0x3F6. These accesses always use PIO mode 0 timings.

3:2 Reserved. Hardwired to 0.

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1 Drive 0 IORDY Sample Point Enable (IE0) – R/W. When IE0 = 0, IORDY sampling is disabled for

drive 0. The internal IORDY is forced asserted at the first sample point specified by the ISP field in

this register. When IE0 = 1 and the drive 0 is selected (via a copy of bit 4 of 0x1F6), all accesses to

0x1F0-0x1F7 or 0x3F6 sample IORDY. The ISP field in this register specifies the IORDY sample

point.

0 Drive 0 Fast Timing Select – R/W. 1 = Enable, 0 = Disable. When enabled, accesses to drive 0

(via a copy of bit 4, 0x1F6) use the PIO mode timing specified by the IORDY Sample Point and

Recovery Time fields of this register for I/O accesses to 0x1F0. When 0, PIO mode 0 timings are

used for accesses to 0x1F0. This bit does not effect the timing of accesses to 0x1F1-0x1F7 and

0x3F6. These accesses are always use PIO mode 0 timings.

4.16.11 UDMACTL, Ultra DMA/66 Control Register: A=1.48, R=00

Bit Description

7:2 Reserved. Hardwired to 0.

1 Drive 1 UDMA Enable – R/W. 1 = Enable Ultra DMA/66 mode for primary channel drive 1. 0 =

Disable.

0 Drive 0 UDMA Enable – R/W. 1 = Enable Ultra DMA/66 mode for primary channel drive 0. 0 =

Disable

4.16.12 UDMATIM, Ultra DMA/66 Timing Register: A=1.4A, R=00

Bit Description

7:6 Reserved. Hardwired to 0.

R

5 Drive 1Fast Cycle Time – R/W. When 0, the minimum write cycle time is 4 LPCI clocks and Ready

to Pause time is 6 LPCI clocks. When 1, write cycle time is 2 LPCI clocks and Ready to Pause time is

4 LPCI clocks.

4:2 Reserved. Hardwired to 0

1 Drive 0 Fast Cycle Time – R/W. When 0, the minimum write cycle time is 4 LPCI clocks and Ready

to Pause time is 6 LPCI clocks. When 1, write cycle time is 2 LPCI clocks and Ready to Pause time

is 4 LPCI clocks.

0 Reserved. Hardwired to 0.

4.17 IDE Bus Master Controller I/O Space Registers

The bus master portion of the IDE controller consumes six bytes of direct PC I/O address space. The base of these

I/O registers are pointed to by the Bus Master Interface Address Register[15:4]. In the register descriptions, these

bits are referred to as IDE_BASE.

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4.17.1 BMICX, Bus Master IDE Command Register: A=IDE_BASE+0, R=00

Bit Description

7:4 Reserved. Hardwired to 0.

3 Bus Master Read/Write Control – R/W. 0 = Reads; 1 = Writes. This bit must not be changed

during a DMA transfer. Between transfers this bit can be written to allow setup of the next DMA

transfer direction.

2:1 Reserved. Hardwired to 0.

0 Start/Stop Bus Master – WO. 1 = Start; 0 = Stop. This is a write only bit. All reads return 0.

When this bit is 1, a bus master operation starts. The controller transfers data between the IDE

device and memory only while this bit is set. Writing a 0 to this bit can stop master operation.

This results in all state information being lost.

If this bit is set 0 while bus master operation is still active and the IDE device has not yet finished

its data transfer, the bus master command is aborted and data transferred from the IDE device may

be discarded rather than being written to system memory. This bit is intended to be set to 0 after a

data transfer is completed, as indicated by either bit 0 or bit 2 being set in the IDE Channels’ Bus

Master IDE Status Register.

4.17.2 BMISX, Bus Master IDE Status Register: A=IDE_BASE+2, R=00

Bit Description

7 Reserved. Hardwired to 0.

6:5 Drive DMA Capable – R/W. These bits have no effect on hardware. They may be read/written to

indicate whether drive 1 or 0 is DMA capable. Bit 6 is normally associated with Drive 1 and bit 5

with Drive 0.

4:3 Reserved. Hardwired to 0

2 IDE Interrupt Status – R/WC. This bit, when set to a 1, indicates when an IDE device has

asserted IRQ14. When bit 2 = 1, all read data from the IDE device has been transferred to main

memory and all write data has been transferred to the IDE device. Software sets this bit to a 0 by

writing a 1 to it. Once cleared, the status bit will only be set again by another assertion edge on

IRQ14. The relationship between the status of bit 2 and bit 0 is described in Table 6.

1 Reserved. Hardwired to a 0

0 Bus Master IDE Active – RO. This read-only status bit is set 1 when bit 0 of the BMICX register

is set to a 1 signaling the start of a bus master operation. This bit is cleared when the last transfer

for a region is performed (where EOT for that region is set in the region descriptor) or when bit 0 of

the BMICX register is set to 0. When cleared by the first mechanism, all data transferred from the

drive is available in system memory. The relationship between the status of bit 2 and bit 0 is

described in Table 6.

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BMISX Bit 2 BMISX Bit 0 Description

Table 6 Interrupt/Activity Status Combinations

R

0 1 DMA Transfer is in progress. No interrupt has been generated by the IDE

device.

1 0 The IDE device generated an interrupt and the Physical Region Descriptors are

exhausted. This is the normal completion where the size of the physical memory

regions is equal to the IDE device transfer size.

1 1 The IDE device generated an interrupt. He controller has not reached the end of

the physical memory regions. This is a valid completion case when the size of the

physical memory regions is larger than the IDE device transfer size.

0 0 Error condition. If the IDE DMA Error bit is 1, there is a problem transferring

data to/from memory. Specifics of the error have to be determined using busspecific

information. If the Error bit is 0, the PRD specified a smaller buffer size

than the programmed IDE transfer size.

4.17.3 BMIDTPX, Bus Master IDE Descriptor Table Pointer Register:

A=IDE_BASE+4, R=0000_0000

This register provides the base memory address of the Descriptor Table. The Descriptor Table must be Dword

aligned and not cross a 4-Kbyte boundary in memory.

Bit Description

31:2 Descriptor Table Base Address (DTBA) – R/W. Bits[31:2] correspond to HA[31:2].

1:0 Reserved. Hardwired to 0.

4.18 Device 0, Function 2 (USB) Configuration Registers

These configuration registers can only be accessed from the local processor by generating I/O accesses to the

LPCI/BPCI Configuration Data Register after first specifying the exact register with a 32 bit I/O write cycle to the

LPCI/BPCI Configuration Index Register. The register descriptions below specify the address using only the LPCI

configuration function number and register number as follows: A = ., R =

Reset value. The local processor can access these registers without generating a PCI bus cycle by setting its PCI

Configuration Index Bus Number and Device Number fields to 0 and its Function Number Field to 2. The 82600 does

not allow access to these registers from the LPCI or BPCI interface.

4.18.1 VID2, Vendor Identification Register: A=2.0, R=1331

Bit Description

15:0 Vendor Identification Register. This is hardwired to the RadiSys vendor ID: 1331.

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4.18.2 DID2, Device Identification Register: A=2.2, R=8202

Bit Description

15:0 Device Identification Register. This is hardwired to 8202.

4.18.3 PCICMD2, PCI Command Register: A=2.4, R=0000

Bit Description

15:3 Reserved. Hardwired to 0.

2 Bus Master Enable – R/W. Setting/clearing does not effect 82600 operation. This bit is provided

for legacy software support. This functionality is not required by the 82600 since DMA transfers

between the USB ports and main memory do not use either the LPCI or BPCI buses.

1 Memory Access Enable. This bit is hardwired to 0.

0 I/O Access Enable (IOAE) – R/W. This bit controls access to the I/O space registers. When IOAE

= 1, access to the USB I/O registers is enabled. The base address register for the USB I/O registers

in the USB Base Address Register (USBBA) must be programmed before this bit is set to 1

4.18.4 PCISTS2, PCI Status Register: A=2.6, R=0000

Bit Description

15:0 All bits. Hardwired to a 0.

4.18.5 RID, Revision Identification Register: A=2.8, R=0000

Bit Description

7:0 Revision Identification Register. The USB RID is 00.

4.18.6 CLASSC2, Class Code Register: A=2.9, R=0C_0300

This register is read-only from the local host. This register is not accessible from either the LPCI or BPCI interfaces.

Bit Description

23:16 Base Class Code. This is hardwired to 0C (Serial bus controller)

15:8 Sub Class Code. This is hardwired to 03 (Universal Serial Bus Host Controller)..

7:0 Programming Interface. This is hardwired to 00 (Universal Host controller interface)

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4.18.7 MLT2, Master Latency Timer: A=2.D, R=00

Bit Description

R

7:3 Master Latency Timer Count Value – R/W. These bits have no effect on the hardware since the

USB DMA function in the 82600 passes data directly to/from main memory without using either the

LPCI or BPCI buses.

2:0 Reserved. Hardwired to 0.

4.18.8 HEDT2, Header Type Register: A=2.E, R=00

Bit Description

7:0 Device Type. Hardwired to 00. Multi-function type is defined in the Function 0 Header Register

LHT.

4.18.9 USBBA, USB Base Address Register: A=2.20, R=0000_0001

This register selects a 32 byte I/O address space for the USB host controller registers.

Bit Description

31:16 Reserved. Hardwired to 0.

15:5 USB Controller I/O Base Address (USB_BASE) – R/W. These bits are compared to I/O address

bits AD[15:5].

4:1 Reserved. Hardwired to 0.

0 Resource Type Indicator. Hardwired to 1 (indicates an I/O base address)

4.18.10 INTL, Interrupt Line Register: A=2.3C, R=00

Bit Description

7:0 Interrupt Line – R/W. These bits are for software interpretation only. The value in this register

has no effect on the hardware.

4.18.11 INTP, Interrupt Pin Register: A=2.3D, R=04

Bit Description

7:3 Reserved. Hardwired to 0.

2:0 Interrupt Routing - RO. These bits are hardwired to 100b to indicate that the USB will signal

interrupts through the LIRQD# interrupt signal. The USB interrupts are internally ORed with the

LIRQD# signal.

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4.18.12 SBRNUM, Serial Bus Release Number: A=2.60, R=11

Bit Description

7:0 Release Number. This is hardwired to 11 to indicate that the USB is designed to Release 1.1 of the

USB specification.

4.19 USB Host Controller I/O Space Registers.

These registers can be accessed after the USB Base Address Register (USBBA) is set to point to this I/O space and

the I/O Access Enable bit is set in the PCI Command Register (PCICMD2). The Base indicated in the addresses for

these registers is contained in USBBA Register bits [15:5] and is denoted as USB_BASE.

4.19.1 USBCMD-USB Command Register: A=USB_BASE+0, R=0000

The Command Register indicates the command to be executed by the serial bus host controller. Writing to the

register causes a command to be executed. Table 7 provides additional information on the operation of the Run/Stop

and Debug bits.

Bit Description

15:8 Reserved. Hardwired to 0

7 Max Packet (MAXP) – R/W. 1 = 64 bytes. 0 = 32 bytes. This bit selects the maximum packet size

that can be used for full speed bandwidth reclamation at the end of a frame. This value is used by

the Host Controller to determine whether it should initiate another transaction based on the time

remaining in the SOF counter. Use of reclamation packets larger than the programmed size will

cause a Babble error if executed during the critical window at frame end. The Babble error results in

the offending endpoint being stalled. Software is responsible for ensuring that any packet that

could be executed under bandwidth reclamation is within this size limit.

6 Configure Flag (CF) – R/W. Hardware Configuration Definition (HCD) software sets this bit as

the last action in its process of configuring the Host Controller. This bit has no effect on the

hardware. It is provided only as a semaphore service for software.

5 Software Debug (SWDBG) – R/W. 1 = Debug mode. 0 = Normal Mode. In SW Debug mode, the

Host Controller clears the Run/Stop bit after the completion of each USB transaction. The next

transaction is executed when software sets the Run/Stop bit back to 1. The SWDBG bit must only

be manipulated when the controller is in the stopped state. This can be determined by checking

the HCHalted bit in the USBSTS register.

4 Force Global Resume (FGR) – R/W. 1 = Host Controller sends the Global Resume signal on the

USB. Software sets this bit to 0 after 20 ms have elapsed to stop sending the Global Resume

signal. At that time all USB devices should be ready for bus activity. The Host Controller sets this

bit to 1 when a resume event (connect, disconnect, or K-state) is detected while in global suspend

mode. Software resets this bit to 0 to end Global Resume signaling. The 1 to 0 transition causes

the port to send a low speed EOP signal. This bit will remain a 1 until the EOP has completed.

74 Subject to Change Advance Information


Bit Description

3 Enter Global Suspend Mode (EGSM) – R/W. 1 = Host Controller enters the Global Suspend mode.

No USB transactions occur during this time. The Host Controller is able to receive resume signals

from USB and interrupt the system. Software resets this bit to 0 to come out of Global Suspend

mode. Software writes this bit to 0 at tie same time that Force Global Resume (bit 4) is written to 0

or after writing bit 4 to 0. Software must also ensure that the Run/Stop bit (bit 0) is cleared prior to

setting this bit

2 Global Reset (GRESET) – R/W. When this bit is set the Host Controller sends the global reset

signal on the USB and then resets all its logic, including the internal hub registers. The hub

registers are reset to their power on state. This bit is reset by the software after a minimum of 1 0

ms has elapsed as specified in Chapter 7 of the USB Specification.

Note: Chip Hardware Reset has the same effect as Global Reset (bit 2), except that the Host

Controller does not send the Global Reset on USB.

1 Host Controller Reset (HCRESET) – R/W. When this bit is set, the Host Controller module resets

its internal timers, counters, state machines, etc. to their initial value. Any transaction currently in

progress on USB is immediately terminated. The Host Controller resets this bit when the reset

process is complete.

R

The HCReset effects on Hub registers are slightly different from Chip Hardware Reset and Global

USB Reset. The HCReset affects bits [8,3:0] of the Port Status and Control Register (PORTSC) of

each port. HCReset resets the state machines of the Host Controller including the

Connect/Disconnect state machine (one for each port). When the Connect/Disconnect state

machine is reset, the output that signals connect/disconnect are negated to 0, effectively signaling

a disconnect, even if a device is attached to the port. This virtual disconnect causes the port to be

disabled. This disconnect and disabling of the port causes bit 1 (Connect Status Change) and bit 3

(Port Enable/Disable Change) of the PORTSC to get set. The disconnect also causes bit 8 of

PORTSC to reset. About 64-bit times after HCReset goes to 0, the connect and low-speed detect

will take place and bits 0 and 8, of the PORTSC will change accordingly.

0 Run/Stop (RS) – R/W. 1 = Run. 0 = Stop. When set to a 1, the Host Controller proceeds with

execution of the schedule. The Host Controller continues execution as long as this bit is set.

When this bit is set to 0, the Host Controller completes the current transaction on the USB and

then halts. The HCHalted bit in the status register indicates when the Host Controller has finished

the transaction and has entered the stopped state. The Host Controller clears this bit when the

following fatal errors occur: consistency check failure, PCI Bus errors.

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SWDBG

(bit 5)

Run/Stop

(bit 0)

Table 7: Summary of Run/Stop, Debug Bit Interaction

Operation

0 0 If executing a command, the Host Controller completes the command and then

stops. The 1.0 ms frame counter is reset and command list execution resumes from

start of frame using the frame list pointer selected by the current value in the

FRNUM register. (While Run/Stop = 0, the FRNUM register can be

reprogrammed.)

0 1 Execution of the command list resumes from Start Of Frame using the frame list

pointer selected by the current value in the FRNUM register. The Host Controller

remains running until Software or Hardware clears the Run/Stop bit.

1 0 If executing a command, the Host Controller completes the command and then

stops and the 1.0 ms frame counter is frozen at its current value. All status are

preserved. The Host Controller begins execution of the command list from where

it left off when the Run/Stop bit is set.

1 1 Execution of the command list resumes from where the previous execution

stopped. The Host Controller sets the Run/Stop bit to 0 when a TD is being

fetched. This causes the Host Controller to stop again after the execution of the

TD (single step). When the Host Controller has completed execution, the

HCHalted bit in the Status Register is set.

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4.19.2 USBSTS, USB Status Register: A=USB_BASE+2, R=0000

R

This register indicates pending interrupts and various states of the Host Controller. The status resulting from a

transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by writing a 1 to

it.

Bit Description

15:6 Reserved. Hardwired to 0

5 HCHalted – R/WC. The Host Controller sets this bit to 1 after it has stopped executing as a result

of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (debug

mode or an internal error).

4 Host Controller Process Error– R/WC. The Host Controller sets this bit to 1 when it detects a

fatal error and indicates that the Host Controller suffered a consistency check failure while

processing a Transfer Descriptor. An example of a consistency check failure would be finding an

illegal PID field while processing the packet header portion of the TD. When this error occurs, the

Host Controller clears the Run/Stop bit in the Command Register to prevent further schedule

execution. A hardware interrupt is generated to the system

3 Host System Error– R/WC. The Host Controller sets this bit to 1 when a serious error occurs

during a host system access involving the Host Controller module. When this error occurs, the

Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the

scheduled TDs. A hardware interrupt is generated to the system.

2 Resume Detect– R/WC. The Host Controller sets this bit to 1 when it receives a “RESUME”

signal from a USB device. This is only valid if the Host Controller is in a global suspend state (bit 3

of Command Register = l).

1 USB Error Interrupt – R/WC. The Host Controller sets this bit to 1 when completion of a USB

transaction results in an error condition (e.g., error counter underflow). If the TD on which the

error interrupt occurred also had its IOC bit set, both this bit and bit 0 are set

0 USB Interrupt (USBINT – R/WC). The Host Controller sets this bit to 1 when the cause of an

interrupt is a completion of a USB transaction whose Transfer Descriptor had its IOC bit set.

The Host Controller also sets this bit to 1 when a short packet is detected (actual length field in TD

is less than maximum length field in TD), and short packet detection is enabled in that TD.

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4.19.3 USBINTR, USB Interrupt Enable Register: A=USB_BASE+4, R=0000

This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the

corresponding interrupt is active, an interrupt is generated to the host. The host controller cannot disable fatal errors

(Host Controller Processor Error bit 4, USBSTS Register). Interrupt sources that are disabled in this register still

appear in the Status Register to allow software to poll for events.

Bit Description

15:4 Reserved. Hardwired to 0

3 Short Packet Interrupt Enable – R/W. 1 = Enabled. 0 = Disabled.

2 Interrupt On Complete (IOC) Enable – R/W. 1 = Enabled. 0 = Disabled

1 Resume Interrupt Enable – R/W. 1 = Enabled. 0 = Disabled

0 Time-out/CRC Interrupt Enable – R/W. 1 = Enabled. 0 = Disabled

4.19.4 FRNUM, Frame Number Register: A=USB_BASE+6, R=0000

Bits [10:0] of this register contain the current frame number that is included in the frame SOF packet. This register

reflects the count value of the internal frame number counter. Bits [9:0] are used to select a particular entry in the

Frame List during schedule execution. This register is updated at the end of each frame time.

This register must be written as a word. Byte writes are not supported. This register cannot be written unless the

Host Controller is in the STOPPED state as indicated by the HCHalted bit (USBSTS register). A write to this register

while the Run/Stop bit is set (USBCMD register) is ignored.

Bit Description

15:11 Reserved. Hardwired to 0

10:0 Frame List Current Index/Frame Number – R/W. Bits [10:0] provide the frame number in the SOF

Frame. The value in this register increments at the end of each time frame (approximately every 1

ms). In addition, bits [9:0] are used for the Frame List current index and correspond to memory

address signals [11:2].

4.19.5 FLBASEADD, Frame List Base Address Register:

A=USB_BASE+8, R =xxxx_xxxx

This 32-bit register contains the beginning address of the Frame List in the system memory. HCD loads this register

prior to starting the schedule execution by the Host Controller. When written, only the upper 20 bits are used. The

lower 12 bits are written as 0 (4-Kbyte alignment). The contents of this register are combined with the frame number

counter to enable the Host Controller to step through the Frame List in sequence. The two least significant bits are

always 00. This requires Dword alignment for all list entries. This configuration supports 1,024 Frame List entries.

Bit Description

31:12 Base Address – R/W. These bits correspond to memory address signals[31:12], respectively

11:0 Reserved. Must be written to 0s.

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4.19.6 SOFMOD, Start of Frame (SOF) Modify Register: A=USB_BASE+C, R=40

R

This 1-byte register is used to modify the value used in the generation of SOF timing on the USB. Only the seven

least significant bits are used. When a new value is written into these 7 bits, the SOF timing of the next frame will be

adjusted. This feature can be used to adjust out any offset from the clock source that generates the clock that drives

the SOF counter. This register can also be used to maintain real time synchronization with the rest of the system so

that all devices have the same sense of real time. Using this register, the frame length can be adjusted across the full

range required by the USB specification. Its initial programmed value is system dependent based on the accuracy of

hardware USB clock and is initialized by the system BIOS. It may be reprogrammed by USB system software at any

time. Its value will take effect from the beginning of the next frame. This register is reset upon a Host Controller

Reset or Global Reset. Software must maintain a copy of its value for reprogramming if necessary.

Bit Description

7 Reserved. Hardwired to 0.

6:0 SOF Timing Value – R/W. Guidelines for the modification of frame time are contained in Chapter 7

of the USB Specification. The SOF cycle time (number of SOF counter clock periods to generate a

SOF frame length) is equal to 11,936 + value in this field. The default value is decimal 64 which

gives a SOF cycle time of 12,000. For a 12-MHz SOF counter clock input, this produces a 1 -ms

Frame period. The following table indicates what SOF Timing Value to program into this field for a

certain frame period.

Frame Length

(# 12 MHz Clocks)

(decimal)

SOF Reg Value

(decimal)

11,936 0

11,937 1

. .

. .

11,999 63

12,000 64

12,001 65

. .

. .

12,062 126

12,063 127

4.19.7 PORTSC, Port Status and Control Register:

Port 0 A=USB_BASE+10, R=0080 Port 1 A=USB_BASE+12, R=0080

After a Power-up reset, Global reset, or Host Controller reset, the initial conditions of a port are: No device connected,

Port disabled, and the bus line status is 00 (single-ended zero). Note: If a device is attached, the port state will

transition to the attached state and system software will process this as with any status change notification. It may

take up to 64 USB bit times for the port transition to occur. If the Host Controller is in global suspend mode, then, if

any of bits [6,3,1] gets set, the Host Controller will signal a global resume. Refer to Chapter 11 of the USB

Specification for details on hub operation.

Bit Description

15:13 Reserved. Must be written to 0 when writing to this register.

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Bit Description

12 Suspend-R/W. 1 = Port in suspend state. 0 = Port not in suspend state. This bit should not be

written to a 1 if global suspend is active (bit 3 = 1 in the USBCMD register). Bit 2 and bit 12 of this

register define the hub states as follow:

Bits [12,2] Hub Port State

x0 Disable

01 Enable

11 Suspend

When in suspend state, downstream propagation of data is blocked on this port, except for single

ended 0 resets (global reset and port reset). The blocking occurs at the end of the current

transaction, if a transaction was in progress when this bit was written to 1. In the suspend state,

the port is sensitive to resume detection. Note that the bit status does not change until the port is

suspended and that there may be a delay in suspending a port if there is a transaction currently in

progress on the USB.

11 Over-Current Indicator Change-R/WC. 1 = a change from 1 to 0 has been detected on the Overcurrent

(USBOCx#) pin for this port. 0 = No change has been detected. Software sets this bit to 0

by writing a 1 to it.

10 Over-Current Indicator-RO. 1 = Overcurrent pin (USBOCx#) for this port is at logic 0 indicating

overcurrent condition. 0 = Overcurrent pin for this port is at logic 1 indicating a normal condition.

If asserted, the corresponding port is disabled.

9 Port Reset-R/W. 1 = Port is in Reset. 0 = Port is not in Reset. When in the Reset State, the port is

disabled and sends the USB Reset signaling. Note that host software must guarantee that the

RESET signaling is active for the proper amount of time as specified in the USB Specification

8 Low Speed Device Attached -RO. 1 = Low speed device is attached to this port. 0 = Full speed

device. Writes have no effect.

7 Reserved. Hardwired to 1.

6 Resume Detect-R/W. 1 = Resume detected/driven on port. 0 = No resume (K-state)

detected/driven on port. Software sets this bit to a 1 to drive resume signaling. The Host

Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state.

Note that when this bit is 1, a K-state is driven on the port as long as this bit remains 1 and the port

is still in suspend state. Writing a 0 (from 1) causes the port to send a low speed EOP. This bit will

remain a 1 until the EOP has completed.

5:4 Line Status-RO. These bits reflect the D+ (bit 4) and D- (bit 5) signals lines’ logical levels. These

bits are used for fault detection and recovery as well as for USB diagnostics. This field is updated

at EOF2 time (see Chapter 11 of the USB Specification).

3 Port Enable/Disable Change—R/WC. I = Port enabled/disabled status has changed. 0 = No

change. For the root hub, this bit gets set only when a port is disabled due to disconnect on that

port or due to the appropriate conditions existing at the EOF2 point (see Chapter 11 of the USB

Specification). Software clears this bit by writing a 1 to it.

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Bit Description

R

2 Port Enabled/Disabled-R/W. 1 = Enable. 0 = Disable. Ports can be enabled by host software only.

Ports can be disabled by either a fault condition (disconnect event, overcurrent condition, or other

fault condition) or by host software. Note that the bit status does not change until the port state

actually changes and that there may be a delay in disabling or enabling a port if there is a

transaction currently in progress on the USB.

1 Connect Status Change-R/WC 1 = Change in Current Connect Status. 0 = No change. Indicates a

change has occurred in the port’s Current Connect Status (see bit 0). The hub device sets this bit

for any changes to the port device connect status, even if system software has not cleared a

connect status change. If, for example, the insertion status changes twice before system software

has cleared the changed condition, hub hardware will be “setting” an already-set bit (i.e., the bit

will remain set). However, the hub transfers the change bit only once when the Host Controller

requests a data transfer to the Status Change endpoint. System software is responsible for

determining state change history in such a case. Software sets this bit to 0 by writing a 1 to it

0 Current Connect Status-RO. 1 = Device is present on port. 0 = No device is present. This value

reflects the current state of the port, and may not correspond directly to the event that caused the

Connect Status Change bit (Bit 1) to be set.

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4.20 Local I/O Mapped Functions

The power management, SMBus, watchdog timer, digital I/O and BPCI/SDRAM functions are accessed in the local

host’s I/O space that is set by the PWRBASE address stored in the PWRMGT/Extended Functions Configuration

Register.

4.20.1 Power Management Support Registers

4.20.1.1 PMSTS, Power Management Status Register: A=PWRBASE+0, R=0000

Bit Description

15 GLBSTBYTIMEN Status - R/WC. This bit is set if GLBSTDBY/SMI Timer Status bit is set and

the GLBSTDBY/SMI Timer Enable bit is also set. This bit can only be set by hardware and can only

be cleared by writing a 1 to this bit position.

14:11 Reserved.

10 RTC Status (RTC_STS) - R/WC. 1 = RTC Alarm has been signaled. 0 = RTC Alarm has not been

signaled. This bit is set when the internal RTC asserts its IRQ8 signal and the whole chip is

powered-up. This bit is only set by hardware and is reset by writing a 1 to this bit position.

9 Reserved.

8 Power Button Status-R/WC. 1 = PWRBTN# signal has been asserted. 0 = PWRBTN# signal has

not been asserted. There is a 16ms delay from the external signal assertion to the setting of this bit

for internal switch debounce circuitry. This bit is set by hardware only when a debounced edge is

detected on PWRBTN#. It is cleared by writing a 1 to this bit.

7:6 Reserved.

5 Global Status (GLB_STS) - R/WC. This bit is set in response to a “1” being written to the

BIOS_RLS bit. This bit can cleared by writing a “1” to this bit position. When this bit is set and

the Global Status SCI enable bit is also set, an SCI (IRQ9) is signaled.

4:1 Reserved. Hardwired to 0. System Design Note: since bit 4 is a read-only bit that reads 0,

snooping must be enabled in the processor when it is in the Autohalt or Stop Grant state.

0 Timer Overflow Status (TMROF_STS) -R/WC. 1 = Bit 23 of the 24 bit Power Management timer

has toggled. 0 = Bit has not toggled. When the TMROF_EN bit in the PMEN Register is set then

the setting of the TMROF_STS bit will additionally generate an SCI interrupt. This bit is set only

by hardware and is cleared by writing a 1 to this bit position.

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4.20.1.2 PMEN, Power Management Resume Enable Register: A=PWRBASE+2, R=0000

Bit Description

15:11 Reserved. Hardwired to 0.

10 RAM – R/W. This bit is R/W and has no effect on the hardware.

9 Reserved. Hardwired to 0

8 Power Button SCI Enable (PWRBTN_EN) - R/W .1 = Enable PWRBTN_STS SCI generation. 0 =

Disable.

7:6 Reserved. Hardwired to 0.

5 Global Status SCI Enable (GLBH_EN) R/W. 1 = Enable SCI generation upon setting of the

GBL_STS bit in the PMSTS Register. 0 = Disable.

4:1 Reserved. Hardwired to 0.

0 Timer SCI Enable (TMROF_EN) -R/W. 1 = Enable SCI generation upon setting of the

TMROF_STS in the PMSTS Register. 0 = Disable.

4.20.1.3 PMCNTRL, Power Management Control Register: A=PWRBASE+4, R=0000

Bit Description

15:14 Reserved. Hardwired to 0.

13 Reserved - This bit will always read back as a zero. It should only be “written” to a zero. Writing a

1 into this bit will cause unpredictable behavior.

12:10 RAM bits – R/W. These bits can be read/written to any value. They have no effect on the

hardware, provided reserved bit 13 is 0.

9:3 Reserved. Hardwired to 0.

2 Global Release (GLB_RLS) - R/W. When a 1 is written to this bit position with the BIOS_EN bit

in the SMICTRL Register is set, the BIOS_STS bit in the SMICTRL Register is set and an SMI# is

generated. Writing a 0 has no effect. Reads return 0.

1 Reserved. Hardwired to 0.

0 SCI Enable (SCI_EN) - R/W. 1 = Enable the generation of SCI upon assertion of PWRBTN_STS,

GLB_STS, TMROF_STS, and WDG_STS. 0 = Disable. If this bit is clear SCI (IRQ9 as a level

generated signal) generation is disabled. Please note that to signal IRQ9 to the interrupt controller

any one of the LIRQX (LINTA-LINTD) or BIRQX (BINTA-BINTD) route control registers must be

set to map to IRQ9 and the level bit for IRQ9 must be set in bit 1 of the ELCR2 register.

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4.20.1.4 PMTMR, Power Management Timer: A=PWRBASE + 8, R=00_0000

Bit Description

23:0 Timer Value (TMR_VAL) - RO. This register returns the running count of the power management

timer. This up counter is clocked by the 3.5795Mhz clock (14.318Mhz/4). The timer is reset to 0 by

a LPCI or BPCI reset. When bit 23 (MSB) of the counter transitions from high to low or low to

high, the TMROF_STS status bit in the PMSTS Register is set and an SCI interrupt is generated if

the TMROF_EN bit is enabled in the PMEN Register.

4.20.1.5 GPSTS, General Purpose Status Register: A=PWRBASE+ C, R=0000

Bit Description

15:4 Reserved. Hardwired to 0.

3 GLBSTDBY/SMI Timer Status - R/WC. 1 = The GLBSTDBY/SMI timer has reached 0. 0 = the

GLBSTDBY/SMI timer has not reached 0. This bit is only set by hardware and is cleared by writing

a 1 to this bit position.

2 Keyboard Data Status (KEYDAT_STS) - R/WC 1 = The keyboard data line has been driven low. 0

= No keyboard data line has been driven low. This bit is only set by hardware and can only be

cleared by writing a 1 to this bit position.

1 Ring Status (RI_STS) - R/WC. 1 = A Ring indicate signal has been asserted by one of the two

internal COM ports whose ring indicate signals are ORed together. This bit is only set by hardware

and can only be cleared by writing a 1 to this bit position. Please note that if COM1 is disabled and

the DIO pin functions are instead enabled, pin DIO[29] can cause this bit to be set.

0 USB Status (USB_STS) - R/WC 1 = A USB interface has indicated that a USB resume has been

driven onto one of the two USB ports while in Power On Suspend. 0 = No USB resume has been

detected. This bit is only set by hardware and can only be cleared by writing a 1 to this bit

position.

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4.20.1.6 GPEN General Purpose Enable Register: A=PWRBASE+ E, R=0000

Bit Description

15:5 Reserved.

3 GLBSTDBY/SMI Timer Enable (GLB_TE) - R/W. 1 = Enable the setting of the resume status bit

in the PMSTS register when GLBSTDBY_STS in the GPSTS Register is set. 0 = Disable.

2:0 RAM bits – R/W. These bits can be read/written to any value and have no effect on the hardware.

4.20.2 Legacy Power Management Support Registers

4.20.2.1 PCNTRL, Processor Control Register: A=PWRBASE+10, R=00

Bit Description

7:5 Reserved. Hardwired to 0.

4 Throttle Enable (THT_EN)-R/W. 1 = Enable system throttle clock control. 0 = Disable.

3:2 Throttle Duty Programming Bits (THTL_DTY)-R/W. These bits select the duty cycle for the

STPCLK# signal when the THT_EN bit is set so the system is in the system-throttling mode. The

duty cycle indicates the percentage of time the STPCLK# signal is asserted while in throttle mode.

The duty cycle is relative to a 16 RTC clock period cycle; thus 75% duty cycle would mean that

STPCLK is asserted for 12 of the 16 RTC-clock cycle period.

Bits 3:2 Mode

00 93.75% duty cycle (processor running for 6.25%)

01 87.5% duty cycle (processor running for 12.5%)

10 75% duty cycle (processor running for 25%)

11 50% duty cycle (processor running for 50%)

1:0 Reserved. Hardwired to 0.

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4.20.2.2 GLBTIM, Global Standby Timer Register: A=PWRBASE+12, R=0000

Bit Description

15 Prescale -R/W. 1 = use a 4 Hz clock (derived from RTC clock) to clock the Global Standby Timer.

0 = use a 1024 Hz clock to clock the Global Standby Timer.

14:13 Reserved.

12:0

Global Timer Reload/Count – R/W. Writes to these bits set the 13-bit global timer reload latch and

the counter itself. Reads at this address return the value in the counter and not the reload latch

value. There is a delay of ~45uS between the writing of a value and when that value is available for

readback. The counter can be set in the range of .250 milliseconds to 2048 seconds (34.13 minutes)

using a 4 Hz clock or a range of about ~1ms to 8 seconds using a 1024 Hz clock. The timer/counter

is reset to the latch value whenever any one of the following events occur:

1) A local processor or memory access causes assertion of LDEV1 and bit 3 is enabled in the

Global Standby Timer Control Register

2) A local processor or memory access causes assertion of LDEV0 and bit 2 is enabled in the

Global Standby Timer Control Register

3) The PWRBTN# pin is asserted and the Enable Activity bit in the Global Standby Timer

Control Register is enabled

4) A software write to this register

5) Countdown of the Global Standby timer to 0.

When the timer/counter reaches zero, an SMI event is signaled (if SMI is enabled) and the timer is

stopped. The timer/counter does not count down unless the ENTIM bit is set in the Global

Standby Timer Control Register; however, writes to the Global Standby Timer continue to update

the timer/counter independent of the ENTIM bit value. Both the latch and the timer/counter are

cleared on a hardware reset. The pre-scaling down counter is also preset to all 1’s by reset or a

write to this register.

86 Subject to Change Advance Information


4.20.2.3 WTCHDG, Watchdog Timer Register: A=PWRBASE+ 14, R=0000

Bit Description

R

15 Prescale - R/W. 1 = use a 4 Hz clock (derived from RTC clock) to clock the watchdog timer. 0 = use

a 1024 Hz clock to clock the watchdog timer.

14:13 Reserved.

12:0 Watchdog Reload/Count – R/W. Writes to these bits set the 13-bit watchdog timer reload latch.

Writes to the watchdog timer latch write through the latch and into the counter as well. Reads at

this address return the value in the counter and not the reload latch value. There is a delay of

~45uS between the writing of a value and when that value is available for readback. The counter

can be set in the range of 250 milliseconds to 2048 seconds (34.13 minutes) using a 4Hz clock or a

range of about ~1ms to 8 seconds using a 1024 Hz clock. The timer/counter is reset to the latch

value whenever any one of the following events occur:

1) A local processor or memory access causes assertion of LDEV1 and bit 5 is enabled in the

Watchdog Control/Status Register

2) A local processor or memory access causes assertion of LDEV0 and bit 4 is enabled in the

Watchdog Control/Status Register

3) Assertion of the BPCI BDEVSEL# by the 82600 when bit 3 is enabled in the Watchdog

Control/Status Register

4) Assertion of the BPCI BFRAME# by the 82600 when bit 2 is enabled in the Watchdog

Control/Status Register

5) A software write to this register

6) Countdown of the watchdog timer to 0. This will also cause an interrupt or reset event

depending on the programming of the SCI Enable and Reset Enable bits of the Watchdog

Control/Status Register

The timer/counter will not count down unless the Reset Enable (RES_EN) bit or the SCI Enable

(SCI_EN) bit is set in the Watchdog Control/Status Register. Both the latch and the timer/counter

are cleared on Hardware reset. The pre-scaling counter (counts down) is also preset to all 1’s by

reset or a write to this register.

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4.20.2.4 GLBTIMCTRL, Global Standby Timer Control Register: A=PWRBASE+16,

R=00

Bit Description

7:4 Reserved

3 LDEV1 Reload Enable - R/W. 1 = An access that asserts LDEV1 will cause the Global Standby

Timer to be reloaded. 0 = Disable LDEV1 reloads.

2 LDEV0 Reload Enable - R/W. 1 = An access that asserts LDEV0 will cause the Global Standby

Timer to be reloaded. 0 = Disable LDEV0 reloads.

1 Enable Activity - R/W. 1 = PWRBTN# pin is used as an active low activity pin input that reloads

the Global Timer.

0 Enable Timer - R/W. 1 = Enable counting. 0 = Disable counting.

88 Subject to Change Advance Information


4.20.2.5 SMICTRL, SMI Status/Control Register: A=PWRBASE+18, R=0000

Bit Description

15:14 Reserved. Hardwired to 0.

13 SERIRQ Status – R/WC. 1 = a SERIRQ SMI assertion has occurred. If the corresponding

SERIRQ SMI Enable bit is set, an SMI will also be generated. This bit is only set by hardware and

can only be cleared by writing a 1 to this bit position.

12 PWRBTN Status (PWRBTN_STS) - R/WC. 1 = A PWRBTN# assertion has occurred. If the

corresponding PWNBTN_EN Enable bit is set, an SMI will also be generated. This bit is only set

by hardware and can only be cleared by writing a 1 to this bit position.

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11 GLBTIM Status (GLBTIM_STS) - R/WC. 1 = Global timer has expired. If the corresponding

GLBTIM SMI Enable bit is set, an SMI will also be generated. This bit is only set by hardware and

can only be cleared by writing a 1 to this bit position.

10 LDEV1 Status (LDEV1_STS) - R/WC. 1 = An access to local address decode 1 has occurred. If

the LDEV1_EN enable bit is set an SMI will be generated. This bit is only set by hardware and can

only be cleared by writing a 1 to this bit position.

9 LDEV0 Status (LDEV0_STS) - R/WC. 1 =An access to local address decode 0 has occurred. If

the LDEV0_EN enable bit is set an SMI will be generated. This bit is only set by hardware and can

only be cleared by writing a 1 to this bit position.

8 BIOS Status (BIOS_STS) - R/WC. 1 = GLB_RLS in the Power Management Control Register has

been set or pulsed. This is set when the GLB_RLS register bit is written to a 1. This bit is only set

by hardware and can only be cleared by writing a 1 to this bit position.

7 BIOS Release (BIOS_RLS) – R/W. When a 1 is written to this bit position, the GLB_STS bit in

the General Purpose Status Register is set and an SCI is generated if the GLBTIM_EN bit is

additionally set. Writing a 0 has no effect. Reads return 0.

6 SERIRQ SMI Enable – R/W. 1 = Signal an SMI when the SERIRQ stream drives SMI.

5 PWRBTN# Enable (PWRBTN_EN) - R/W. 1 = Assert SMI if the PWRBTN# is asserted. 0 =

Disable PWRBTN# SMI.

4 GLBTIM SMI Enable (GLBTIM_EN) - R/W. 1 = Signal an SMI when the Global timer reaches 0. 0 =

Do not signal an SMI when the global timer reaches 0.

3 LDEV1 SMI Enable (LDEV1_EN) - R/W. 1 = An access that asserts local device decode 1, LDEV1,

will cause an SMI. 0 = Disable LDEV1 SMI interrupts.

2 LDEV0 SMI Enable (LDEV0_EN) - R/W. 1 = An access that asserts local device decode 0, LDEV0,

will cause an SMI. 0 = Disable LDEV0 SMI interrupts.

1 BIOS Enable (BIOS_EN) - R/W. When set, the GLB_RLS bit in the Power Management Control

Register can be set to cause an SMI. This allows software a programmatic method of causing an

SMI.

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0 Enable SMI (SMI_EN) - R/W. 1 = Enable SMI interrupts. 0 = Disable. This is an SMI overall

enable. This bit must be set for SMI interrupts to be signaled to the processor.

4.20.2.6 DGCTRL, Watchdog Control/Status Register: A=PWRBASE+1A, R=00

Bit Description

7 Reserved.

6 Watchdog Status - R/WC. This bit is set to 1 by the hardware when watchdog timer reaches 0.

Writing a 1 clears this bit. Writing a 0 has no effect.

5 LDEV1 Relatch Enable - R/W. 1 = Watchdog timer is reloaded whenever an access causes LDEV1

(local decode 1) to be asserted. 0 = Disable LDEV1 relatching.

4 LDEV0 Relatch Enable - R/W. 1 = Watchdog timer is reloaded whenever an access causes LDEV0

(local decode 0) to be asserted. 0 = Disable LDEV0 relatching

3 BPCI Target Checking Enable - R/W. 1 = Watchdog timer is reloaded whenever the 82600 asserts

BDEVSEL#. Other targets asserting DEVSEL on the BPCI bus will not cause the timer to be

reloaded. 0 = Disable BDEVSEL# checking.

2 Backplane Checking Enable - R/W. 1 = Watchdog timer is reloaded whenever the BPCI

BFRAME# signal is asserted. 0 = Disable.

1 SCI Enable (SCI_EN) - R/W. 1 = Assert the SCI (IRQ9) interrupt when the watchdog timer expires

(reaches 0). 0 = Do not assert the SCI interrupt when the watchdog timer expires. If both the

SCI_EN and RES_EN bits are clear, the watchdog timer will not count. If both the SCI_EN and

RES_EN bits are set, the RES_EN will take precedence.

0 Reset Enable (RES_EN) - R/W. 1 = Perform warm reset if the watchdog timer expires (reaches 0).

A warm reset consists of:

1) Assertion of CPURST#

2) Assertion of the LPCI LRST#

3) Reset of the 82600 internal logic and registers

4) Assertion of the BPCI BRST# if the 82600 is configured as the BPCI Central Resource

5) Driving of the local processor power-on option bits

0 = Do not assert reset when the watchdog timer reaches 0. If both the SCI_EN and RES_EN bits

are clear, the watchdog timer will not count. If both the SCI_EN and RES_EN bits are set, the

RES_EN will take precedence.

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4.20.2.7 LDEV0, Local Device Decode 0 Register: A=PWRBASE+1C, R=0000_0000

This register defines a programmable I/O decode or memory decode region. Accesses to the internally decoded

region defined by this register can cause:

1) The watchdog timer to be reloaded if enabled by the LDEV0 Relatch Enable bit in the Watchdog Control

Status Register

2) An SMI to be asserted if enabled by the LDEV0 SMI Enable bit in the SMI Status/Control Register

3) The Global Standby Timer to be reloaded if enabled by the LDEV0 Reload Enable bit in the Global Standby

Timer Control Register

All FSB and main memory accesses are checked against these compare bits. This is independent of whether the

accesses originated from the local processor, a USB DMA, EIDE DMA, or a BPCI or LPCI memory access to the local

SDRAM.

Bit Description

31:16 Compare and Mask – R/W. These bits are each matched against the respective processor I/O or

memory address bit (A15 !xor REGBIT31, A14 !xor REGBIT30, etc. for I/O; A31 !xor REGBIT31, A30

xor REGBIT30, etc. for memory). If the IOD0 bit is set, these bits are used to match I/O addresses;

otherwise they are used to match memory addresses.

15:4 Reserved.

3 Reserved. This bit must be written to 0 to enable the proper decode function.

2 I/O Decode (IOD0) - R/W. 1 = Perform I/O decode. 0 = Perform memory decode.

1 Enable Read Decode (RDD0) - R/W. 1 = Enable read decode. 0 = Disable read decode. RDD0,

WRD0, or both must be enabled for LDEV0 functionality.

0 Enable Write Decode (WRD0) - R/W. 1 = Enable write decode. 0 = Disable write decode. RDD0,

WRD0, or both must be enabled for LDEV0 functionality.

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4.20.2.8 LDEV1, Local Device Decode 1 Register: A=PWRBASE+20, R=0000_0000

This register, like LDEV0, defines a programmable I/O decode or memory decode region. Accesses to the internally

decoded region defined by this register can cause:

1) The watchdog timer to be reloaded if enabled by the LDEV1 Relatch Enable bit in the Watchdog Control

Status Register

2) An SMI to be asserted if enabled by the LDEV1 SMI Enable bit in the SMI Status/Control Register

3) The Global Standby Timer to be reloaded if enabled by the LDEV1 Reload Enable bit in the Global Standby

Timer Control Register

All FSB and main memory accesses are checked against these compare and mask bits. This is independent of

whether the accesses originated from the local processor, a USB DMA, EIDE DMA, or a BPCI or LPCI memory

access to the local SDRAM.

Bit Description

31:16 Compare and Mask – R/W. These bits are each matched against the respective processor I/O or

memory address bit (A15 !xor REGBIT31, A14 !xor REGBIT30, etc. for I/O; A31 !xor REGBIT31, A30

xor REGBIT30, etc. for memory). If the IOD1 bit is set, these bits are used to match I/O addresses;

otherwise they are used to match memory addresses.

15:4 Reserved. Hardwired to 0.

3 Reserved. This bit must be written to 0 to enable the proper decode function.

2 I/O Decode, IOD1-R/W. 1 = Perform I/O decode. 0 = Perform memory decode.

1 Enable Read Decode (RDD1) - R/W. 1 = Enable read decode. 0 = Disable read decode. RDD1,

WRD1, or both must be enabled for LDEV1 functionality.

0 Enable Write Decode (WRD1) - R/W. 1 = Enable write decode. 0 = Disable write decode. RDD1,

WRD1, or both must be enabled for LDEV1 functionality.

4.20.3 Digital I/O Control/Data Registers

4.20.3.1 DIOO, Digital I/O Output Register: A=PWRBASE + 24, R=0000_0000

Bit Description

31:0 DIO Output Data – R/W. These 32 bits are driven out to the associated Digital I/O pin, if the

corresponding DIO direction bit has been set to “output” in the DIOD register and the pin function

has been enabled as Digital I/O. The output sense is non-inverting. For example, writing a 1 to a

particular bit will cause a LVTTL high to appear on an associated DIO pin. Reads from this register

return the value in this register, not the value of the DIO pin. These bits can be used as scratchpad

register bits if the pins associated with these bits are not configured for DIO operation. Please note

register bits DIOO[19:16] exist and can be read back, these 4 bits do not control digital outputs

since these pins can only be used as digital intputs.

92 Subject to Change Advance Information


4.20.3.2 DIOD, Digital I/O Direction Register: A=PWRBASE+28, R=0000_0000

R

The DIO direction register defines for each bit in the DIO Output Register whether or not to enable the register to the

output pin.

Bit Description

31:0 DIO Direction Data - RW. A bit is only enabled to drive the pin if the corresponding bit in this

register is a 1 and the corresponding pin is configured to be a DIO pin.

4.20.3.3 DIOI, Digital I/O Input Register: A=PWRBASE + 2C, R=0000_0000

This register reflects the state of the Digital I/O pins. This is true regardless of the state of the DIO direction register

or the configuration of the associated pin(s).

Bit Description

31:0 DIO Input Data - RO. 1 = Associated pin is at LVTTL high. 0 = Associated pin is at LVTTL low.

Advance Information Subject to Change 93


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4.20.4 SMBus Status/Control Registers

4.20.4.1 SMBus Transmit/Status/Control Register: A=PWRBASE + 30, R=0000

This register is used to control SMBus output data one byte at a time. This register and the SMBus

Input/Control/Status register can be used to implement any I 2 C or SMBus commands (e.g. Quick command, Send

byte, and Receive byte). Commands and data bytes are written into the Transfer Data field one byte at a time. A

routine to send a byte to SMBus should first check that the XMIT bit is clear. To send the data the XMIT bit must be

set. Software may poll for the XMIT bit to be clear or wait for the XMITDONE signal to be set before checking error

status and writing the next byte into this register or waiting for the receive data in the SMBus Input/Control/Status

register. Commands to this register will not be written while the XMIT bit is set, however, the transaction will

complete on the host bus, allowing software to continue execution. When the XMIT bit is clear and a command is

written to this register to set the XMIT bit the status bits XMITDONE, TIMEOUT, NEGACK, and LOSTARB will

automatically be cleared. All accesses to this register must be double byte.

Bit Description

15 XMITDONE - R/WC. This bit is set after an 8 bit SMBus transfer initiated by the 82600 has

completed. When set, this bit can cause an interrupt when IRQEN in the PWRMGT/Extended

Functions Configuration Register is set. Software may clear this bit and clear the interrupt

condition by writing a 1 to this bit or by writing a 1 to the XMIT bit in this register. The XMIT bit

must be clear before this write.

14 TIMEOUT - R/WC. This bit is set if an SMBus time-out condition occurs because SMBCLK was

held low longer than 25ms as timed by the RTC clock input. Software may clear this bit by writing a

1 to it or by writing a 1 to the XMIT bit in this register. The XMIT bit must be clear before this

write.

13 NEGACK - R/WC. This bit is set if a negative acknowledge is given to any SMB byte transaction.

Software may clear this bit by writing a 1 to it or by writing a 1 to the XMIT bit in this register. The

XMIT bit must be clear before this write.

12 LOSTARB - R/WC. This bit is set if arbitration has been lost to another master while attempting

to transmit a byte. The Start, Stop, and XMIT bits are all cleared when LOSTARB is asserted and

software is expected to reissue the SMBus output register command to retry it. Since arbitration

can continue through multiple 8-bit transfers, a retry may involve reissuing earlier 8-bit SMBus

transfers. Software may clear this bit by writing a 1 to it or by writing a 1 to the XMIT bit in this

register. The XMIT bit must be clear before this write.

11 SENDSTART - R/W. This bit is set by software for eight bit writes to the SMBus that need a Start

bit to begin the SMBus transfer. When SENDSTART and XMIT are both asserted, the LSB of this

register is “saved” in the internal state machine to indicate whether this SMBUS transaction is a

read or a write.

10 SENDSTOP - R/W. This bit is set by software for SMBus write transfers that need a STOP to be

signaled after the eight bit transfer and the acknowledge cycle has occurred. This bit only controls

STOP signaling during the write phase of an SMB transfer; however, it will send a stop for a “read”

command as well although this is not normally desired. The STOP/~ACK bit in the SMB

Input/Control/Status Register should be used for this function. To send multiple write bytes, this

bit must be kept clear (XMIT=1 with SENDSTOP=0 and a “write” [Data LSB of last SENDSTART

command] is in progress) to automatically cause the SCLK to be held low until the next data byte is

written. SENDSTOP should only be set in conjunction with the last byte to be written.

94 Subject to Change Advance Information


Bit Description

9 XMIT - R/W/HC. This bit is set to a 1 to start an SMBus 8-bit transfer. It is normally cleared by

hardware once the acknowledge has occurred and the STOP bit has been sent if enabled. When

clear, this register is available again to transfer the next SMBus eight bits of data. LOSTARB and

TIMEOUT also clear this bit. Please note that a pending SMBus read byte of data in the SMBus

data input buffer, denoted by the Data Available bit in the SMBus Input/Control/Status Register

being set, will hold-off a transmit (XMIT = 1) by clamping the SMBCLK low.

8 RAM - R/W. This is a read/write bit. This bit serves no useful function and may be used by

software as a general R/W storage bit.

7:0 Transfer Data – R/W. These eight bits are transmitted serially to the SMBus, MSB first, when the

XMIT bit is set. When SENDSTART and XMIT are also set, the LSB of this field indicates

whether this is a “read” (=1)or “write” (=0) command. This read/write indication is still transmitted

to the SMBUS in the normal fashion.

4.20.4.2 SMBus Input/Control/Status Register: A=PWRBASE+32, R=0000

All accesses to this register must be double byte.

Bit Description

15:12 Reserved. Hardwired to 0.

11 TIMEOUT - RO. This bit is read-only and is a copy of the TIMEOUT bit in the SMBus

Transmit/Status/Control Register. This bit may be cleared in that register.

10 NEGACK - RO. This bit is read-only and is a copy of the NEGACK bit in the SMBus

Transmit/Status/Control Register. This bit may be cleared in that register.

R

9 Data Available - R/WC. This status bit indicates that SMBus data is available in bits 7:0 to be

read. Until this bit is cleared by writing a 1 to this bit position, the 82600 will continue to hold the

SMBCLK line low unless the STOP/~ACK bit is set (see bit 8). By holding the SMBCLK line low,

the local host processor is given time to read the input data before the next piece of data is clocked

into the 82600 from the SMBus read target. When set this bit can cause an interrupt when IRQEN

in the PWRMGT/Extended Functions Configuration Register is set

8 STOP/~ACK - R/W. This bit, when set, signifies that the next read byte of data to be received

should be the last, indicating that a negative ACK and a STOP should be sent in response to this

read. When clear, a normal acknowledge is sent in response to the next read/receive data that is

returned to the 82600. When expecting more than one byte of data to be returned, this bit should

be loaded with the normal ACK status (bit set to 0) to be sent for the next read byte

simultaneously with the clearing of the Data Available bit signifying that the previous data has

been read. Clearing the Data Available bit will allow SMB clocking to continue for the next read.

7:0 Input Data - RO. When Data Available is set, these eight bits contain SMBus serial data from a

host read/receive/process command or from another SMBus master write command.

Advance Information Subject to Change 95


R

4.20.4.3 IRQ9SRC Status Register: A=PWRBASE+34, R=0000

This read-only register groups all internal IRQ9 sources into one read-only status register. Please note that to signal

IRQ9 to the interrupt controller any one of the LIRQX (LINTA-LINTD) or BIRQX (BINTA-BINTD) route control

registers must be set to map to IRQ9 and the level bit for IRQ9 must be set in bit 1 of the ELCR2 register.

Bit Description

15:10 Reserved. Hardwired to 0.

9 Watchdog IRQ9 - RO. This bit is high whenever both the Watchdog Status and SCI Enable bits in

the Watchdog Control/Status Register are high and the overall SCI Enable bit in the Power

Management Control Register is set. Otherwise this bit reads as a 0.

8 Power Button IRQ9 – RO. This bit is high whenever both the Power Button Status bit in the

Power Management Status Register and Power Button SCI Enable bit in the Power Management

Resume Enable Register are high and the overall SCI Enable bit in the Power Management Control

Register is set. Otherwise this bit reads as a 0.

7 Global Status IRQ9 - RO. This bit is high whenever both the Global Status bit in the Power

Management Status Register and the Global Status SCI Enable bit in the Power Management

Resume Enable Register are high and the overall SCI Enable bit in the Power Management Control

Register is set. Otherwise this bit reads as a 0.

6 Timer Overflow IRQ9 - RO. This bit is high whenever both the Timer Overflow Status bit in the

Power Management Status Register and the Timer SCI Enable bit in the Power Management

Resume Enable Register are high and the overall SCI Enable bit in the Power Management Control

Register is set. Otherwise this bit reads as a 0.

5 BIST IRQ9 - RO. This bit is high whenever both the Start BIST bit and the BIST Supported bit are

both high in the BPCI BIST configuration register.

4 SMBus IRQ9 - RO. This bit is high whenever the SMBus IRQEN bit is set in the

PWRMGT/Extended Functions Configuration Register and at least one of the following SMBus

status bits is high: XMITDONE, TIMEOUT, NEGACK, or LOSTARB in the SMBus

Transmit/Status/Control Register, or the Data Available bit in the SMBus Input/Control/Status

Register.

3 IDMA Done1 - RO. This bit is set when the incoming channel 1’s DMA In Progress status bit is

cleared. It stays set until the incoming channel 1’s IRQ9 Enable Bit is cleared.

2 IDMA Done0 - RO. This bit is set when the incoming channel 0’s DMA In Progress status bit is

cleared. It stays set until the incoming channel 0’s IRQ9 Enable Bit is cleared.

1 ODMA Done1 - RO. This bit is set when the outgoing channel 1’s DMA In Progress status bit is

cleared. It stays set until the outgoing channel 1’s IRQ9 Enable Bit is cleared.

0 ODMA Done0 – RO. This bit is set when the outgoing channel 0’s DMA In Progress status bit is

cleared. It stays set until the outgoing channel 0’s IRQ9 Enable Bit is cleared.

96 Subject to Change Advance Information


4.20.4.4 PCI Interrupt Status Register: A=PWRBASE+36, R=Pin Levels

This read-only register groups all external LPCI/BPCI interrupt sources into one read-only status register.

Bit Description

7 BPCI INTD - RO. This is a read-only copy of the signal level present on the BPIRQD# pin.

6 BPCI INTC - RO. This is a read-only copy of the signal level present on the BPIRQC# pin.

5 BPCI INTB - RO. This is a read-only copy of the signal level present on the BPIRQB# pin.

4 BPCI INTA - RO. This is a read-only copy of the signal level present on the BPIRQA# pin.

3 LPCI INTD - RO. This is a read-only copy of the signal level present on the LPIRQD# pin.

2 LPCI INTC - RO. This is a read-only copy of the signal level present on the LPIRQC# pin.

1 LPCI INTB - RO. This is a read-only copy of the signal level present on the LPIRQB# pin.

0 LPCI INTA - RO. This is a read-only copy of the signal level present on the LPIRQA# pin.

4.20.5 BPCI/SDRAM DMA Control Registers

There are four sets of identical DMA channel control registers:

R

4.20.5.1 ODMACS0 - Outgoing DMA Control/Status 0: A=PWRBASE+38, R=0000

4.20.5.2 ODMACS1 - Outgoing DMA Control/Status 1: A=PWRBASE+3A, R=0000

4.20.5.3 IDMACS0 - Incoming DMA Control/Status 0: A=PWRBASE+3C, R=0000

4.20.5.4 IDMACS1 - Incoming DMA Control/Status 1: A=PWRBASE+3E, R=0000

These registers are defined as follows:

Bit Description

15:12 Reserved. Hardwired to 0.

11 DMA In Progress - RO.

This status bit indicates that a DMA transfer is in progress. When in DMA chaining mode, this bit

is cleared when the next descriptor address is zero. If DMA chaining is not being used, this bit is

cleared after the last byte is transferred. In either mode this bit is cleared when a hardware error

occurs (host abort, master abort, or target abort).

1 = DMA is in progress.

0 = DMA complete.

Advance Information Subject to Change 97


R

Bit Description

10 Host Abort Status - R/WC. 1 = Received Host abort status. This bit is set by hardware when the

DMA Host Address or the Next Descriptor Address does not “hit” local SDRAM. Writing a 1 to

this position will clear the status bit. Writing a 0 has no effect

9 Master Abort Status - R/WC. 1 = The DMA received Master abort status from the BPCI interface.

Writing a 1 to this position will clear the status bit. Writing a 0 has no effect

8 Target Abort Status - R/WC. 1 = The DMA received Target abort status from the BPCI interface.

Writing a 1 to this position will clear the status bit. Writing a 0 has no effect

7 Reserved. Hardwired to 0.

6 DMA Start - R/W.

This bit is read/write from the local host. Writing a 1 to this bit position causes a DMA transaction

to start unless the Transfer Length is 0, the host address is over the top of SDRAM or the next

descriptor address is zero and chaining mode is set. For the latter three cases, the DMA In

Progress status bit is not set and cleared so a DMA Done interrupt will not be issues if enabled.

Writing a 0 to this bit position will stop the DMA transaction in progress at the next 32 byte

boundary. In this case the DMA Transfer Length register may be read to see if the DMA did not

complete as indicated by a non-zero value.

The value in this bit reflects the last value written. It is not changed by the DMA controller.

5 DMA Interrupt Enable – R/W.

1 = Assert IRQ9 (level mode) when the DMA In Progress bit transitions from a 1 to a 0. Please note

that to signal IRQ9 to the interrupt controller any one of the LIRQX (LINTA-LINTD) or BIRQX

(BINTA-BINTD) route control registers must be set to map to IRQ9 and the level bit for IRQ9 must

be set in bit 1 of the ELCR2 register.

0 = Disable IRQ9 generation from this DMA channel.

4 DMA Chaining – R/W. If set to 1 and DMA Start is set to 1, the Next Descriptor Address Register

is used to fetch the first DMA transaction to execute. When 0, the BPCI Address, Host Address,

and Transfer Length Registers must be preloaded by host software before setting the DMA start

bit to 1 and these registers are used to directly perform one non-chained DMA operation. While

this bit is 1 and the DMA In Progress status bit is set, local host initiated writes to the BPCI

Address, Host Address, and Transfer Length address registers do not update these registers.

Changing the DMA chaining bit while a DMA is in progress results in undefined behavior.

98 Subject to Change Advance Information


Bit Description

3:2 Pacing Timer - R/W. This 2-bit field is used to pace the rate of the DMA in progress. The field

indicates the number of 8 BPCI clock quantas that must expire between receiving/sending the last

BPCI word from the previous burst until initiating the next BPCI burst transaction. For maximum

DMA performance this field should be set to 0. Setting this field to a non-zero value frees up bus

bandwidth for other BPCI transactions. This field does not affect the DMA descriptor fetching.

These are fetched from host memory immediately after the current DMA chain descriptor has

completed execution.

Pacing Timer Value BPCI Clocks

00 0

01 8

10 16

11 24

1 BPCI Memory Read Control - R/W. 1 = Use a Memory Read Multiple BPCI command for all but

the last DMA transaction. The last DMA transaction will use a Memory Read. 0 = Always use a

Memory Read command for all DMA transactions. This bit has no meaning for the outgoing

channels.

0 Reserved. Hardwired to 0.

4.20.5.5 ODMAPA0, Outgoing DMA BPCI Address Register 0:

A=PWRBASE+40, R=0000_0000

4.20.5.6 ODMAPA1, Outgoing DMA BPCI Address Register 1:

A=PWRBASE+50, R=0000_0000

4.20.5.7 IDMAPA0, Incoming DMA BPCI Address Register 0:

A=PWRBASE+60, R=0000_0000

4.20.5.8 IDMAPA1, Incoming DMA BPCI Address Register 1:

A=PWRBASE+70, R=0000_0000

There are four sets of identical DMA PCI Address Registers. These registers are defined as follows:

Bit Description

31:0 BPCI Address - R/W. These bits are loaded with the starting BPCI address and are incremented in

the BCLK domain to the next address as each DMA read/write transaction completes. While the

DMA chaining bit is set and the DMA In Progress status bit is set, host initiated writes to this

register have no effect. If the DMA chaining bit is clear, writing to this register while a DMA is

already in progress results in undefined behavior.

R

Advance Information Subject to Change 99


R

4.20.5.9 ODMAHA0, Outgoing DMA Host Address Register 0:

A=PWRBASE+44, R=0000_0000

4.20.5.10 ODMAHA1, Outgoing DMA Host Address Register 1:

A=PWRBASE+54, R=0000_0000

4.20.5.11 IDMAHA0, Incoming DMA Host Address Register 0:

A=PWRBASE+64, R=0000_0000

4.20.5.12 IDMAHA1, Incoming DMA Host Address Register 1:

A=PWRBASE+74, R=0000_0000

There are four sets of identical DMA Host Address Registers. These registers are defined as follows:

Bit Description

31:0 Host Address - R/W. These bits are loaded with a starting local host physical address and are

incremented in the HCLK domain to the next address as each SDRAM DMA read/write transaction

is completed. If the physical address written to this register does not hit the SDRAM memory

region in the host address space or if the address increment passes the top of SDRAM, the DMA

will abort. While the DMA chaining bit is set and the DMA In Progress status bit is set, host

initiated writes to this register have no effect. If the DMA chaining bit is clear, writing to this

register while a DMA is already in progress results in undefined behavior.

100 Subject to Change Advance Information


4.20.5.13 ODMATL0, Outgoing DMA Transfer Length Register 0:

A=PWRBASE+48, R=0000_0000

4.20.5.14 ODMATL1, Outgoing DMA Transfer Length Register 1:

A=PWRBASE+58, R=0000_0000

4.20.5.15 IDMATL0, Incoming DMA Transfer Length Register 0:

A=PWRBASE+68, R=0000_0000

4.20.5.16 IDMATL1, Incoming DMA Transfer Length Register 1:

A=PWRBASE+78, R=0000_0000

There are four sets of identical DMA Transfer Length Registers. These registers are defined as follows:

Bit Description

31:24 Reserved. Hardwired to 0.

R

23:0 Transfer Length - R/W. These bits define the number of bytes to be transferred. During the DMA

transfer, this register is continually decremented in the HCLK domain by the number of DMA

bytes read from the source. There are typically 32 bytes of data from the Host or BPCI bus. When

this register is 0, the DMA In Progress status bit is cleared after any pending DMA writes are

completed. If this register is 0, a DMA will not start even if a 1 is written into STARTDMA bit of

the DMA Status/Control register. The maximum number of bytes that may be transferred in one

DMA transaction is FF_FFFFH bytes (16MB - 1). While the DMA chaining bit is set and the DMA

In Progress status bit is set, host initiated writes to this register have no effect. If the DMA

chaining bit is clear, writing to this register while a DMA is already in progress results in undefined

behavior.

Advance Information Subject to Change 101


R

4.20.5.17 ODMANDA0, Outgoing DMA Next Descriptor Address Register 0:

A=PWRBASE+4C, R=0000_0000

4.20.5.18 ODMANDA1, Outgoing DMA Next Descriptor Address Register 1:

A=PWRBASE+5C, R=0000_0000

4.20.5.19 IDMANDA0, Incoming DMA Next Descriptor Address Register 0:

A=PWRBASE+6C, R=0000_0000

4.20.5.20 IDMANDA1, Incoming DMA Next Descriptor Address Register 1:

A=PWRBASE+7C, R=0000_0000

There are four sets of identical DMA Next Descriptor Address Registers. These registers are defined as follows:

Bit Description

31:3 Next Descriptor Address - R/W. This is a 32 bit physical host address with bits 2:0 hardwired to 0

that points to the next DMA descriptor in the DMA “chain” list. A value of 0 in this register is

interpreted as the end of the DMA descriptor list. This register is ignored if the DMA chaining bit

is clear. While the DMA chaining bit is set and the DMA In Progress status bit is set, host initiated

writes to this register have no effect.

2:0 Reserved. Hardwired to 0

4.20.6 Virtual PCI to PCI (P2P) Bridge Configuration Registers.

These registers are used to configure the local host address mapping to the BPCI bus. Addresses that are not

claimed by the internal SDRAM controller or internal peripherals are checked against the base and limit registers

within P2P register space to determine whether they should be sequenced to the BPCI bus with positive decode or to

the LPCI bus with subtractive decode.

These registers can be accessed by the local host using two different methods:

1) In BPCI Central Resource mode, these registers are “virtually” located as bus #0, device #1 on the LPCI bus.

Legacy software will be able to see these registers as standard PCI to PCI bridge registers that are virtually

located (device #1) on the LPCI bus..

2) In either Central Resource mode or Peripheral Bridge mode, these registers may be accessed as registers at

bus #0, device #0, function #0 when using the Alternate Configuration Address and Data Registers located

at I/O addresses 0x1CF8 and 0x1CFC.

An 82600 configured as a BPCI Peripheral Bridge can only use the second mechanism to access these registers. In

this mode, the virtual PCI-to-PCI bridge configuration registers do not appear to be virtually located on the LPCI bus.

In addition, other PCI masters cannot access these P2P configuration registers, even if the BPCI interface is

configured as a Peripheral Bridge.

Note that several of the P2P Primary Command and Status bits have no utility in the 82600 environment since the

primary-side interface is the local processor host bus and not a PCI bus.

Addressing of these registers is denoted as A = ,.

102 Subject to Change Advance Information


Address

Offset

Register

Symbol

PCI to PCI Bridge Configuration Registers

Table 8: Virtual PCI to PCI Bridge Configuration Registers

Register Name Access:

00-01 VID Vendor Identification RO

02-03 DID Device Identification RO

RO = Read-Only

R/W = Read/Write

04-05 PCICMD PCI Command Register See register

06-07 PCISTS PCI Status Register RO & R/WC

08 RID Revision Identification R/W,

09-0B CLASSC Class Code Register R/W

0C CLS Cache Line Size Register RO

0D MLT Master Latency Timer R/W

0E HT Header Type RO

18 PBN Primary Bus Number R/W

19 SBN Secondary Bus Number R/W

1A SUBN Subordinate Bus Number R/W

1B SLT Secondary Latency Timer (see BPCI

CSH’s MLT register)

R/WC = Read/Write Clear

R

Advance Information Subject to Change 103

R/W

1C-1D IOBL I/O Base and Limit R/W

1E SSTS Secondary Status (see BPCI CSH’s STS

register)

R/WC

20-23 MBL0 Memory Base and Limit0 R/W

24-27 MBL1 Memory Base and Limit1 R/W

28-2B MUB Memory Upper 32-bits Base RO

2C-2F MUL Memory Upper 32-bits Limit RO

30-33 IOUBL I/O Base and Limit upper 16 bits RO


R

Address

Offset

Register

Symbol

Register Name Access:

3C-3D ILIP Interrupt Line/Interrupt Pin Register RO

3E-3F BCR Bridge Control Register R/W

40 HBPCIR Host to BPCI Address Remap register R/W

60-63 BIRQRC[A:D] BIRQx Route Control Register R/W

70 BMTT BPCI Multi-Transaction Timer Register R/W

RO = Read-Only

R/W = Read/Write

4.20.6.1 VID, Vendor Identification Register: A=0, 1.0.0, R=1331

Bit Description

R/WC = Read/Write Clear

15:0 Vendor Identification Register. This is hardwired to the RadiSys vendor ID: 1331. This value is

read-only.

4.20.6.2 DID, Device Identification Register: A=2, 1.0.2, R=8210

Bit Description

15:0 Device Identification Register. The 82600 ID is 8210. This value is read-only.

104 Subject to Change Advance Information


4.20.6.3 PCICMD, PCI Command Register: A=4, 1.0.4, R=0000

Bit Description

15:10 Reserved. Hardwired to 0.

9 Fast Back-to-Back. Hardwired to 0. As a master, the 82600 will not initiate fast back to back

accesses

8 SERR# Enable. Hardwired to a 0. SERR# is never driven by the 82600.

7 Address and Data Stepping Enable. Hardwired to 0

6 Parity Error Enable. Hardwired to 0. The 82600 never reports address and parity errors.

5 Video Pallet Snooping. Hardwired to 0

4 Memory Write and Invalidate Enable. Hardwired to 0

3 Special Cycle Enable. Hardwired to 0. The 82600 captures all host generated special cycles

internally and ignores PCI generated special cycles

2 Bus Master Enable - R/W. Both this bit and the Bus Master Enable bit in the BPCI Command

Register must be set to allow the 82600 to generate memory, I/O or configuration accesses to the

BPCI bus.

R

1 Memory Access Enable (MAEP2P) - R/W. When MAEP2P = 1 and the Bus Master Enable bit in

both the BPCI Command Register and this register are also 1, local host initiated memory accesses

that fall between the addresses defined in both the Memory Base and Limit Registers will be routed

to the BPCI bus. When MAEP2P = 0 or the Bus Master Enable bit in the BPCI Command Register =

0 or the Bus Master Enable bit in this register = 0, all memory accesses are serviced either by the

SDRAM or LPCI bus.

0 I/O Access Enable (IOEP2P) - R/W. When IOEP2P = 1 and the Bus Master Enable bit in both the

BPCI Command Register and this register are also 1, the 82600 positively decodes host initiated I/O

access addresses that fall between the addresses defined in the I/O Base and Limit Register and

sequences the accesses that fall between the base and limit to the BPCI bus. When IOEP2P = 0 or

the Bus Master Enable bit in the BPCI Command Register = 0 or the Bus Master Enable bit in this

register = 0, all I/O accesses are serviced only by internal peripherals or the LPCI bus.

Advance Information Subject to Change 105


R

4.20.6.4 PCISTS, PCI Status Register: A=6, 1.0.6, R=0000

This register is read-only. Since the primary bus is the processor local bus, not a PCI bus, these bits are all

hardwired.

Bit Description

15 Detected Parity Error. Hardwired to a 0.

14 Signaled SERR# Status. Hardwired to a 0.

13 Received Master Abort Status. Hardwired to 0.

12 Received Target Abort Status. Hardwired to 0

11 Signaled Target Abort Status. Hardwired to a 0

10:9 DEVSEL# Timing. Hardwired to 00 (fast timing).

8 PERR# Response. Hardwired to a 0

7 Target Fast Back to Back. This bit is hardwired to 0.

6:0 Reserved. Hardwired to 0.

4.20.6.5 RID, Revision Identification Register: A=08, 1.0.8, R=00

Bit Description

7:0 Revision Identification Register. The 82600 RID is 00. This value is read-only

4.20.6.6 CLASSC, Class Code Register: A=09, 1.0.9, R=06_0400

Bit Description

23:16 Base Class Code. This is hardwired to 06 (Bridge device).

15:8 Sub Class Code. This is hardwired to 04 (PCI to PCI bridge device).

7:0 Programming Interface. This is hardwired to 00 (standard PCI to PCI bridge programming

interface).

4.20.6.7 CLS, Cache Line Size Register: A=0C, 1.0.C, R=08

Bit Description

7:0 Cache Line Size Register - RO. This register is read-only and indicates the number of 32-bit

words that are included in a single cache line. Since the 82600 supports a 32 byte line, the value in

this register is hardwired to 08.

106 Subject to Change Advance Information


4.20.6.8 MLT, Master Latency Timer: A=0D, 1.0.D, R=00

Bit Description

7:3 Master Latency Timer Count Value - R/W. These bits are read/write, but have no effect on the

hardware since the primary interface is the local processor host bus, not a PCI bus.

2:0 Reserved. Hardwired to 0.

4.20.6.9 HT, Header Type: A=0E, 1.0.E, R=01

Bit Description

7:0 Header Type - RO. This is hardwired to 01: the configuration space conforms to a PCI to PCI

configuration register space.

4.20.6.10 PBN, Primary Bus Number: A=18,1.0.18, R=00

Bit Description

7:0 Primary Bus Number - R/W. This register may be read/written as a scratchpad register. It has no

effect on the hardware.

4.20.6.11 SBN, Secondary Bus Number: A=19,1.0.19, R=00

Bit Description

R

7:0 Secondary Bus Number (SBN) - R/W. These bits are set to the BPCI bus number. This register, in

conjunction with the Subordinate Bus Number Register, is used to determine which PCI

configuration cycles must be sequenced to the BPCI bus. In Central Resource mode, a type 0

configuration cycle will occur on the BPCI bus when a standard PCI configuration data cycle is

initiated from the local host and the secondary bus number is matched by the bus number in the

standard PCI Configuration Address Register. A type 0 cycle occurs on the BPCI bus independent

of this register using the Alternate Configuration Data Register when the Bus Number is 0 in the

Alternate Configuration Address Register. This register has no effect on standard PCI

configuration cycles when the 82600 is in Peripheral Bridge mode.

Advance Information Subject to Change 107


R

4.20.6.12 SUBN, Subordinate Bus Number: A=1A,1.0.1A, R=00

Bit Description

7:0 Subordinate Bus Number (SUBN) - R/W. These bits support a second or higher level PCI to PCI

bridge on the BPCI bus. This register, in conjunction with the Secondary Bus Number, is used to

determine which PCI configuration cycles must be sequenced to the BPCI bus. When in Central

Resource mode and the Bus Number in the standard PCI Configuration Address Register is less

than or equal to SUBN and greater than the SBN, then a type 1 configuration cycle will occur on

the BPCI bus when a standard PCI configuration data access is initiated from the local host. When

using the Alternate configuration data/address registers, a type 1 configuration cycle is initiated

whenever the Alternate configuration address register contains a non-zero bus number. This

register has no effect on standard PCI configuration cycles when the 82600 is in Peripheral Bridge

mode.

4.20.6.13 SLT, Secondary Latency Timer: A=1B,1.0.1B, R=00

Bit Description

7:3 Secondary Latency Timer - R/W. These bits are physically the same bits as the BMLT Master

Latency Timer at 0D, 1.0.8D and may be read/written using either address. The value placed in

these bits, with the 3 LSBs always = 0, forms an 8-bit count value that defines the guaranteed time

slice, measured in BPCI clocks, given to the 82600 before it must surrender mastership of the BPCI

bus if other BPCI agents are requesting access to the bus.

2:0 Reserved. Hardwired to 0.

4.20.6.14 IOBL, I/O Base and Limit Register: A=1C,1.0.1C, R=0000

Bit Description

15:12 IO Limit - R/W. These 4 bits form the I/O address upper bound and are used to match against the

upper 4 bits of a local host initiated 16-bit I/O address. All local host initiated I/O accesses whose

addresses fall between the IO Base and Limit registers, inclusive, are sequenced to the BPCI bus

11:8 I/O Type. Hardwired to 0 (16-bit I/O address).

7:4 IO Base-R/W. These 4 bits form the I/O address lower bound. These bits are compared against

the upper 4 bits of a local host initiated 16-bit I/O address. All local host initiated I/O accesses

whose addresses fall between the IO Base and Limit registers, inclusive, are sequenced to the BPCI

bus.

3:0 I/O Type. Hardwired to 0 (16-bit I/O address).

108 Subject to Change Advance Information


4.20.6.15 SSTS, Secondary Status Register: A=1E, 1.0.1E, R=0230

This register is physically the same register as the BPCI Status Register and can be accessed with a BPCI

configuration cycle when the 82600 is configured as a Peripheral Bridge on the BPCI bus.

Bit Description

15 Detected Parity Error. Hardwired to a 0.

14 Signaled SERR# Status - R/WC. When the 82600 asserts the BSERR# signal, this bit is set to 1.

Writing a 1 to this bit position clears this bit. Writing a 0 has no effect on this bit.

13 Received Master Abort Status - R/WC. When the 82600 generates a BPCI master-abort, this

status bit is set. Writing a 1 to this bit position clears this bit. Writing a 0 has no effect on this

status bit.

12 Received Target Abort Status - R/WC. When the 82600 initiates a BPCI bus transaction and

receives a target abort, this bit is set. Writing a 1 to this bit position clears this bit. Writing a 0 has

no effect on this status bit.

11 Signaled Target Abort Status. Hardwired to a 0

10:9 DEVSEL# Timing. Hardwired to 01 (medium timing).

8 PERR# Response. Hardwired to a 0

7 Target Fast Back to Back. This bit is hardwired to 0. The 82600, as a target on the BPCI bus,

cannot respond to fast back to back accesses.

6 Reserved. Hardwired to 0.

5 66Mhz Capable. Hardwired to 1.

4 ECP Support. Hardwired to 1 to indicate support for Enhanced Capabilities (Hot swap friendly).

3:0 Reserved. Hardwired to 0.

R

Advance Information Subject to Change 109


R

4.20.6.16 MBL0, Memory Base and Limit Register 0: A=20,1.0.20, R=0000_0000

Bit Description

31:20 Memory Limit - R/W. These 12 bits form the local host’s memory address upper bound and are

used to match against the upper 12 bits of a local host initiated 32-bit memory address. Both the

base and limit registers must be set to a region that does not conflict with the local SDRAM

address map. Local accesses are first compared to the local SDRAM address comparitor. All local

host initiated memory accesses whose addresses fall between the Memory Base and Limit

registers, inclusive, and that are not sequenced to the SDRAM bus are sequenced to the BPCI bus

19:16 Reserved Hardwired to 0.

15:4 Memory Base - R/W. These 12 bits form the local host’s memory address lower bound. These bits

are compared against the upper 12 bits of a local host initiated 32-bit memory address. All local

host initiated memory accesses whose addresses fall between the Memory Base and Limit

registers, inclusive, and that are not sequenced to the SDRAM bus are sequenced to the BPCI bus.

3:0 Reserved. Hardwired to 0.

4.20.6.17 MBL1, Memory Base and Limit Register 1: A=24,1.0.24, R=0000_0000

These registers correspond to a PCI to PCI prefetchable region. The local host processor may be configured to

support this region as a prefetchable, write-combining memory space; however, the 82600 will treat accesses to this

region in the same manner as accesses that match the MBL0 address range.

Bit Description

31:20 Memory Limit - R/W. Both the base and limit registers must be set to a region that does not

conflict with the local SDRAM address map. Local accesses are first compared to the local

SDRAM address comparitor. All local host initiated memory accesses whose addresses fall

between the Memory Base and Limit registers, inclusive, and that are not sequenced to the

SDRAM are sequenced to the BPCI bus.

19:16 Reserved Hardwired to 0.

15:4 Memory Base - R/W. These 12 bits form the local host’s memory address lower bound. These bits

are compared against the upper 12 bits of a local host initiated 32-bit memory address. All local

host initiated memory accesses whose addresses fall between the Memory Base and Limit

registers, inclusive, and that are not sequenced to the SDRAM bus are sequenced to the BPCI bus.

3:0 Reserved. Hardwired to 0.

4.20.6.18 MUB, Memory Upper Base: A=28,1.0.28, R=0000_0000

This register is hardwired to 0 and is always read back as 0. 64-bit PCI addresses are not supported.

Bit Description

31:0 Memory Upper Base – RO. Hardwired to 0.

110 Subject to Change Advance Information


4.20.6.19 MUL, Memory Upper Limit Register: A=2C,1.0.2C, R=0000_0000

This register is hardwired to 0 and is always read back as 0. 64-bit PCI addresses are not supported.

Bit Description

31:0 Memory Upper Limit – RO. Hardwired to 0.

4.20.6.20 IOUBL, I/O Upper Base and Limit Register: A=30,1.0.30, R=0000_0000

This register is hardwired to 0 and is always read back as 0. 32 bit I/O addresses are not supported.

Bit Description

31:0 I/O Upper Base and Limit Register – RO. Hardwired to 0.

4.20.6.21 ILIP, Interrupt Line/Pin Register: A=3C,1.0.3C, R=0000

R

This register is hardwired to 0 and is always read back as 0. The BCSH ILIP Register implements the interrupt line/pin

function when the 82600 is configured as a Peripheral Bridge on the BPCI bus.

Bit Description

15:0 Interrupt Line/Pin Register – RO. Hardwired to 0.

4.20.6.22 Bridge Control Register: A=3E,1.0.3E, R=0000

Bit Description

15:7 Reserved. Hardwired to 0

6 Secondary Bus Reset – R/W. This bit only affects operation when the 82600 is configured as the

Central Resource of the BPCI bus. When configured in this manner, writing a 1 to this bit will

cause the 82600 to assert reset on the BPCI bus. Writing a 0 to this bit will negate BRST# provided

LRST# is also negated. This bit has no effect when the 82600 is configured as a Peripheral Bridge

on the BPCI bus.

5:2 Reserved. Hardwired to 0. .

1 BSERRNMI – R/W. 1 = A BSERR# assertion will cause an NMI if the Enable Parity NMI in the

PortB Register is set to 0 and the Disable NMI bit of the RTC Register is clear. 0 = Disable NMI

assertion from BSERR#.

0 Reserved. Hardwired to 0

Advance Information Subject to Change 111


R

4.20.6.23 HBPCIR, Host to BPCI Remap Register: A=40,1.0.40, R=E4

This register may be used to access regions of the BPCI address space that would not normally be accessible from

the local host processor. For example, when the 82600 is configured as a Peripheral Bridge, the local host processor

would not be able to access BPCI low memory because its own local main memory resides in this space. This register

divides the host address space into four equal 1GB regions. For each 1GB region, this register determines the upper

two address bits that are sent to the BPCI interface for host memory accesses that are mapped to the BPCI bus. This

register has no effect on the host accesses not bound for the BPCI bus (i.e., addresses that don’t fall between the

P2P Memory Base and Limit Registers).

Bit Description

7:6 Region 3 Address Remap Bits – R/W. For host accesses from 0xC000_0000 to 0xFFFF_FFFF

(excluding regions mapped to ISA, a LPCI peripheral or SDRAM resident flash), these two bits

replace A31 (bit 7) and A30 (bit 6) for accesses bound to the BPCI interface. These bits initialize to

0b11 (pass through mode).

5:4 Region 2 Address Remap Bits – R/W. For host accesses from 0x8000_0000 to 0xBFFF_FFFF

(excluding any region mapped to ISA or an LPCI peripheral), these two bits replace A31 (bit 5) and

A30 (bit 4) for accesses bound to the BPCI interface. These bits initialize to 0b10 (pass through

mode).

3:2 Region 1 Address Remap Bits – R/W. For host accesses from 0x4000_0000 to 0x7FFF_FFFF

(excluding any region mapped to ISA, main memory or an LPCI peripheral), these two bits replace

A31 (bit 3) and A30 (bit 2) for accesses bound to the BPCI interface. These bits initialize to 0b01

(pass through mode)

1:0 Region 0 Address Remap Bits – R/W. For host accesses from 0x0010_0000 to 0x3FFF_FFFF

(excluding any region mapped to ISA, main memory or an LPCI peripheral), these two bits replace

A31 (bit 1) and A30 (bit 0) for accesses bound to the BPCI interface. These bits initialize to 0b00

(pass through mode)

4.20.6.24 BIRQRC[A:D], BPIRQx Route Control Registers: A=60-63, 1.0.60-1.0.63, R=80

These registers define the BPCI interrupt pin routing to the internal IRQ lines supported by the internal 8259s.

Register 60 defines the routing for BPIRQA#, 61 defines the routing for BPIRQB#, etc. All four registers can be

routed to the same interrupt where they are ORed together. In addition, they are ORed with the LPCI IRQ lines, if they

are routed to the same interrupt. All interrupts that are “routed-to” using these registers must be set to level sensitive

in the ELCR1 and ELCR2 Edge/Level Control Registers.

Bit Description

7 Interrupt Routing Enable – R/W. 0 = Enable, 1 = Disable.

6:4 Reserved. Hardwired to 0.

3:0 Interrupt Routing – R/W. When bit 7 = 0, these bits select the routing of the BPIRQx to one of the

8259 interrupt inputs. The four bits encode the IRQx input as 4-bit binary number (e.g. a 1111

entry means that the BPCI interrupt will be routed to IRQ15). 0,1,2,8,13 and 14 encodings are

reserved and should not be used.

112 Subject to Change Advance Information


4.20.6.25 BMTT, Backplane Multi-Transaction Timer Register: A=70, 1.0.70, R=20

Bit Description

7:2 BMTT Count Value. The value programmed here represents the guaranteed time slice in BPCLKs

allotted to the current agent. Once expire, the 82600 will grant the bus as soon as another BPCI

agent requests the bus. The count value is always set to a multiple of 4 since bits 1 and 0 are

always 0.

1:0 Reserved. Hardwired to 0.

4.21 Backplane PCI Configuration Registers - Backplane View

R

These registers also appear at 0x80+offset within the host view’s PCI to PCI configuration space registers to allow

access to these registers when the 82600 is configured as the Central Resource. In Central Resource mode BPCI

IDSEL access is not available. Some of these registers are shared between configuration spaces (e.g. the master

latency timer is implemented as one set of bits that may be accessed as either the P2P’s secondary latency timer or as

the BPCI CSH master latency timer). The 82600 does not support burst PCI configuration cycles from the BPCI bus

and will assert STOP# to terminate burst PCI configuration accesses after asserting a single TRDY# signifying

disconnect without data.

BPCI Address

Offset/P2P

Offset

Register

Symbol

Table 9: BPCI Configuration Registers – Backplane View

Register Name Access:

L = Local host

(at address 0x80 +

offset)

P = BPCI

RO = Read-Only

R/W = Read/Write

R/WC = Read/Write

Clear

82600/ Backplane PCI Bridge Registers (also accessible in Central Resource mode at 0.1.0.80 +

offset)

00-01/80-81 BVID Vendor Identification L-R/W; P-RO

02-03/82-83 BDID Device Identification L-R/W, P-RO

04-05/84-85 BPCICMD BPCI Command Register See register

06-07/86-87 BPCISTS BPCI Status Register L/P-RO & R/WC

08/88 BRID Revision Identification L-R/W, P-RO

09-0B/89-8B BCLASSC Class Code Register L-R/W, P-RO

0C/8C BCLS Cache Line Size Register L/P – RO

0D/8D BMLT Master Latency Timer L/P – R/W

Advance Information Subject to Change 113


R

BPCI Address

Offset/P2P

Offset

Register

Symbol

Register Name Access:

L = Local host

(at address 0x80 +

offset)

P = BPCI

RO = Read-Only

0E/8E BHT Header Type L/P – RO

0F/8F BBIST Built-In-Self-Test Register L/P- R/W

R/W = Read/Write

R/WC = Read/Write

Clear

10-13/90-93 BAR0 Base Address Register 0 L/P – R/W

14-17/94-97 BAR1 Base Address Register 1 L/P – R/W

2C-2D/AC-AD BSUBVID Subvendor Identification L-R/W , P-RO

2E-2F/AE-AF BSUBDID Subvendor Device Identification L-R/W , P-RO

30-33/B0-B3 RBAR ROM Base Address Register L/P-R/W

34/B4 CPR Capabilities Pointer Register L/P RO

3C-3D/BC-BD ILIP Interrupt Line/Interrupt Pin Register L/P- R/W

3E-3F/BE-BF PGNTLAT BPCI Arbitration Grant/Latency Register L – R/W, P - RO

40-43/C0-C3 MRBAR0 Memory Remap Base Address Register 0 L/P-R/W

44-47/C4-C7 MRBAR1 Memory Remap Base Address Register 1 L/P-R/W

48-4B/C8-CB RRBAR ROM Remap Base Address Register L/P-R/W

4C/CC MBPC Miscellaneous BPCI Control L – R/W, P-RO

50-53/D0-D3 HSC Hot Swap Capability L/P – R/W & WC

60-63/E0-E3 LPID Local to PCI bus Interrupt Doorbell

Register

64-67/E4-E7 PLID PCI to local bus Interrupt Doorbell

Register

7C-7F/FC-FF BAAR Backplane Abort Address Register L/P RO

L-R/W, P-R/WC

L-R/WC,P-R/W

114 Subject to Change Advance Information


4.21.1 BVID, Vendor Identification Register: A=0, 1.0.80, R=1331

Bit Description

15:0 Vendor Identification Register – R/W. This is initialized to the RadiSys vendor ID: 1331. This

value may be overwritten from the host interface side. This value is read-only from the BPCI

interface.

4.21.2 BDID, Device Identification Register: A=2, 1.0.82, R=8210

Bit Description

15:0 Device Identification Register – R/W. The 82600 ID defaults to 8210. This value may be

overwritten from the host interface side. This value is read-only from the BPCI interface.

R

Advance Information Subject to Change 115


R

4.21.3 BPCICMD, BPCI Command Register: A=4, 1.0.84, R=0000

Bit Description

15:10 Reserved. Hardwired to 0.

9 Fast Back-to-Back. Hardwired to 0. As a master, the 82600 will not initiate fast back to back

accesses

8 SERR# Enable – R/W. 1 = Enable, 0 = Disable. When enabled, a multi-bit memory error will cause

the 82600 to assert SERR#.

7 Address and Data Stepping Enable. Hardwired to 0

6 Parity Error Enable Hardwired to 0

5 Video Pallet Snooping. Hardwired to 0

4 Memory Write and Invalidate Enable. Hardwired to 0

3 Special Cycle Enable. Hardwired to 0. The 82600 captures all host generated special cycles

internally and ignores BPCI generated special cycles

2 Bus Master Enable – R/W. This bit initializes to 0 and should be set by the Central Resource to

allow the 82600 to generate BPCI transactions. When the 82600 is configured as the Central

Resource, then the BIOS or monitor software must first set this bit using BPCI configuration cycles

that are intercepted internally. Both this bit and the Bus Master Enable bit in the PCI Command

Register must be set to allow the 82600 to generate memory, I/O or configuration accesses to the

BPCI bus.

1 Memory Access Enable (MAEB) – R/W. When MAEB = 1, the BPCI bus can access the 82600

SDRAM. The BAR0 and BAR1 registers define the specific memory regions accessible by the BPCI

bus. Enabling this bit enables both the BAR0 and BAR1 registers so both must be properly

programmed before this bit is set. If only a single region of 82600 SDRAM is to be accessible by the

BPCI bus then the BAR0 and BAR1 registers must be programmed identically. When MAEB = 0,

the BPCI bus cannot access the 82600 SDRAM.

0 I/O Access Enable. Hardwired to a 0. The 82600 does not respond to BPCI I/O cycles.

116 Subject to Change Advance Information


4.21.4 BPCISTS, BPCI Status Register: A=6, 1.0.86, R=0230

R

This register can also be accessed as the secondary status register within the P2P (offset 0x1E) configuration space.

Bit Description

15 Detected Parity Error. Hardwired to a 0.

14 Signaled SERR# Status – R/WC. When the 82600 asserts the SERR# signal, this bit is set to 1.

Writing a 1 to this bit position clears this bit. Writing a 0 has no effect on this status bit.

13 Received Master Abort Status – R/WC. When the 82600 generates a BPCI master-abort, then this

status bit is set. In addition, the Backplane Abort Address Register latches the abort address

whenever the “OR” of the 2 “abort” status bits (see Received Target Abort Status) is asserted. If

both abort bits are set, the Local Abort Address register will contain the address of the “first” (in

time) abort address. Writing a 1 to this bit position clears this bit. Writing a 0 has no effect on this

status bit.

12 Received Target Abort Status – R/WC. When the 82600 initiates a BPCI bus transaction and

receives a target abort, this bit is set. In addition, the Backplane Abort Address Register latches

the abort address whenever the “OR” of the 2 “abort” status bits (see Master Target Abort Status)

is asserted. If both abort bits are set, the Local Abort Address register will contain the address of

the “first” (in time) abort address. Writing a 1 to this bit position clears this bit. Writing a 0 has no

effect on this status bit.

11 Signaled Target Abort Status. Hardwired to a 0

10:9 DEVSEL# timing. Hardwired to 01 (medium timing).

8 PERR# Response. Hardwired to a 0

7 Target Fast Back to Back. This bit is hardwired to 0. The 82600, as a target, cannot respond to

fast back to back accesses.

6 Reserved. Hardwired to 0.

5 66MHz Capable. Hardwired to 1.

4 ECP Support. Hardwired to 1 to indicate support for Enhanced Capabilities (Hot swap friendly).

3:0 Reserved. Hardwired to 0.

4.21.5 BRID, Revision Identification Register: A=8, 1.0.88, R=00

Bit Description

7:0 Revision Identification Register – R/W. The 82600 RID is 00. This value may be overwritten from

the host interface side. This value is read-only from the BPCI interface.

Advance Information Subject to Change 117


R

4.21.6 BCLASSC, Class Code Register: A=9, 1.0.89:

R=060000 (in Central Resource mode): R=000000 (in Peripheral Bridge mode)

When configured as the BPCI Central Resource, this register is initialized to the Host Bridge class code. Otherwise it

is initialized to an undefined class code. All 3 byte fields may be overwritten from the host interface side. This

register is read-only from the BPCI interface.

Bit Description

23:16 Base Class Code – R/W. This is set to 06 (Bridge device) if the 82600 is configured as the BPCI

Central Resource. This is set to 00 (undefined … 0x0E = I20), if the 82600 is configured as the

BPCI Peripheral Bridge. This value may be overwritten from the host interface side. This value is

read-only from the BPCI interface.

15:8 Sub Class Code – R/W. This is set to 00 initially. This value may be overwritten from the host

interface side. This value is read-only from the BPCI interface.

7:0 Programming Interface – R/W. This is set to 00 initially. This value may be overwritten from the

host interface side. This value is read-only from the BPCI interface.

4.21.7 BCLS, Cache Line Size Register: A=C, 1.0.8C, R=08

Bit Description

7:0 Cache Line Size Register - RO. This register indicates the number of 32-bit words that are

included in a single cache line. Since the 82600 supports a 32-byte line, the value in this register is

hardwired to 08.

4.21.8 BMLT, Master Latency Timer: A=D, 1.0.8D, R=00

Bit Description

7:3 Master Latency Timer Count Value – R/W. These are physically the same bits as the SLT

Secondary Latency Timer bits (1B,1.0.1B). The value placed in these bits with the 3 LSBs always =

0 forms an 8-bit count value that defines the guaranteed time slice (measured in BPCI clocks) given

to the 82600 before it must surrender mastership of the BPCI bus, if other BPCI agents are

requesting access to the bus. This value may be written from either the host or BPCI interface.

2:0 Reserved. Hardwired to 0.

4.21.9 BHT, Header Type: A=E, 1.0.8E, R=00

Bit Description

7:0 Header Type. This is hardwired to 0: standard configuration register space.

118 Subject to Change Advance Information


4.21.10 BBIST, BIST Register Timer: A=F, 1.0.8F, R=00

R

This register is initialized to indicate no BIST support; however, BIST is supported by modifying the value in this

register from the host bus side. If BIST is supported, the host software must respond to interrupt 15 to supply the

BIST routine. Only bit 6 may be written from the BPCI interface.

Bit Description

7 BIST Supported – R/W. This bit is initialized to 0 (no BIST support), but may be written from the

host side to a 1 to indicate BIST support.

6 Start BIST – R/W. This bit is initialized to 0. The BPCI interface may start BIST by setting this bit.

When set, IRQ9 (level sensitive) is asserted to the local host. host software must complete the

BIST within 2 seconds (write this bit back to 0 and write the Completion Code).

5:4 Reserved. Hardwired to 0.

3:0 Completion Code – R/W. This field is initialized to 0. It may be subsequently written from the host

side to indicate a failing BIST completion code. A 0 code indicates that BIST passed; however, this

field should only be read by the BPCI Central Resource after first setting the Start BIST bit and

waiting for it to be cleared by the local host.

Advance Information Subject to Change 119


R

4.21.11 BAR0, Base Address Register 0: A=10, 1.0.90, R=0000_0000

This register, taken together with the MRBAR0 register, allows a minimum of 1MB up to a maximum of 2GB of main

memory to be mapped to the BPCI bus. When the 82600 is configured as a Peripheral Bridge, this register allows the

Central Resource in the system to configure a portion of the 82600 main memory into the BPCI address space. This

register (along with the MRBAR) must also be programmed even when the 82600 is configured as the Central

Resource. As a Central Resource, it would normally be programmed to allow all of its memory to be accessible from

the BPCI bus starting at BPCI address 0; however, the full capability of this register may be used to protect all or a

portion of the 82600 main memory from the BPCI bus interface.

Before the memory region defined by this register is accessible by the BPCI bus, memory access must be enabled by

the Memory Access Enable bit of the BPCI Command Register. The Memory Access Enable bit enables BPCI access

to 82600 SDRAM as defined by both the BAR0 and BAR1 registers. Both the BAR0 and BAR1 registers must be

programmed before the Memory Access Enable bit is set. If only a single region of 82600 SDRAM is to be accessible

by the BPCI bus then the BAR0 and BAR1 registers must be programmed identically.

Bit Description

31:20 Base Address – R/W. The contents of these bits are matched against incoming BPCI addresses (bit

31 !xor AD31, bit 30 !xor AD30 … bit 20 !xor AD20.) to determine if the 82600 is the target of a BPCI

memory transaction. Bits 30-20 may be masked by the MRBAR0 Register (A = 1.0.C0) to allow more

than 1MB of BPCI memory space to be mapped to the 82600. These bits may be read and written

from both the host bus and BPCI bus interfaces; however, all or a least significant contiguous

subset of the bits 30-20 may be masked-off (always read as 0) by the MRBAR Register.

19:4 Base Address Don’t Cares. These bits are hardwired to a 0. The 82600 requires at least 1MB of

memory be allocated to BPCI space if the BPCI address space is enabled.

3 Prefetch. This bit is hardwired to a 0.

2:1 Type. This is hardwired to a 00: locate anywhere in the 32-bit address space.

0 Memory Space Indicator. This is hardwired to a 0 to indicate that this is a memory space address (as

opposed to I/O).

120 Subject to Change Advance Information


4.21.12 BAR1, Base Address Register 1: A=14, 1.0.94, R=0000_0000

R

This register, taken together with the MRBAR1 register, allows a minimum of 1MB up to a maximum of 1GB of main

memory to be mapped to the BPCI bus. When the 82600 is as a Peripheral Bridge, this register allows the Central

Resource in the system to configure a portion of the 82600 memory into the BPCI address space. This register (along

with the MRBAR1) must also be programmed even when the 82600 is configured as the Central Resource. As the

Central Resource, it would normally be programmed to allow all of its memory to be accessible from the BPCI bus

starting at BPCI address 0; however, the full capability of this register may be used to protect all or a portion of the

82600 main memory from the BPCI bus interface.

Before the memory region defined by this register is accessible by the BPCI bus, memory access must be enabled by

the Memory Access Enable bit of the BPCI Command Register. The Memory Access Enable bit enables BPCI access

to 82600 SDRAM as defined by both the BAR0 and BAR1 registers. Both the BAR0 and BAR1 registers must be

programmed before the Memory Access Enable bit is set. If only a single region of 82600 SDRAM is to be accessible

by the BPCI bus then the BAR0 and BAR1 registers must be programmed identically.

Bit Description

31:20 Base Address – R/W. The contents of these bits are matched against incoming BPCI addresses (bit

31 !xor AD31, bit 30 !xor AD30 … bit 20 !xor AD20.) to determine if the 82600 is the target of a BPCI

memory transaction. Bits 30-20 may be masked by the MRBAR1 register (A = 1.0.C0) to allow more

than 1MB of BPCI memory space to be mapped to the 82600. These bits may be read and written

from both the host bus and BPCI bus interfaces; however, all or a least significant contiguous

subset of the bits 30-20 may be masked-off (always read as 0) by the MRBAR register.

19:4 Base Address Don’t Cares. These bits are hardwired to a 0. The 82600 requires at least 1MB of

memory be allocated to BPCI space, if the BPCI address space is enabled.

3 Prefetch. This bit is hardwired to a 0.

2:1 Type. This is hardwired to a 00: locate anywhere in the 32-bit address space.

0 Memory Space Indicator. This is hardwired to a 0 to indicate that this is a memory space address (as

opposed to I/O).

4.21.13 BSUBVID, Sub-Vendor Identification Register: A=2C, 1.0.AC, R=0000

Bit Description

15:0 Sub-Vendor Identification Register– R/W. This is initialized to 0. This value may be overwritten

from the host interface side. This value is read-only from the BPCI interface.

4.21.14 BSUBDID, Sub-Device Identification Register: A=2E, 1.0.AE, R=0000

Bit Description

15:0 Sub-Device Identification Register – R/W. The SUBDID defaults to 0000. This value may be

overwritten from the host interface side. This value is read-only from the BPCI interface.

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4.21.15 RBAR, ROM Base Address Register: A=30, 1.0.B0, R=0000_0000

Bit Description

31:11 ROM Base Address. Bits 13-11 are hardwired to 0 (16Kbyte expansion size). Bits A31-A14 may be

read/written from both the host or BPCI bus with the BPCI address that will be used to access the a

16KB section of the 82600 ROM region defined by the RRBAR register. More “expansion” ROM

code can be obtained from the memory window (read/write memory pointed to by the BAR, A =

0.10) at the cost of duplicating a ROM image in RAM space and using the ROM base address code

to “bootstrap” into the RAM memory.

10:1 Reserved. Hardwired to 0

0 Address Decode Enable – R/W. This bit, when set, enables accessing the expansion ROM from the

BPCI interface. The Memory Access Enable bit in the PCICMD register (bit1) must also be set to

allow access to this ROM.

4.21.16 CPR, Capabilities Pointer Register: A=34,1.0.B4, R=50

Bit Description

7:0 Capabilities Pointer. Hardwired to 50. These bits form the head of a capabilities linked list. The

pointer is an offset into the configuration space header and points to the Hot Swap Friendly

capabilities entry.

122 Subject to Change Advance Information


4.21.17 ILIP, Interrupt Line/Interrupt Pin Register: A=3C,1.0.BC, R=0000

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This register is only used when the 82600 is configured as a Peripheral Bridge on the BPCI bus. When configured as

the Central Resource, the value stored in this register does not have any effect on the 82600.

Bit Description

15-13 Reserved. Hardwired to a 0.

12:11 Assert Interrupt – R/W. When these bits are set to “10” (bit12 = 1, bit11 = 0), then an interrupt

will be asserted on the selected BPCI interrupt line (see bits 10:8). These bits have no effect on the

82600 when it is configured in Central Resource mode.

10:8 BPCI Interrupt Pin – R/W. This three bit encoding determines which BPCI interrupt line the 82600

uses to signal outbound BPCI interrupts as follows:

000 No interrupt pin

001 BPIRQA#

010 BPIRQB#

011 BPIRQC#

100 BPIRQD#

101 No interrupt pin

11x No interrupt pin.

This register may be read/written from the local host or BPCI interface. If no interrupt pin is

selected, than all four BPCI interrupt pins may instead be used as level sensitive local interrupt

inputs. When one of the BPCI interrupts is selected to signal outgoing interrupts, then the

remaining three interrupts may be used as level sensitive interrupt inputs (see BIRQRC - the

BPIRQx Route Control registers for details). To initiate a BPCI interrupt on the selected BPCI

BPIRQx# line either bits 12 and 11 of this register or the Local to PCI Doorbell Register (0xC0-C3)

can be used. These bits have no effect on the 82600 when it is configured as the Central Resource.

7:0 Interrupt Line – R/W. The value written into this register by the Central Resource determines the

interrupt line/level that the BPCI interrupt pin is mapped-into back at the Central Resource. For x86

systems, the lower 4 bits encode the interrupt line (IRQ0- IRQ15) that is to be used. This value may

be read/written from either the BPCI or local host interface and are purely “RAM” bits: they have

no effect on the 8259s or any other function inside the 82600.

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4.21.18 PGNTLAT, BPCI Arbitration Grant/Latency Register: A=3E,1.0.BE, R=0000

Bit Description

15:8 Maximum Latency – R/W. The value in this register is read-only from the BPCI side and may be

written from the local host side with the value in quantas of 0.25microseconds that indicates how

quickly the 82600 will want to gain ownership of the BPCI bus. This value has no internal effect on

the 82600, but is to be read by the Central Resource to allow it to optimize its BPCI arbitration

process if possible.

7:0 Minimum Grant Latency – R/W. The value in this register is read-only from the BPCI side and

may be written from the local host side with the value in quantas of 0.25microseconds that

indicates how long the 82600 will want to retain ownership of the BPCI bus. This value has no

internal effect on the 82600, but is to be read by the Central Resource to allow it to optimize its

BPCI arbitration process if possible.

4.21.19 MRBAR0, Memory Remap Base Address Register 0: A=40, 1.0.C0, R=0000_0000

This register allows a portion or all of the 82600 main memory to be flexibly mapped into BPCI memory space. It

allows a minimum of 1MB and a maximum of 2GB of memory to be shared in BPCI address space. For example, if the

design has 32MB of 82600 memory and 4MB of this is shared in the BPCI address space, the 4MB of BPCI shared

memory could start at anyone of eight host address boundaries: 0, 4MB, 8MB, 12MB, 16MB, 20MB, 24MB, and

28MB. MRBAR0 can also be set to point to SDRAM resident flash, if it exists. In this case BDEVSEL# will only be

asserted for BPCI read transactions that match the BAR0 address.

Bit Description

31:19 Remap/Mask Bits – R/W. All or a contiguous portion of these bits replace the upper address bits

from the BPCI interface destined for the 82600 SDRAM interface. Bit 31 is hardwired to 0

(corresponds to A31). Bits 30:20 can be written from the local host interface only and correspond

to A30-A20, respectively. Bit 19, if set, enables replacement of A31-A20 and address matching on

the same address range in the BAR0. If clear, replacement and address matching begins at the next

bit beyond the demarcation line marked by the least significant “1” in this register. For example, if

bit 21 is the least significant “1”, then A31-A22 would be replaced with register bits 31-22 to form

the address forwarded to the 82600 SDRAM controller and addresses from AD31-AD22 from the

BAR0 would be used by the BPCI decoder (enabling 4MB of BPCI mapped memory region through

the 82600)

18:0 Reserved. Hardwired to 0.

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4.21.20 MRBAR1, Memory Remap Base Address Register 1: A=44, 1.0.C4, R=0000_0000

This register allows a portion or all of the 82600 main memory to be flexibly mapped into BPCI memory space. It

allows a minimum of 1MB and a maximum of 2GB of memory to be shared in BPCI address space. For example, if the

design has 32MB of 82600 memory and 4MB of this is shared in the PCI address space, the 4MB of BPCI shared

memory could start at anyone of eight host address boundaries: 0, 4MB, 8MB, 12MB, 16MB, 20MB, 24MB, and

28MB. MRBAR1 can also be set to point to SDRAM resident flash, if it exists. In this case BDEVSEL# will only be

asserted for BPCI read transactions that match the BAR1 address.

Bit Description

31:19 Remap/Mask Bits – R/W. All or a contiguous portion of these bits replace the upper address bits

from the BPCI interface destined for the 82600 SDRAM interface. Bit 31 is hardwired to 0

(corresponds to A31). Bits 30:20 can be written from the host interface only and correspond to

A30-A20, respectively. Bit 19, if set, enables replacement of A31-A20 and address matching on the

same address range in the BAR1. If clear, replacement and address matching begins at the next bit

beyond the demarcation line marked by the least significant “1” in this register. For example, if bit

21 is the least significant “1”, then A31-A22 would be replaced with register bits 31-22 to form the

address forwarded to the 82600 SDRAM controller and addresses from AD31-AD22 from the BAR1

would be used by the BPCI decoder (enabling 4MB of BPCI mapped memory region through the

82600)

18:0 Reserved. Hardwired to 0.

4.21.21 RRBAR, ROM Remap Base Address Register: A=48, 1.0.C8, R=0000_0000

Bit Description

31:14 ROM Remap Base Address – R/W. These bits replace the upper 18 address bits from the BPCI

interface destined for the 82600 SDRAM/flash interface. These bits can be used to remap BPCI

addresses that match the RBAR address, provided the ROM exists on the 82600 SDRAM interface.

Flash/ROM that exists on the LPCI bus may not be directly accessed from the BPCI bus using this

mechanism; however, LPCI ROMs may be first copied to a section of SDRAM to make them

accessible to the BPCI bus.

13:0 Reserved. Hardwired to 0.

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4.21.22 MBPC, Miscellaneous BPCI Control: A=4C,1.0.CC, R=00

Bit Description

7 Arbiter Timeout, R/WC. This bit is set by hardware when the BPCI arbiter does not see

BFRAME# asserted within 16 clocks of asserting a BGNTx# to a bus master. When this occurs the

BGNTx# is negated and the BREQx# signal is ignored. Writing a 1 to this bit position clears this bit.

6:3 Reserved. Hardwired to 0.

2:1 Target Prefetch Control – R/W.

0x 82600 immediately invalidates any read data prefetched and not used by a BPCI access.

10 82600 retains prefetched data for all read commands until invalidated by a host bus write or

consumed by a BPCI memory operation.

11 82600 retains prefetch data for read-multiple and read-line commands, but immediately

invalidates bytes not consumed by a BPCI memory read command.

0 BPCICR Ready – R/W. This bit powers up clear. Once the BIOS or power-up monitor has set all of

the BPCI accessible configuration registers to the values desired (e.g. BSUBVID, BSUBDID, etc.),

this bit should be set. Until this bit is set, the 82600 responds with Retry to BPCI configuration

accesses from the BPCI interface. Local host interface reads/writes are independent of the state of

this bit. Once this bit has been written to a 1 it can only be cleared by a hardware power-on.

126 Subject to Change Advance Information


4.21.23 HSC, Hot Swap Capability Register: A=50,1.0.D0, R=0000_0006

This register is only useful when the 82600 is configured as a Peripheral Bridge on the BPCI bus.

Bit Description

31:24 Reserved. Hardwired to 0.

23 ENUM Insert Status - R/WC This bit is set in hardware by the low to high edge detection of the

AND gate output formed from the BPCICR Ready bit (set by software in the Miscellaneous BPCI

Control register) and the EJECTSTS pin being high (ejector locked/closed). While this status bit is

high, the ENUM# open drain pin is driven low provided the ENUM Mask bit is 0. Writing a 1 to

this bit clears it. Writing a 0 has no effect on this bit. This bit is asynchronously cleared by

negation of PWRGOOD.

22 ENUM Extract Status - R/WC. After a board insertion event, this bit is set in hardware when the

EJECTSTS pin is low (ejector unlocked/open). Writing a 1 to this bit clears it. Writing a 0 has no

effect on this bit. This bit is asynchronously cleared by negation of PWRGOOD and cannot be set

until ENUM Insert Status has transitioned from high to low.

21:20 Reserved. Hardwired to 0.

19 LED On/Off Control - R/W. When set to a one, the LEDOUT pin is asserted if the 82600 is in

Peripheral Bridge mode. This bit is internally ORed with both the negation of PWRGOOD as well

as with the assertion of BRST# (the BPCI RESET signal) to assert the LEDOUT pin.

18 Reserved. Hardwired to 0

17 ENUM Mask - R/W. 0 = Assert ENUM#, if ENUM Insert or ENUM Extract Status bits are set

1 = Disable assertion of ENUM#.

16 Reserved. Hardwired to 0

15:8 Next Item Pointer. This is hardwired to 0 to indicate the last item in the linked list.

7:0 Capabilities ID. This is hardwired to 06 to indicate that the functionality implemented is

CompactPCI Hot Swap compatible.

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4.21.24 LPID, Local to BPCI Interrupt Doorbell Register: A=60,1.0.E0, R=0000_0000

Bit Description

31:0 BPCI Doorbell Bits-R/W (local host), R/WC (BPCI). When the 82600 is in Peripheral Bridge

mode, a non-zero local host write to this register causes a BPCI interrupt to be generated on the

BPCI interrupt pin designated by the Interrupt Line/Interrupt Pin register. The BPCI Central

Resource can clear pending doorbell bits by writing a 1 to the bit position to be cleared. A BPCI

access that writes 0’s into this register has no effect. The BPCI interrupt will be asserted until all

local to BPCI doorbell bits are cleared.

Advance Information Subject to Change 127


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4.21.25 PLID, PCI to Local Interrupt Doorbell Register: A=64,1.0.E4, R=0000_0000

Bit Description

31:0 PCI Doorbell bits-R/WC (local host), R/W (BPCI). A non-zero BPCI write to this register causes

a local interrupt to be generated internally as though the BPCI interrupt input designated by the

Interrupt Line/Interrupt Pin register has been asserted. The interrupt uses the BPCI to 8259

interrupt-mapping registers. The local host can clear pending doorbell bits by writing a 1 to the bit

position to be cleared. A local host access that writes 0’s into this register has no effect. The

interrupt will continue be asserted until all BPCI to local doorbell bits are cleared.

4.21.26 BAAR, Backplane Abort Address Register: A=7C,1.0.FC, R=0000_0000

Bit Description

31-0 Abort Address - RO. The Abort Address Register latches the appropriate abort address whenever

the “OR” of the two “abort” status bits (see Master and Receive Target Abort Status bits in the

BPCI Status Register) is asserted. If both abort bits are set, the Local Abort Address register will

contain the address of the “first” (in time) abort address that occurs. This register is read-only

and is only valid when at least one of the two abort status bits are set. A new abort address can be

loaded only after clearing the abort status bits in the BPCI status register before a new BPCI abort

occurs. If a memory transfer was in progress when the abort occurred a Dword aligned address will

be loaded into this register. If an I/O transfer was in progress the true address will be loaded into

this register.

4.22 Embedded 16550 UART Register Descriptions:

General Description

The 82600 embedded Universal Asynchronous Receiver/Transmitters (UARTs) support full duplex asynchronous

communication. This is compatible to the NS16450, but adds a transmit and receive FIFOs to the base feature set.

The major features of the UARTs are:

(1) Complete asynchronous communication protocol including

-5, 6, 7 or 8 bit data transmission.

-Even/odd or no parity bit generation & detection.

-Start & stop bit generation & detection.

-Line break detection & generation.

-Receiver overrun & framing errors detection.

-Communications rates of upto 256K baud.

(2) Internal Programmable Baud Rate Generator.

(3) Two Modes of operation - NS16450 and FIFO mode.

(4) Transmitter is buffered with 16 Byte FIFO.

(5) Receiver is buffered with 16 Byte FIFO plus 3 error bits per data byte.

(6) Exception handling using interrupt/polled modes.

(7) Internal Diagnostic capabilities with loopback.

128 Subject to Change Advance Information


(8) Modem handshake capability using CTS, RTS, DSR, DTR, RI & DCD signals.

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Internal registers of the UART provide full programmability of serial asynchronous communication parameters. The

communication line & modem status can be monitored at any time by the local processor by reading appropriate

registers in the UART.

The register I/O addresses are described in Table 10. Please note that addresses 2F8/3F8 and 2F9/3F9 actually

control two different register functions depending upon the DLAB bit (bit 7 of the LCR, 2FB/3FB).

DLAB COM1

I/O address

COM2

I/O address

Table 10 UART Registers

Register

0 3F8 2F8 Receiver Buffer Register(RBR)- Read Only.

Transmitter Holding Register(THR)- Write Only.

0 3F9 2F9 Interrupt Enable Register(IER)- Read/Write.

X 3FA 2FA Interrupt Identification Register(IIR) - Read Only.

FIFO Control Register(FCR)- Write Only.

X 3FB 2FB Line Control Register(LCR)- Read/Write.

X 3FC 2FC MODEM Control Register(MCR)- Read/Write.

X 3FD 2FD Line Status Register(LSR) - Read Only.

Factory Test Register(FTR) - Write Only.

X 3FE 2FE MODEM Status Register(MSR) - Read Only.

X 3FF 2FF Scratch Pad Register(SPR) - Read/Write.

1 3F8 2F8 Divisor Latch Lower(DLL)- Read/Write.

1 3F9 2F9 Divisor Latch Higher(DLM)- Read/Write.

4.22.1 RBR/THR, Receiver Buffer Register/Transmitter Holding Register

A=2F8 & 3F8 (DLAB = 0), R=xx

Data that has been received or is to be transmitted is read/written to this register, provided DLAB = 0.

Bit Description

7:0 RBR, RO; THR, WO. A read of this register returns received serial data, if the Data Ready bit is set in

the LSR register. A read of this register will also clear the Data Ready bit. A write to this register will

supply data the transmitter block to be transmitted serially via the Txd pin. A write to this register will also

clear the THRE and TEMT bits in the LSR register.

Advance Information Subject to Change 129


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4.22.2 DLL, Divisor Latch Lower: A=2F8 & 3F8 (DLAB = 1), R=xxxx

This 16-bit register is used to divide the UART’s input clock down to the appropriate baud rate for both receiving

and transmitting characters serially.

Bit Description

15:0 Divisor Latch - R/W. This register is loaded with a baud rate divisor value. The baud rate achieved can

be calculated by first dividing the UART’s input clock (nominally 1.843Mhz for PC compatible operation)

by 16 and then by the value in this register. The baud rate output for the divisor value of 0 is same as that

for the divisor value of 1.

4.22.3 IER, Interrupt Enable Register: A=2F9 & 3F9 (DLAB = 0), R=xx

These register bits enable an interrupt to be asserted on IRQ3(COM2) or IRQ4(COM1) provided the respective OUT2

bit is low. To negate the IRQ, the respective status bit that is causing the interrupt can be cleared (see status bit

descriptions in the other registers) or a read of the IIR register will also clear the IRQ.

Bit Description

7:4 Reserved. Hardwired to 0..

3 Enable MSR Interrupt - R/W. This bit enables asserting an interrupt on the respective interrupt line

whenever a modem status register signal is asserted. The sources for this interrupt are the CTS, DSR, RI,

and DCD modem status register bits.

2 Enable LSR Interrupt - R/W. This bit enables asserting an interrupt on the respective interrupt line

whenever a receiver error status is detected in the Line Status Register (LSR). The sources of this

interrupt are overrun error, parity error, framing error, and break errors.

1 Enable THRE Interrupt - R/W. This bit enables asserting an interrupt on the respective interrupt line

whenever the Transmitter Holding Register Empty flag is asserted (ready for more data to be sent to the

THR)..

0 Enable DR interrupt - R/W. This bit enables asserting an interrupt on the respective interrupt line

whenever the Data Ready signal is asserted (data is ready to be read in the Read Buffer Register, RBR).

130 Subject to Change Advance Information


4.22.4 FCR, FIFO Control Register: A=2FA & 3FA, R=xx

Bit Description

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7:6 RCVR FIFO Trigger Level - WO. The trigger level interrupt is generated when the number of bytes

received in the RCVR FIFO is equal to or greater than the trigger level set by these two bits. The following

table shows the trigger level for the RCVR FIFO.

Encoding Trigger Level

00 1 byte

01 4 bytes

10 8 bytes

11 14 bytes

5:4 Reserved. Hardwired to 0.

3 FCR3 - WO. This bit, when set (bit 0 must also be set), causes the DMA signals (nrxrdy and ntxrdy) to

change from mode 0 to mode 1.

2 FCR2 - WO. This bit is used to reset the XMIT FIFO. When set (bit 0 must also be set), it will reset the

XMIT FIFO and it’s counter logic as well as resetting itself.

1 FCR - WO. This bit is used to reset the RCVR FIFO. When set (bit 0 must also be set), it will reset the

RCVR FIFO and it’s counter logic as well as resetting itself.

0 FCR0, WO. This bit enables the FIFOs when set. The other bits of this register will be programmed only if

this bit is set. Whenever this bit changes the state(either from low to high or from high to low) it resets

the data in the RCVR and the XMIT FIFOs.

Advance Information Subject to Change 131


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4.22.5 IIR, Interrupt Identification Register: A=2FA & 3FA, R=xx

Bit Description

7:6 FIFO mode - RO. Both of these bits reflect the value stored in bit 0 of the FCR register.

5:4 Reserved. Hardwired to 0.

3 Timeout pending - RO. 1 = Character timeout interrupt is pending (FIFO mode only). When bit is high bits

2&1of this register will read as a “10”. 0 = no timeout interrupt is pending. When 0, a bit 2&1 encoding of

“10” indicates a Received Data Ready interrupt. This bit is always 0 when bit 0 of the FCR register is 0

(FIFO mode is off).

2:1 Interrupt Code - RO. This two bit field indicates the source of the interrupt as follows:

Encoding Priority Interrupt

00 4 th

01 3 rd

10 2 nd

11 1 st

Modem status (CTS,DSR,RI, or DCD).

Transmitter Holding Register is empty (THRE)

Received Data Ready (DR) or character timeout (see bit 3 above).

Receiver Line Status Error (Overrun, Parity, Frame, or Break).

0 Interrupt Pending - RO. This bit is clear when an interrupt is pending. The inversion of this signal

connects to IRQ3 (COM2) or IRQ4 (COM1).

132 Subject to Change Advance Information


4.22.6 LCR, Line Control Register: A=2FB & 3FB, R=xx

The Line Control Register determines the format of the asynchronous communication protocol.

Bit Description

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7 DLAB - R/W. This is the divisor latch access bit (DLAB). This bit is set high to access the divisor

latches for the read or write operation. This bit is set low to access the Receiver Buffer Register,

Transmitter Holding Register or the Interrupt Enable Register.

6 Set Break - R/W. When set high, this bit forces the serial output Txd to the logic 0 state..

5:3 Parity control - R/W. These bit controls the generation and checking of parity as follows.

LCR[5:3] Parity Bit

000 no parity

001 odd parity (odd number of 1’s)

010 no parity

011 even parity (even number of 1’s)

100 no parity

101 parity = 1’b1

110 no parity

111 parity = 1’b0

2:0 Character Length and Stop Bit – R/W. The two LSBs of LCR decide the number of data bits to be

received or transmitted in a character. Bit 2 (stopbit) along with the two LSBs specify the number of stop

bits to be transmitted. The receiver checks for the first stop bit only. The following table shows the

number of data bits to be transmitted or received and the number of stop bits to be transmitted:

LCR[2:0] Char. Length Number of Stop Bits

000 5 1

001 6 1

010 7 1

011 8 1

100 5 1.5

101 6 2

110 7 2

111 8 2

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4.22.7 MCR, Modem Control Register: A=2FC & 3FC, R=xx

Bit Description

7:5 Reserved. Hardwired to 0..

4 Loop - R/W. When set, the UART is placed into a loop mode of operation. This feature is used to check

the receiver and the transmitter path. In loop mode the following occur: the MODEM control output

signals are internally connected to the MODEM status input signals and the MODEM output signals are

forced to their inactive state (high). The external serial output pin, TXD, is forced to a logic 1 state. The

serial input pin, RXD, is disconnected and the output of the Transmitter shift register is internally

connected to the receiver shift register input of the UART to effect the loop-back mode of operation.

3 OUT2 - R/W. This bit is used to control whether the associated UART drives the internal interrupt

controller or an external source drives the interrupt controller.

2 OUT1 - R/W. This is just a RAM bit. The state of this bits that does not effect the UART or the 82600.

1 RTS - R/W. This bit drives the state of the associated RTS# external pin. When 0, the external RTS# pin

is driven negated (high level on pin). When 1, the external RTS# pin is driven asserted..

0 DTR - R/W. This bit drives the state of the associated DTR# external pin. When 0, the external DTR# pin

is driven negated (high level on pin). When 1, the external DTR# pin is driven asserted.

4.22.8 LSR, Line Status Register: A=2FD & 3FD, R=xx

The Line Status Register provides the status information regarding the data transfer.

Bit Description

7 Reserved. Hardwired to 0.

6 Transmitter Empty(TEMT) - RO. This bit is set whenever both THR (transmitter holding register/FIFO)

and the transmitter shift register is empty.

5 Transmitter Holding Register Empty (THRE) - RO. This bit is set when the THR is empty. This bit is

cleared whenever a byte is written to the THR (DLAB must be 0).

4 Break Error (BI) - RO. This bit is set high whenever the serial input (RXD) remains low for than a

character time. This bit is cleared by reading this register

3 Framing Error (FE) - RO. This bit is set high whenever a Stop bit is not asserted. This bit is cleared by

reading this register.

2 Parity Error (PE) - RO. This bit is set high whenever the received parity does not have the proper parity.

This bit is cleared by reading this register

1 Overrun Error (OE) - RO. This bit is set high whenever the last byte received is not read before the new

byte is transferred into the RBR. This bit is cleared by reading this register.

0 Data Ready (DR) - RO. This bit is set high when data is completely received and transferred to the RBR

register. This bit is clear by reading the data from the RBR register (2F8/3F8)

134 Subject to Change Advance Information


4.22.9 FTR, Factory Test Register: A=2FD&3FD, R=xx

Bit Description

7:3 Reserved. Writing to these bits have no effect..

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2 Force Frame Error – R/W. 1 = Force the transmitter to generate framing errors. 0 = Normal operation.

1 Force Parity Error – R/W. 1 = Force the transmitter to generate parity errors. 0 = Normal operation.

0 Test Baud Rate Generator – R/W. 1 = Switch upper and lower bytes of the Divisor latch to enable testing

the upper byte of the divisor latch in < 256 clocks. 0 = Normal operation..

4.22.10 MSR, Modem Status Register: A=2FE & 3FE, R=xx

Bit Description

7 DCD - RO. A read of this bit returns the logic value (inverted from the external pin) on the associated

external DCD# pin.

6 RI - RO. A read of this bit returns the logic value (inverted from the external pin) on the associated

external RI# pin.

5 DSR - RO. A read of this bit returns the logic value (inverted from the external pin) on the associated

external DSR# pin.

4 CTS - RO. A read of this bit returns the logic value (inverted from the external pin) on the associated

external CTS# pin.

3 DDCD - RO. This bit is set whenever a logic level change is detected on the associated DCD# external

pin. A read of this register or hardware reset clears this bit.

2 TERI - RO.. This bit is set when the associated RI# external pin is negated. A read of this register or

hardware reset clears this bit.

1 DDSR - RO. This bit is set whenever a logic level change is detected on the associated DSR# external

pin. A read of this register or hardware reset clears this bit.

0 DCTS - RO.. This bit is set whenever a logic level change is detected on the associated CTS# external

pin. A read of this register or hardware reset clears this bit.

4.22.11 SPR, Scratch Pad Register, A=2FF/3FF, R=xx

Bit Description

7:0 Scratch - R/W. The Scratch Pad Register does not affect the UART in any way. It can be used as a

scratchpad register by an application.

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4.23 Embedded 82C206 Peripheral Register Descriptions:

Table 11: 8254 Compatible Counter/Timer I/O Registers

Port Register Name/Function Default Value Type

40h Counter 0 Interval Time Status Byte Format 0XXXXXXXb Read Only

Counter 0 Counter Access Port Register Undefined Read/Write

41h Counter 1 Interval Time Status Byte Format 0XXXXXXXb Read Only

Counter 1 Counter Access Port Register Undefined Read/Write

42h Counter 2 Interval Time Status Byte Format 0XXXXXXXb Read Only

Counter 2 Counter Access Port Register Undefined Read/Write

43h Timer Control Word Register Undefined Write Only

Timer Control Word Register Read Back XXXXXXX0b Write Only

Counter Latch Command X0h Write Only

136 Subject to Change Advance Information


4.23.1 TCW - Timer Control Word Register: A=43, R=xx

R

The Timer Control Word Register specifies the counter selection, the operating mode, the counter byte programming

order and the size of the count value. It also specifies whether the counter counts down in a 16 bit BCD format or

binary format. After writing the control word, a new count can be written at any time. This value takes effect

according to the programmed mode.

This register is programmed prior to any counter being accessed to specify counter modes. Following 82600 reset,

the control words for each register are undefined and each counter output is 0. Each timer must be programmed to

bring it into a known state.

Bit Description

7:6 Counter Select – R/W. The Counter Selection bits select the counter or the control word to be acted

upon as shown below. The Read Back Command is selected when bits[7:6] are both 1

00 Counter 0 select

01 Counter 1 select

10 Counter 2 select

11 Read Back Command

5:4 Read/Write Select – R/W. These bits are the read/write control bits. The actual counter programming is

done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2)

00 Counter Latch Command

01 Read/Write Least Significant Byte (LSB)

10 Read/Write Most Significant Byte (MSB)

11 Read/Write LSB then MSB

3:1 Counter Mode Selection – R/W. These bits select one of six possible modes of operation for the selected

counter.

000 0 Out signal on end of count ( = 0)

001 1 Hardware retriggerable one-shot

x10 2 Rate generator (divide by n counter)

x11 3 Square wave output

100 4 Software triggered strobe

101 5 Hardware triggered strobe

0 Binary/BCD Countdown Select – R/W.

0 Binary countdown is used. The largest possible binary count is 216

1 Binary coded decimal (BCD) count is used. The largest possible BCD count is 104

There are two special commands that can be issued to the counters through the Timer Control Word Register, the

Read Back Command and the Counter Latch Command. When these commands are chosen, several bits within this

register are redefined. These register formats are described below.

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4.23.2 Read Back Command

The Read Back Command is used to determine the count value, programmed mode, and current states of the OUT pin

and Null count flag of the selected counter or counters. Status and/or count may be latched in any or all of the

counters by selecting the counter during the register write. The count and status remain latched until read, and

further latch commands are ignored until the count is read.

Both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to 0. If

both are latched, the first read operation from that counter returns the latched status. The next one or two reads,

depending on whether the counter is programmed for one or two byte counts, returns the latched count. Subsequent

reads return an unlatched count.

Bit Description

7:6 Read Back Command – R/W. When bits[7:6] = 11, the Read Back Command is selected during a write to

the Timer Control Word Register. Following the Read Back Command, I/O reads from the selected

counter’s I/O address produce the current latch status, the current latched count or both if bits 4 and 5

are both 0.

5 Latch Count of Selected Counters – R/W.

0 Current count value of the selected counters will be latched

1 Current count will not be latched

4 Latch Status of Selected Counters – R/W.

0 Status of the selected counters will be latched

1 Status will not be latched

3 Counter 2 Select – R/W. When set to 1, Counter 2 count and/or status will be latched

2 Counter 1 Select – R/W. When set to 1, Counter 1 count and/or status will be latched

1 Counter 0 Select – R/W. When set to 1, Counter 0 count and/or status will be latched.

0 Reserved. Must be 0.

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4.23.3 Counter Latch Command

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The Counter Latch Command latches the current count value at the time the command is received. This command is

used to insure that the count read from the counter is accurate. The count value is then read from each counter's

count register through the Counter Ports Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for

counter 2). The count must be read according to the programmed format, i.e. if the counter is programmed for two

byte counts then two bytes must be read. The two bytes do not have to be read one right after the other (read, write,

or programming operations for other counters may be inserted between the reads). If a counter is latched once and

then latched again before the count is read, the second Counter Latch Command is ignored.

Bit Description

7:6 Counter Selection – R/W. These bits select the counter for latching. If 11 is written, then the write is

interpreted as a read back command.

00 Counter 0

01 Counter 1

10 Counter 2

11 Read Back Command select

5:4 Counter Latch Command – R/W. When bits[5:4] = 00, the Counter Latch Command is selected during a

write to the Timer Control Word Register. Following the Counter Latch Command, I/O reads from the

selected counter’s I/O address produce the current latched count.

3:0 Reserved. Must be 0.

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4.23.4 Interval Timer Status Byte Format Register,

A=40 (Counter 1), 41 (Counter 2), 42 (Counter 3), R=xx

Each counter's status byte can be read following a Read Back Command. If latch status is chosen (bit 4 = 0, Read

Back Command) as a read back option for a given counter, the next read from the counter's Counter Access Ports

Register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. The status byte returns

the following:

Bit Description

7 Counter OUT Pin State – R/W. When this bit is a 1, the OUT pin of the counter is also a 1. When this bit

is a 0, the OUT pin of the counter is also a 0.

6 Count Register Status – R/W. This bit indicates when the last count written to the Count Register (CR)

has been loaded into the counting element (CE). The exact time this happens depends on the counter

mode, but until the count is loaded into the counting element (CE), the count value will be incorrect.

0 Count has been transferred from CR to CE and is available for reading.

1 Null Count. Count has not been transferred from CR to CE and is not yet available for

reading.

5:4 Read/Write Selection Status – R/W. These reflect the read/write selection made through bits[5:4] of the

Control Register. The binary codes returned during the status read match the codes used to program the

counter read/write selection.

00 Counter Latch Command

01 Read/Write Least Significant Byte (LSB)

10 Read/Write Most Significant Byte (MSB)

11 Read/Write LSB then MSB

3:1 Mode Selection Status – R/W. These bits return the counter mode programming. The binary code

returned matches the code used to program the counter mode, as listed under the bit function above.

000 0 Out signal on end of count ( = 0)

001 1 Hardware retriggerable one-shot

x10 2 Rate generator (divide by n counter)

x11 3 Square wave output

100 4 Software triggered strobe

101 5 Hardware triggered strobe

0 Countdown Type Status – R/W. This bit reflects the current countdown type; ether 0 for binary

countdown or a 1 for binary coded decimal (BCD) countdown.

140 Subject to Change Advance Information


4.23.5 Counter Access Ports Register,

A=40 (Counter 1), 41 (Counter 2), 42 (Counter 3), R=xx

Bit Description

R

7:0 Counter Port – R/W. Each counter port address is used to program the 16-bit Count Register. The order

of programming, either LSB only, MSB only, or LSB then MSB, is defined with the Interval Counter

Control Register at port 43h. The counter port is also used to read the current count from the Count

Register, and return the status of the counter programming following a Read Back Command.

4.24 8259 Compatible Interrupt Controller I/O Registers

The interrupt controller registers are located at 20h and 21h for the master controller (IRQ0 - 7), and at A0h and A1h

for the slave controller (IRQ8 - 13). These registers have multiple functions, depending upon the data written to

them. Table 12 is a description of the different register possibilities for each address:

Table 12: Interrupt Controller Register Functions

Port Register Name/Function Default Value Type

20h Master PIC ICW1 Initialization. Command Word 1 Register Undefined Write Only

Master PIC OCW2 Operational Control Word 2 Register 001XXXXXb Write Only

Master PIC OCW3 Operational Control Word 3 Register X01XXX10b Read/Write

21h Master PIC ICW2 Initialization. Command Word 2 Register Undefined Write Only

Master PIC ICW3 Initialization. Command Word 3 Register Undefined Write Only

Master PIC ICW4 Initialization. Command Word 4 Register 01h Write Only

Master PIC OCW1 Operational Control Word 1 Register 00h Read/Write

A0h Slave PIC ICW1 Initialization. Command Word 1 Register Undefined Write Only

Slave PIC OCW2 Operational Control Word 2 Register 001XXXXXb Write Only

Slave PIC OCW3 Operational Control Word 3 Register X01XXX10b Read/Write

A1h Slave PIC ICW2 Initialization. Command Word 2 Register Undefined Write Only

Slave PIC ICW3 Initialization. Command Word 3 Register Undefined Write Only

Slave PIC ICW4 Initialization. Command Word 4 Register 01h Write Only

Slave PIC OCW1 Operational Control Word 1 Register 00h Read/Write

4D0h Master PIC Edge/Level Triggered Register 00h Read/Write

4D1h Slave PIC Edge/Level Triggered Register 00h Read/Write

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4.24.1 ICW1 - Initialization Command Word 1 Register: A=20 (Master), A0 (Slave),

R=xx

A write to Initialization Command Word 1 starts the interrupt controller initialization sequence, during which the

following occurs:

1. The Interrupt Mask Register is cleared.

2. IRQ7 input is assigned priority 7.

3. The slave mode address is set to 7.

4. Special Mask Mode is cleared and Status Read is set to IRR.

Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to complete the initialization

sequence.

Bit Description

7:5 ICW/OCW Select – WO. These bits are MCS-85 specific, and not needed. Should be programmed to

“000”

4 ICW/OCW Select – WO. This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4

sequence.

3 Edge/Level Bank Select (LTIM) – WO. Disabled. Replaced by the edge/level triggered control registers

(ELCR).

2 ADI – WO. Ignored for the 82600. Should be programmed to 0.

1 SNGL – Single or Cascade – WO. Must be programmed to a 0 to indicate two controllers operating in

cascade mode.

0 ICW4 Write Required (IC4) – WO. This bit must be programmed to a 1 to indicate that ICW4 needs to

be programmed.

142 Subject to Change Advance Information


4.24.2 ICW2 - Initialization Command Word 2 Register: A=21 (Master), A1 (Slave),

R=xx

R

ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address.

The value programmed in bits [7:3] is used by the local processor to define the base address in the interrupt vector

table for the interrupt routines associated with each IRQ input on the controller. Typical ISA ICW2 values are 08h for

the master controller and 70h for the slave controller.

Bit Description

7:3 Interrupt Vector Base Address – WO. Bits [7:3] define the base address in the interrupt vector table for

the interrupt routines associated with each interrupt request input.

2:0 Interrupt Request Level – WO. When writing ICW2, these bits should all be 0. During an interrupt

acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be

serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the

second INTA# cycle. The code is a three bit binary code:

Code Master Interrupt Slave Interrupt

000 IRQ0 IRQ8

001 IRQ1 IRQ9

010 IRQ2 IRQ10

011 IRQ3 IRQ11

100 IRQ4 IRQ12

101 IRQ5 IRQ13

110 IRQ6 IRQ14

111 IRQ7 IRQ15

4.24.3 ICW3 - Master Controller Initialization Command Word 3 Register: A=21, R=xx

Bit Description

7:3 Reserved. These bits must be programmed to zero.

2 Cascaded Interrupt Controller IRQ Connection – WO. This bit must always be programmed to a 1. This

bit indicates that the slave controller is cascaded into IRQ2 of the master controller. When IRQ8#-IRQ15

is asserted, it goes through the slave controller’s priority resolver. The slave controller’s INTR output

goes into IRQ2 of the master. IRQ2 then goes through the master controller’s priority solver. If it wins,

the INTR signal is asserted to the local processor, and the returning interrupt acknowledge returns the

interrupt vector for the slave controller.

1:0 Reserved. These bits must be programmed to zero.

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4.24.4 ICW3 - Slave Controller Initialization Command Word 3 Register: A=A1, R=xx

Bit Description

7:3 Reserved. Must be 0.

2:0 Slave Identification Code – WO. These bits are compared against the slave identification code broadcast

by the master controller from the trailing edge of the first internal INTA# pulse to the trailing edge of the

second internal INTA# pulse. These bits must be programmed to 02h to match the code broadcast by the

master controller. When 02h is broadcast by the master controller during the INTA# sequence, the slave

controller assumes responsibility for broadcasting the interrupt vector.

4.24.5 ICW4 - Initialization Command Word 4 Register: A=21 (Master), A1 (Slave),

R=01

Bit Description

7:5 Reserved. Must be 0.

4 SFNM - Special Fully Nested Mode – WO. Should normally be disabled by writing a 0 to this bit. If SFNM

= 1, the special fully nested mode is programmed.

3 Buffered Mode (BUF) – WO. Must be programmed to 0 for the 82600. This is non-buffered mode.

2 Master/Slave in Buffered Mode – WO. Not used. Should always be programmed to 0.

1 Automatic End of Interrupt (AEOI) – WO. This bit should normally be programmed to 0. This is the

normal end of interrupt. If this bit is 1, the automatic end of interrupt mode is programmed.

0 Microprocessor Mode – WO. This bit must be programmed to 1 to indicate that the controller is operating

in an Intel Architecture-based system. Programming this bit to 0 will result in improper controller

operation.

4.24.6 OCW1 - Operational Control Word 1 (Interrupt Mask) Register:

A=21 (Master), A1 (Slave), R=00

OCW1 sets and clears the mask bits in the Interrupt Mask Register (IMR). Each interrupt request line may be

selectively masked or unmasked any time after initialization. The IMR stores the interrupt line mask bits. The IMR

operates on the IRR. Masking of a higher priority input does not affect the interrupt request lines of lower priority

inputs. Unlike status reads of the ISR and IRR, for reading the IMR, no OCW3 is needed. The output data bus

contains the IMR when an I/O read is active and the I/O address is 021h or 0A1h (OCW1). All writes to OCW1 must

occur following the ICW1-ICW4 initialization sequence, since the same I/O ports are used for OCW1, ICW2, ICW3

and ICW4.

Bit Description

7:0 Interrupt Request Mask – R/W. When a 1 is written to any bit in this register, the corresponding IRQ

line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is cleared,

and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master controller

will also mask the interrupt requests from the slave controller.

144 Subject to Change Advance Information


4.24.7 OCW2 - Operational Control Word 2 Register: A=20 (Master), A0 (Slave),

R=001XXXXXb

R

OCW2 controls both the Rotate Mode and the End of Interrupt Mode. Following a hardware reset or ICW

initialization, the controller enters the fully nested mode of operation. Non-specific EOI without rotation is the default.

Both rotation mode and specific EOI mode are disabled following initialization.

Bit Description

7:5 Rotate and EOI Codes – WO. (R, SL, EOI) - These three bits control the Rotate and End of Interrupt

modes and combinations of the two. The functions defined by the bit combinations are:.

*L0 - L2 Are Used

[7:5] Function

000 Rotate in Auto EOI Mode (Clear)

001 Non-specific EOI command

010 No Operation

011 Specific EOI Command

100 Rotate in Auto EOI Mode (Set)

101 Rotate on Non-Specific EOI Command

110 *Set Priority Command

111 *Rotate on Specific EOI Command

4:3 OCW2 Select – WO. When selecting OCW2, bits [4:3] must be programmed to 00.

2:0 Interrupt Level Select (L2, L1, L0) – WO. L2, L1, and L0 determine the interrupt level acted upon when

the SL bit is active. When the SL bit is inactive, these bits do not have a defined function; programming

L2, L1 and L0 to 0 is sufficient in this case.

Bits Interrupt Level Bits Interrupt Level

000 IRQ0/8 100 IRQ4/12

001 IRQ1/9 101 IRQ5/13

010 IRQ2/10 110 IRQ6/14

011 IRQ3/11 111 IRQ7/15

Advance Information Subject to Change 145


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4.24.8 OCW3 - Operational Control Word 3 Register: A=20 (Master), A0 (Slave),

R=X01XXX10b

Bit Description

7 Reserved. Must be 0.

6 ESMM - Enable Special Mask Mode – R/W. If this bit is set, The Special Mask Mode bit can be used by

an interrupt service routine to dynamically alter the system priority structure while the routine is

executing, through selective enabling/disabling of the other channel's mask bits.

5 SMM - Special Mask Mode – R/W. When ESMM = 1, the SMM bit is enabled to set or reset the Special

Mask Mode. When ESMM = 0, the SMM bit becomes a "don't care".

4:3 OCW3 Select – R/W. When selecting OCW3, bits [4:3] must be programmed to 01.

2 Poll Mode Command – R/W. When disabled ( = 0), poll command is not issued. When enabled, the next

I/O read to the interrupt controller is treated as an interrupt acknowledge cycle. An encoded byte is

driven onto the data bus, representing the highest priority level requesting service.

1:0 Register Read Command – R/W. These bits provide control for reading the In-Service Register (ISR) and

the Interrupt Request Register (IRR). When bit 1 = 0, bit 0 will not affect the register read selection. When

bit 1 = 1, bit 0 selects the register status returned following an OCW3 read. If bit 0 = 0, the IRR will be

read. If bit 0 = 1, the ISR will be read. Following ICW initialization, the default OCW3 port address read

will be "read IRR". To retain the current selection (read ISR or read IRR), always write a 0 to bit 1 when

programming this register. The selected register can be read repeatedly without reprogramming OCW3.

To select a new status register, OCW3 must be reprogrammed prior to attempting the read.

[1:0] Function

00 No Action

01 No Action

10 Read IRQ Register

11 Read IS Register

146 Subject to Change Advance Information


4.24.9 ELCR1 - Master Controller Edge/Level Triggered Register: A=4D0, R=00

The addressing used for this register is a standard I/O address, not an offset.

R

In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the

interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat timer (IRQ0), and the keyboard

controller (IRQ1), cannot be put into level mode.

Bit Description

7 IRQ7 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

6 IRQ6 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

5 IRQ5 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

4 IRQ4 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

3 IRQ3 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

2:0 Reserved. Must be 0.

4.24.10 ELCR2 - Slave Controller Edge/Level Triggered Register: A=4D1, R=00

The addressing used for this register is a standard I/O address, not an offset

In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the

interrupt is recognized by a high level. The real time clock, IRQ8# cannot be programmed for level mode.

Bit Description

7 IRQ15 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

6 IRQ14 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

5 IRQ13 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

4 IRQ12 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

3 IRQ11 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

2 IRQ10 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

1 IRQ9 ECL – R/W. 0 = Edge Triggered mode. 1 = Level Triggered mode.

0 Reserved. Must be 0.

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4.25 8237 Compatible DMA I/O Registers

DMA Overview

The 82600 DMA circuitry incorporates the functionality of two 8237 DMA controllers with seven independently

programmable channels (Channels 0-3 and Channels 5-7). DMA Channel 4 is used to cascade the two controllers

together: Channels 0-3 are cascaded onto channel 4. The DMA controller is used for PC/PCI DMAs. To use the

DMA controller, the Enable PC/PCI DMA Support bit must be set in the Miscellaneous Function Enable register.

DDMA is not supported.

The main features of the 82600 DMA controller are:

? Channels 0-3 provide 8-bit, count-by-bytes transfers.

? Channels 5-7 provide 16-bit, count-by-words transfers.

? 24-bit addressing. Each channel includes a 16-bit ISA-compatible Current Address Register (CAR) which

holds the 16 least-significant bits, and an ISA Compatible Page Register, which contains the eight next most

significant bits of address.

? Auto-initialization following a DMA termination.

The DMA controller has registers that are fixed in the lower 64 KB of I/O space.

Table 13. 8237 Compatible DMA Register Descriptions

Port Alias Register Name/Function Default Type

00h Channel 0 DMA Base & Current Address Register Undefined Read/Write

01h Channel 0 DMA Base & Current Count Register Undefined Read/Write

02h Channel 1 DMA Base & Current Address Register Undefined Read/Write

03h Channel 1 DMA Base & Current Count Register Undefined Read/Write

04h Channel 2 DMA Base & Current Address Register Undefined Read/Write

05h Channel 2 DMA Base & Current Count Register Undefined Read/Write

06h Channel 3 DMA Base & Current Address Register Undefined Read/Write

07h Channel 3 DMA Base & Current Count Register Undefined Read/Write

08h Channel 0-3 DMA Command Register 00h Write Only

Channel 0-3 DMA Status Register 00h Read Only

09h Channel 0-3 DMA Request Register 000000XXb Write Only

0Ah Channel 0-3 DMA Write Single Mask Register 000001XXb Write Only

0Bh Channel 0-3 DMA Channel Mode Register 000000XXb Write Only

0Ch Channel 0-3 DMA Clear Byte Pointer Register Undefined Write Only

0Dh Channel 0-3 DMA Master Clear Register Undefined Write Only

148 Subject to Change Advance Information


Port Alias Register Name/Function Default Type

0Eh Channel 0-3 DMA Clear Mask Register Undefined Write Only

0Fh Channel 0-3 DMA Write All Mask Register 01h Read/Write

80h Reserved Page Register Undefined Read/Write

81h Channel 2 DMA Memory Low Page Register Undefined Read/Write

82h - Channel 3 DMA Memory Low Page Register Undefined Read/Write

83h Channel 1 DMA Memory Low Page Register Undefined Read/Write

84h - 86h Reserved Page Registers Undefined Read/Write

87h Channel 0 DMA Memory Low Page Register Undefined Read/Write

88h Reserved Page Register Undefined Read/Write

89h Channel 6 DMA Memory Low Page Register Undefined Read/Write

8Ah Channel 7 DMA Memory Low Page Register Undefined Read/Write

8Bh Channel 5 DMA Memory Low Page Register Undefined Read/Write

8Ch - 8Eh Reserved Page Registers Undefined Read/Write

8Fh Refresh Low Page Register Undefined Read/Write

C0h C1h Channel 4 DMA Base & Current Address Register Undefined Read/Write

C2h C3h Channel 4 DMA Base & Current Count Register Undefined Read/Write

C4h C5h Channel 5 DMA Base & Current Address Register Undefined Read/Write

C6h C7h Channel 5 DMA Base & Current Count Register Undefined Read/Write

C8h C9h Channel 6 DMA Base & Current Address Register Undefined Read/Write

CAh CBh Channel 6 DMA Base & Current Count Register Undefined Read/Write

CCh CDh Channel 7 DMA Base & Current Address Register Undefined Read/Write

CEh CFh Channel 7 DMA Base & Current Count Register Undefined Read/Write

D0h D1h Channel 4-7 DMA Command Register 00h Write Only

Channel 4-7 DMA Status Register 00h Read Only

D2h D3h Channel 4-7 DMA Request Register 000000XXb Write Only

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Advance Information Subject to Change 149


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Port Alias Register Name/Function Default Type

D4h D5h Channel 4-7 DMA Write Single Mask Register 000001XXb Write Only

D6h D7h Channel 4-7 DMA Channel Mode Register 000000XXb Write Only

D8h D9h Channel 4-7 DMA Clear Byte Pointer Register Undefined Write Only

DAh DBh Channel 4-7 DMA Master Clear Register Undefined Write Only

DCh DDh Channel 4-7 DMA Clear Mask Register Undefined Write Only

DEh DFh Channel 4-7 DMA Write All Mask Register 01h Read/Write

4.25.1 DMA Base and Current Address Registers

Address : Ch. #0: 00h Ch. #1: 02h Ch. #2: 04h Ch. #3: 06h Ch. #5 C4h

Ch. #6: C8h Ch. #7: CCh

R=xxxx

This register determines the address for the transfers to be performed. The address specified points to two separate

registers. On writes, the value is stored in the Base Address register and copied to the Current Address register. On

reads, the value is returned from the Current Address register.

The address increments/decrements in the Current Address register after each transfer, depending on the mode of

the transfer. If the channel is in auto-initialize mode, the Current Address register will be reloaded from the Base

Address register after a terminal count is generated.

For transfers to/from a 16-bit slave (channel’s 5-7), the address is shifted left one bit location. Bit 15 will be shifted

out. Therefore, if bit 15 was a 1, it will be lost.

The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop. Before

accessing an address register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first

Bit Description

15:0 Base and Current Address - R/W. These bits represent address bits [15:0] used when forming he 24-bit

address for DMA transfers.

150 Subject to Change Advance Information


4.25.2 DMA Base and Current Count Registers

Address: Ch. #0: 01h Ch. #1: 03h Ch. #2: 05h Ch. #3: 07h Ch. #5 C6h

Ch. #6: CAh Ch. #7: Ceh

R=xxxx

R

This register determines the number of transfers to be performed. The address specified points to two separate

registers. On writes, the value is stored in the Base Count register and copied to the Current Count register. On

reads, the value is returned from the Current Count register.

The actual number of transfers is one more than the number programmed in the Base Count Register (i.e.,

programming a count of 4h results in 5 transfers). The count is decremented in the Current Count register after each

transfer. When the value in the register rolls from zero to FFFF, a terminal count is generated. If the channel is in

auto-initialize mode, the Current Count register will be reloaded from the Base Count register after a terminal count is

generated.

For transfers to/from an 8-bit slave (channel’s 0-3), the count register indicates the number of bytes to be transferred.

For transfers to/from a 16-bit slave (channel’s 5-7), the count register indicates the number of words to be transferred.

The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop. Before

accessing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first.

Bit Description

15:0 Base and Current Count – R/W.

4.25.3 DMA Memory Low Page Registers

Address: Ch. #0: 87h Ch. #1: 83h Ch. #2: 81h Ch. #3: 82h Ch. #5 8Bh

Ch. #6: 89h Ch. #7: 8Ah

R=xx

Bit Description

7:0 DMA Low Page (ISA Address bits [23:16]) – R/W. This register works in conjunction with the DMA

controller's Current Address Register to define the complete 24-bit address for the DMA channel. This

register remains static throughout the DMA transfer.

Advance Information Subject to Change 151


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4.25.4 DMA Command Register

Address: Ch. #0-3: 08h, Ch. #4-7: D0h

R=00

Bit Description

7:5 Reserved. Must be 0.

4 DMA Group Arbitration Priority – WO. Each channel group is individually assigned either fixed or

rotating arbitration priority. At part reset, each group is initialized in fixed priority. Writing a 0 to bit 4

assigns fixed priority to the channel group, while writing a 1 assigns rotating priority to the group.

3 Reserved: Must be 0

2 DMA Channel Group Enable – WO. Writing a 1 to this bit disables the DMA channel group, while

writing a 0 to this bit enables the DMA channel group. Both channel groups are enabled following part

reset. Disabling channel group 4-7 also disables channel group 0-3, which is cascaded through channel 4.

1:0 Reserved. Must be 0.

4.25.5 DMA Status Register

Address: Ch. #0-3: 08h, Ch. #4-7: D0h

R=00

Bit Description

7:4 Channel Request Status – RO. When a valid DMA request is pending for a channel, the corresponding

bit is set to 1. When a DMA request is not pending for a particular channel, the corresponding bit is set

to 0. The source of the DREQ may be hardware or a software request. Note that channel 4 is the cascade

channel, so the request status of channel 4 is irrelevant.

Bit Channel

4 0

5 1 (5)

6 2 (6)

7 3 (7)

3:0 Channel Terminal Count Status – RO. When a channel reaches terminal count (TC), its status bit is set

to 1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for cascade, so the

TC bit response for channel 4 is irrelevant:

Bit Channel

0 0

1 1 (5)

2 2 (6)

3 3 (7)

152 Subject to Change Advance Information


4.25.6 DMA Request Register

Address: Ch. #0-3: 09h, Ch. #4-7: D2h

R=000000XXb

R

The Request Register is used by software to initiate a DMA request. The DMA responds to the software request as

though DREQx is asserted. These requests are non-maskable and subject to prioritization by the priority encoder

network. For a software request, the channel must be in Block Mode. The Request Register status for DMA1 and

DMA2 is output on bits [7:4] of a Status Register read.

Bit Description

7:3 Reserved. Must be 0

2 DMA Channel Service Request – WO. Writing a 0 to this bit resets the individual software DMA

channel request bit. Generation of a Terminal Count also sets this bit to 0. Writing a 1 to this bit sets the

request bit. The request bit for each DMA channel is reset to 0 upon 82600 reset or a Master Clear. The

channel is selected through bits[1:0] so only one channel can be programmed at a time.

1:0 DMA Channel Select – WO. Bits [1:0] select the DMA Request Register to program.

Bits[1:0] Channel

00 0

01 1 (5)

10 2 (6)

11 3 (7)

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4.25.7 DMA Write Single Mask Register

Address: Ch. #0-3: 0Ah, Ch. #4-7: D4h

R=000001XXb

A channel’s mask bit is automatically set when the Current Byte/Word Count Register reaches terminal count (unless

the channel is programmed for autoinitialization). Setting the entire register disables all DMA requests until a clear

mask register instruction allows them to occur. This instruction format is similar to the format used with the DMA

Request Register. Masking DMA channel 4 (DMA controller 2, channel 0) also masks DMA channels [3:0].

Bit Description

7:3 Reserved. Must be 0.

2 Channel Mask Select – WO. When this bit is set to a 1, DREQ is disabled for the selected channel.

When this bit is set to a 0, DREQ is enabled for the selected channel. The channel is selected through

bits [1:0] so only one channel can be masked / unmasked at a time.

1:0 DMA Channel Select – WO. These bits select the DMA Single Mask Register to program.

Bits[1:0] Channel

00 0 (4)

01 1 (5)

10 2 (6)

11 3 (7)

154 Subject to Change Advance Information


4.25.8 DMA Channel Mode Register

Address: Ch. #0-3: 0Bh, Ch. #4-7: D6h

R=000000XXb

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Each channel has a 6 bit Channel Mode Register. The Channel Mode Registers provide control over DMA transfer

type, Transfer mode, address increment/decrement, and autoinitialization.

Bit Description

7:6 DMA Transfer Mode – WO. Each DMA channel can be programmed in one of four different modes:

Bits[7:6] Transfer Mode

00 Demand mode

01 Single mode

10 Block mode

11 Cascade mode

5 Address Increment/Decrement Select – WO. This bit controls address increment/decrement during

DMA transfers. When set to 0, address increment is selected. When set to 1, address decrement is

selected. Address increment is the default after part reset or Master Clear.

4 Autoinitialize Enable – WO. When this bit is a 1, the DMA restores the Base Address and Count

registers to the current registers following a terminal count (TC). When this bit is a 0, the autoinitialize

feature is disabled and DMA transfers terminate on a terminal count. A part reset or Master Clear

disables autoinitialization.

3:2 DMA Transfer Type – WO. These bits represent the direction of the DMA transfer. When the channel

is programmed for cascade mode, (bits[7:6] = “11”) the transfer type is irrelevant.

Bits[3:2] Transfer Type

00 Verify - No I/O or memory strobes generated

01 Write - Data transfered from the I/O devices to memory

10 Read - Data transfered from memory to the I/O device

11 Illegal

1:0 DMA Channel Select – WO. These bits select the DMA Channel Mode Register that will be written by

bits [7:2].

Bits[1:0] Channel

00 0 (4)

01 1 (5)

10 2 (6)

11 3 (7)

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4.25.9 DMA Clear Byte Pointer Register

Address: Ch. #0-3: 0Ch, Ch. #4-7: D8h

R=xx

Bit Description

7:0 Clear Byte Pointer – WO. No specific pattern. Command enabled with a write to the I/O port address.

Writing to this register initializes the byte pointer flip/flop to a known state. It clears the internal latch

used to address the upper or lower byte of the 16-bit Address and Word Count Registers. The latch is

also cleared by 82600 reset and by the Master Clear command. This command precedes the first access to

a 16 bit DMA controller register. The first access to a 16 bit register will then access the significant byte,

and the second access automatically accesses the most significant byte.

4.25.10 DMA Master Clear Register

Address: Ch. #0-3: 0Dh, Ch. #4-7: Dah

R=xx

Bit Description

7:0 Master Clear – WO. No specific pattern. Enabled with a write to the port. This has the same effect as

the hardware Reset. The Command, Status, Request, and Byte Pointer flip/flop registers are cleared and

the Mask Register is set.

4.25.11 DMA Clear Mask Register

Address: Ch. #0-3: 0Eh, Ch. #4-7: DCh

R=xx

Bit Description

7:0 Clear Mask Register – WO. No specific pattern. Command enabled with a write to the port. This

command clears the mask bits of all 4 channels, enabling them to accept DMA requests.

156 Subject to Change Advance Information


4.25.12 DMA Write All Mask Register

Address: Ch. #0-3: 0Fh, Ch. #4-7: Deh

R=01

Bit Description

7:4 Reserved. Must be 0.

R

3:0 Channel Mask Bits – R/W. Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the

bit(s) to a 0 enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon 82600 reset or Master Clear.

When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status.

0 Channel 0 (4)

1 Channel 1 (5)

2 Channel 2 (6)

3 Channel 3 (7)

This register permits all four channels to be simultaneously enabled/disabled instead of

enabling/disabling each channel individually, as is the case with the Mask Register - Write Single Mask

Bit. In addition, this register has a read path to allow the status of the channel mask bits to be read. A

channel's mask bit is automatically set to 1 when the Current Byte/Word Count Register reaches terminal

count (unless the channel is in auto-initialization mode).

Note: Disabling channel 4 also disables channels 0-3 due to the cascade of channel’s 0 - 3 through

channel 4. Masking DMA controller 2 with a write to port DE also masks DREQ assertions from DMA

controller 1.

4.26 RTC I/O Registers

The RTC internal registers and RAM are organized as two banks of 128 bytes each, called the standard and extended

banks. The first 14 bytes of the standard bank contain the RTC time and date information along with four registers, A

- D, that are used for configuration of the RTC. The extended bank contains a full 128 bytes of battery backed

SRAM, and will be accessible even when the RTC module is disabled (via the RTC configuration register). Registers

A-D do not physically exist in the RAM.

All data movement between the host CPU and the real-time clock is done through registers mapped to the standard

I/O space. The register map appears in Table 14.

Table 14: RTC I/O Registers

I/O Locations If U128E bit = 0 Function

70h and 74h Also alias to 72h and 76h Real-Time Clock (Standard RAM) Index Register

71h and 75h Also alias to 73h and 77h Real-Time Clock (Standard RAM) Target Register

72h and 76h Extended RAM Index Register (if enabled)

73h and 77h Extended RAM Target Register (if enabled)

Advance Information Subject to Change 157


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I/O locations 70h and 71h are the standard ISA location for the real-time clock. The map for this bank is shown in

Table 15. Locations 72h and 73h are for accessing the extended RAM. The extended RAM bank is also accessed

using an indexed scheme. I/O address 72h is used as the address pointer and I/O address 73h is used as the data

register. Index addresses above 127h are not valid. If the extended RAM is not needed, it may be disabled

Note: Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When writing to these addresses,

software must first read the value, and then write the same value for bit 7 during the sequential address write.

4.26.1 RTC Indexed Registers

The RTC contains two sets of indexed registers that are accessed using the two separate Index and Target registers

(70/71h or 72/73h), as shown in Table 15.

Table 15: RTC (Standard) RAM Bank

Index Name

00h Seconds

01h Seconds Alarm.

02h Minutes

03h Minutes Alarm

04h Hours

05h Hours Alarm

06h Day of Week

07h Day of Month

08h Month

09h Year

0Ah Register A

0Bh Register B

0Ch Register C

0Dh Register D

0Eh - 7Fh 114 Bytes of User RAM

158 Subject to Change Advance Information


4.26.2 Configuration/Control Registers

4.26.2.1 Register A, RTC Index = 0A

R

This register is used for general configuration of the RTC functions. None of the bits are affected by any reset

signal.

Bit Description

7 UPDATE IN PROGRESS (UIP) – R/W. This bit may be monitored as a status flag. When asserted as a 1,

the update is soon to occur or is in progress. If 0, the update cycle will not start for at least 244 µs. The

time, calendar, and alarm information in RAM is always available when the UIP bit is 0.

6:4 Division Chain Select DV[2:0] – R/W. These three bits control the divider chain for the oscillator, and are

not affected by any reset signal. DV[2] corresponds to bit 6.

DV2 DV1 DV0 Function

0 1 X Normal Operation

1 X X Divider Reset

0 0 1 Invalid

0 0 0 Invalid

3:0 Rate Select RS[3:0] – R/W. Selects one of 13 taps of the 15 stage divider chain. The selected tap can

generate a periodic interrupt if the PIE bit is set in Register B. Otherwise this tap will set the PF flag of

Register C. If the periodic interrupt is not to be used, these bits should all be set to zero. RS3 corresponds

to bit 3.

RS3 RS2 RS1 RS0 Periodic Rate

0 0 0 0 none

0 0 0 1 3.90625 ms

0 0 1 0 7.8125 ms

0 0 1 1 122.070 ?s

0 1 0 0 244.141 ?s

0 1 0 1 488.281 ?s

0 1 1 0 976.5625?s

0 1 1 1 1.953125 ms

1 0 0 0 3.90625 ms

1 0 0 1 7.8125 ms

1 0 1 0 15.625 ms

1 0 1 1 31.25 ms

1 1 0 0 62.5 ms

1 1 0 1 125 ms

1 1 1 0 250 ms

1 1 1 1 500 ms

Advance Information Subject to Change 159


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4.26.2.2 Register B - General Configuration, RTC Index = 0B, R=X0000XXXb

Bit Description

7 SET - Update Cycle Inhibit – R/W. Enables/Inhibits the update cycles. When SET is 0, update cycle

occurs normally once each second. If set to one, a current update cycle will abort and subsequent update

cycles will not occur until SET is returned to zero. When set is one, the BIOS may initialize time and

calendar bytes safely. This bit is not affected by any reset signal.

6 Periodic Interrupt Enable (PIE) – R/W. If set to one, the Periodic Interrupt Enable (PIE) bit allows an

interrupt to occur with a time base set with the RS bits of register A. This bit is cleared during a resume.

5 Alarm Interrupt Enable (AIE) – R/W. If set to one, the Alarm Interrupt Enable (AIE) bit allows an interrupt

to occur when the AF is one as set from an alarm match from the update cycle. An alarm can occur once a

second, one an hour, once a day, or one a month. This bit is cleared during a resume.

4 Update-ended Interrupt Enable (UIE) – R/W. If set to one, the Update-ended Interrupt Enable (UIE) bit

allows an interrupt to occur when the update cycle ends. This bit is cleared during a resume.

3 Square Wave Enable (SQWE) – R/W. The Square Wave Enable bit serves no function in this device, yet

is left in this register bank to provide compatibility with the Motorola 146818B. There is not SQW pin on

this device. This bit is cleared during a resume.

2 Data Mode (DM) – R/W. The Data Mode (DM) bit specifies either binary or BCD data representation. A

one denotes binary, and zero denotes BCD. This bit is not affected any reset signal.

1 Hour Format (HF) – R/W. This bit indicates the hour byte format. If one, twenty-four hour mode is

selected. If zero, twelve-hour mode is selected. In twelve hour mode, the seventh bit represents AM as

zero and PM as one. This bit is not affected by any other reset signal.

0 Daylight Savings Enable (DSE) – R/W. The Daylight Savings Enable bit triggers two special hour updates

per year when set to one. One is on the first Sunday in April, where time increments from 1:59:59 AM to

3:00:00 AM. The other is the last Sunday in October when the time first reaches 1:59:59 AM, it is changed

to 1:00:00 AM. The time must increment normally for at least two update cycles (seconds) previous to

these conditions for the time change to occur properly. These special update conditions do not occur

when the DSE bit is set to zero. The days for the hour adjustment are those specified in United States

federal law as of 1987, which is different than previous years. This bit is not affected by any reset signal.

160 Subject to Change Advance Information


4.26.2.3 Register C - Flag Register, RTC Index = 0C, R=00

Writes to Register C have no effect.

Bit Description

R

7 Interrupt Request Flag (IRQF) – R/W. Interrupt Request Flag = PF * PIE + AF * AIE + UF *UFE. This

also causes the CH_IRQ_B signal to be asserted. This bit is cleared upon a resume or a read of Register C.

6 Periodic Interrupt Flag (PF) – R/W. Periodic interrupt Flag will be one when the tap as specified by the RS

bits of register A is one. If no taps are specified, this flag bit will remain at zero. This bit is cleared upon a

resume or a read of Register C.

5 Alarm Flag (AF) – R/W. Alarm Flag will be high after all Alarm values match the current time. This bit is

cleared upon a resume or a read of Register C.

4 Update-ended Flag (UF) – R/W. Updated-ended flag will be high immediately following an update cycle for

each second. The bit is cleared upon a resume or a read of Register C.

3:0 Reserved. Will always report 0.

4.26.2.4 Register D - Flag Register, RTC index = 0D

None of the bits in this register are affected by any reset signal.

Bit Description

7 Valid RAM and Time Bit (VRT) – R/W. The Valid Ram and Time bit is cleared by the RTCPS pin when it

is low. This bit is set to a 1 by hardware after a read to this register occurs with RTCPS=1. This bit is read

only and is not affected by PWRGOOD..

6 Reserved. This bit always returns a 0 and should be set to 0 for write cycles.

5:0 Date Alarm (DA) – R/W. These bits store the date of month alarm value. If set to 000000, then a don’t

care state is assumed. The host must configure the date alarm for these bits to do anything, yet they can

be written at any time. If the date alarm is not enabled, these bits will return zeros to mimic the

functionality of the Motorola 146818B. These bits are not affected by RESET.

Advance Information Subject to Change 161


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5 Functional Description

5.1 High Throughput Data Flow Topology

The flow of data between the various peripherals supported by the 82600 is implemented as a high throughput star

topology. This eliminates the bottlenecks encountered when the LPCI bus must be used to communicate with LPCI

devices and also supports the traffic for communication with the BPCI bus, EIDE disk drive, USB and PC legacy

peripherals. While improving the data communications bandwidth and reducing the latency time for communications

with the LPCI and BPCI buses, the 82600 implementation also permits simultaneous transfers to occur between

various peripherals. For example, the BPCI can be performing a DMA to and from main memory while the local

processor is communicating with a LPCI peripheral. This implementation of independent data interface per peripheral

maximizes system performance, especially in applications requiring the movement of large blocks of data.

5.2 Dual PCI Bridge Capabilities

82600 features control for two PCI buses, a local PCI bus (LPCI) and a backplane PCI bus (BPCI). The interfaces to

these buses are implemented as independent data paths. In this implementation, activity on the BPCI bus does not

cause traffic on the LPCI bus. Since this implementation does not involve a typical PCI-to-PCI bridge, there is no

additional latency for accesses to the BPCI bus.

The 82600 and the local processor always act as the Central Resource on the LPCI bus. Architecturally it can be

viewed as the high-speed private peripheral bus for the processor. The BPCI interface is intended to be connected to

a backplane bus such as Compact PCI. In this configuration, the 82600 shields the LPCI bus and its associated

devices from traffic on the BPCI bus and vice versa. The 82600 can act as a target and as a memory or I/O access

initiator on both PCI buses. The BPCI interface optionally provides address translation for both target (SDRAM) and

host initiated accesses; whereas the LPCI interface always passes addresses “transparently” whether the 82600 is

acting as a target or initiator.

5.2.1 Backplane PCI Modes

The 82600 interface to the BPCI supports two modes of operation, Central Resource and Peripheral Bridge. In the

Central Resource mode the 82600, along with its associated processor and memory, function as the Central Resource

for the CompactPCI bus. The board containing the 82600 in this mode is installed in CompactPCI slot #1 as shown in

Figure 3. In this mode the 82600 responds to interrupts from the BPCI bus and acts as the central arbiter. In the

Peripheral Bridge mode the 82600 interfaces to one BPCI slot and generates interrupts on the BPCI bus. The board

containing the 82600 in this mode is installed in CompactPCI bus slot #2 through slot #8.

Figure 3 CompactPCI Slot Assignments

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When the 82600 is configured as the Central Resource for the BPCI, a virtual transparent PCI-to-PCI (P2P) bridge from

the LPCI bus to the BPCI bus is seen on the LPCI bus (bus #0) as device #1. In this mode, the virtual PCI to PCI

bridge controls whether configuration cycles that are destined for other downstream PCI buses should be routed to

the LPCI bus or to the BPCI bus. In Central Resource mode, the local processor is responsible for configuring both

the LPCI and BPCI buses so the BPCI configuration registers are not accessible from the backplane and the BPCI

IDSEL signal is not used.

When in Central Resource mode, the BPCI bus number is programmable using the Secondary Bus Number (SBN) in

the P2P configuration space registers. Also in this mode, standard configuration cycles will check the bus number

against the SBN and Subordinate Bus Number (SUBN) in the P2P Bridge to determine if the configuration cycle

should be sent to the BPCI or the LPCI bus.

When the 82600 is configured as a Peripheral Bridge on the BPCI, the virtual P2P Bridge registers no longer appear as

a virtual P2P Bridge on the LPCI bus, but instead appears as a non-tranparent P2P bridge. These P2P bridge registers

are still available and may be accessed through the use of the Alternate BPCI Configuration Index and Data

Registers. In this mode, configuration cycles that use the standard Configuration Address and Data accesses will

ignore the P2P bridge registers and will always be sourced to the LPCI bus. Standard memory and I/O transactions

still use the P2P bridge registers to decide whether to direct an access to either the BPCI or LPCI bus. In Peripheral

Bridge mode, the normal BPCI configuration space registers can be accessed from the BPCI bus when IDSEL is

asserted during a type 0 configuration cycle that is initiated by another master on the BPCI bus. Regardless of the

mode of operation, the 82600 will never respond to a type 1 access initiated from the BPCI interface.

When in Peripheral Bridge mode, all standard configuration cycles go to the LPCI bus and alternate configuration

cycles must be used to access the P2P and BPCI Configuration Space Header (CSH) registers. These CSH registers

are always found at bus #0, device#0, and function #0 using the Alternate Configuration Index and Data Register’s

address space.

5.2.2 Backplane PCI Arbiter Modes

To support the capability of the 82600 to function as either the Central Resource or a Peripheral Bridge in a

CompactPCI system, the arbiter for the Backplane PCI has two hardware configuration modes. The arbiter mode is

determined during power-up by the strapping of the MA2 pin and can be read from the POB, Power-On Option Bit

Register.

5.2.2.1 Central Resource Mode

When the MA2 pin is strapped low through an external 1.5K? resistor the 82600 is placed in Central Resource mode.

In this mode the arbiter on the Backplane PCI bus functions as the bus master. The internal PCI bus arbiter supports

8 request and grant signal lines. One pair of these signals is internally routed to the internal PCI bus master while the

remaining 7 pairs go to the 7 BGNT[6:0]# and BREQ[6:0]# signal pins. These external signals support up to 7 external

PCI bus masters on the Backplane PCI bus. See Figure 4.

Advance Information Subject to Change 163


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REQ

Lines

Internal 82600 Logic

Internal 82600

PCI Bus Arbiter

[7]

8 [7:0]

[6:0]

82600

Internal PCI

Bus Master

Figure 4 82600 BPCI Arbiter in Central Resource Mode

GNT

Lines

8 [7:0]

[7]

[6:0]

5.2.2.2 Peripheral Bridge Mode

BGNT[6:0]# Signal Pins

BREQ[6:0]# Signal Pins

BRST# Signal Pin

82600 Device Pins

To BPCI

External Bus

Masters

When the MA2 pin is strapped high through an external 1.5K? resistor the 82600 is placed in Peripheral Bridge

mode. As shown in Figure 5, in this mode the internal arbiter for the Backplane PCI bus is disabled and the

functionality of several 82600 device pins is redefined:

1) The Request and Grant signals to support the internal Backplane PCI bus master are routed to the BREQ0#

and BGNT0# signal pins.

2) The hot swap required functions of ENUM#, LEDOUT and EJECTSTS are supported by the BGNT1#,

BGNT2# and BREQ2# signal pins.

3) The IDSEL configuration select function required to allow the Central Resource to configure the appropriate

82600 registers is routed to the BREG1# signal pin.

When the 82600 is in Peripheral Bridge mode another device on the Backplane PCI bus must provide the functionality

of the Central Resource including central arbitration of requests and grants and generation of individual IDSEL

signals to each device for system configuration.

164 Subject to Change Advance Information


REQ

Lines

BREQ7#

Internal 82600 Logic

Internal 82600

PCI Bus Arbiter

82600

Internal PCI

Bus Master

Figure 5: 82600 in Peripheral Bridge Mode

GNT

Lines

BGNT7#

Tied High

by the

Arbiter

REQ Function

GNT Function

Force Host

Grant

5.2.3 Views of Backplane PCI Bridge Modes

BGNT0# Signal Pin

BREQ0# Signal Pin

BREQ6# Signal Pin

82600 Device Pins

BGNT[6:1]# Signal Pins

BREQ[5:1]# Signal Pins

BRST# Signal Pin

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To BPCI

For software compatibility, the 82600 supports a total of 3 sets of PCI Configuration Space Headers (CSH):

? A “north-bridge-like” LPCI CSH

? A virtual P2P bridge CSH

? A BPCI target bridge CSH. See Figure 6 and Figure 7.

The 82600 P2P CSH provides for two memory windows and one I/O window that reside in the local host’s address

space and that allow the local host to generate accesses to the BPCI. The base and limit configuration registers of the

memory windows must be set to addresses above the top of local SDRAM and below the top 64MB of the 4GB

address space where the flash memory resides. Accesses below the top of SDRAM will either be sequenced to

SDRAM or to the LPCI bus as described in the Local PCI references section and accesses in the top 64MB will be

sequenced to the flash on the SDRAM bus, if configured in this manner.

Figure 6 is a view of PCI configuration space when the 82600 is configured as the Central Resource. In this mode

standard Configuration Address and Data cycles are used to enumerate the CSHs. Note that this is the programmer’s

or register view of the 82600 virtual P2P bridge since the bridge spans from the LPCI bus to the BPCI bus. In the

Advance Information Subject to Change 165


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82600 hardware implementation, actual local host cycles destined for the BPCI bus go directly to the BPCI bus as

directed by the P2P bridge registers without causing traffic on the LPCI bus.

Local

Host

Interface

Standard

Configuration

Accesses

Alternate

Configuration

Accesses

Figure 6: Central Resource View

Local PCI CSH:

Bus 0, Device 0

82600 LPCI configuration

registers are not accessible

from the LPCI bus

Bus #0

Virtual PCI to PCI CSH:

Bus 0, Device 1

BPCI CSH:

only accessible from the

local host

Bus #x

LPCI

Interface

BPCI

Interface

The BPCI bus number, x in Figure 6, in the LPCI bus space is determined by the P2P Secondary Bus Number register.

Figure 7 is a view of PCI configuration space when the 82600 is configured as a Peripheral Bridge on the BPCI bus.

Local

Host

Interface

Standard

Configuration

Accesses

Alternate

Configuration

Accesses

Figure 7: Peripheral Bridge View

Local PCI CSH:

Bus 0, Device 0

Virtual PCI to PCI CSH:

Bus 0, Device 0

BPCI CSH:

IDSEL & Type 0 Access

5.2.4 Backplane PCI Alternate Configuration

Bus #0

Bus #x

LPCI

Interface

BPCI

Interface

The BPCI bus may optionally also be viewed as a separate parallel PCI bus structure through the use of the Alternate

Configuration Index and Data Registers. In this view, the LPCI and BPCI buses can be both treated as bus #0 relative

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to the local host processor, each in their own private PCI bus spaces. For this case, the LPCI Configuration Space

Header (CSH) enumeration is done with the standard Configuration Address and Data registers and the BPCI CSH

enumeration is done using the Alternate Configuration Index and Data Registers. Legacy software that accesses PCI

Configuration Space Headers is not aware of the alternate access mode and will not be able to enumerate the BPCI

bus structure. When configured as a BPCI Peripheral Bridge, legacy bus enumeration of the BPCI is disabled;

however, the alternate bus enumeration is available for use if required. This is an 82600 specific enhanced level of

functionality. In dual PCI bus systems implemented with a conventional PCI-to-PCI bridge only the Central Resource

of the BPCI system would be able to access the BPCI configuration space.

In both Peripheral Bridge and Central Resource mode, the 82600 supports a BPCI non-transparent bridge mode that

can also be accessed using non-legacy software. This allows both BPCI outgoing and incoming addresses to be

translated and aligned to the BPCI address space and the local Host address space, respectively. At power-up, the

default configuration supports a transparent BPCI bridge.

5.3 BPCI Peripheral Bridge Capabilities

When the 82600 is acting as a Peripheral Bridge on the BPCI bus, it can be configured to supply all of the

functionality normally associated with a CompactPCI Peripheral Bridge. All or any part of its local memory can be

configured by another processor in the system acting as the CompactPCI Central Resource to be a part of the BPCI

memory space starting at any legal PCI address boundary. In addition, an expansion ROM Base Address Register

and remapping register are available. Unlike typical Central Resource chipsets, most of the required PCI

configuration registers are not hardwired and may be overwritten from the local bus side. Examples of these registers

are the Class Code, Vendor and Subvendor ID Registers. When the BPCI interface is placed in Peripheral Bridge

mode the IDSEL pin is available for access to the BPCI configuration space registers from the BPCI bus. The BPCI

RST# pin is configured as an input when the 82600 is configured as a Peripheral Bridge and as an output when

configured as the Central Resource. The internal PCI bus arbiter is disabled and one pair of external REQ#/GNT# pins

are configured to request access to the BPCI bus. The 82600 also supports the address remapping of the local host

initiated accesses above the top of SDRAM through four 1GB address windows. This capability allows access to the

entire 4GB PCI address space, even when 2GB of local memory is configured as locally accessible memory. The

HBPCIR register controls this remapping.

When in Peripheral Bridge mode, the 82600 can be configured to generate an interrupt on any of the four BPCI

interrupt lines. The remaining interrupt lines may be used as local level or edge sensitive interrupt inputs. Doorbell

registers are also available for support of both outgoing and incoming interrupts. Finally, local peripherals can be

supported on the LPCI bus without adding a PCI to PCI bridge chip and its associated performance degradation and

configuration issues.

When the 82600 is configured as the Central Resource for the BPCI bus, some of the Peripheral Bridge centric

remapping capabilities are still available. When the 82600 is configured as a Peripheral Bridge, some of the features

may also be used. For example, the PCI memory master and target windowing/ Central Resource centric features may

also be used. For example, BPCI configuration cycles can be generated to interrogate other BPCI peripheral I/O cards

in the system.

5.4 BPCI Target Support

In both Central Resource and Peripheral Bridge modes, the 82600 allows access from the BPCI bus to any SDRAM

bus resident memory. This access is defined in BPCI configuration space through the use of the BAR0, BAR1,

RBAR registers and locally through the MRBAR0, MBAR1, and RRBAR registers. A minimum of 1MB of main

memory up to a maximum of 2 GB can be mapped into the BPCI bus address space starting at any naturally aligned

PCI address boundary. For example, if 4MB out of a total of 32MB of main memory is to be made available in the

BPCI address space, then this 4MB memory may be configured at any 4MB address boundary in the BPCI address

space. In addition, this 4MB of BPCI shared memory could start at any one of eight host address boundaries: 0,

4MB, 8MB, 12MB, 16MB, 20MB, 24MB, and 28MB.

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The BDEVSEL# signal is asserted by the 82600 to claim a BPCI transaction.. As required by the PCI specification, for

the cases that an access is not claimed by the 82600 or any other BPCI agent using either positive or subtractive

decode, the access must be “master aborted” by the BPCI master.

As a BPCI target in either Central Resource or Peripheral Bridge mode, the 82600 does not claim any BPCI initiated I/O

accesses.

When configured as a Peripheral Bridge, BPCI Function 0 Registers 0-0x3F may be accessed using BPCI

configuration cycles with the IDSEL pin asserted. The 82600 always asserts the BDEVSEL# signal with medium

timing.

Before responding with BDEVSEL# to a BPCI memory access, the 82600 will translate accesses that fall within the

enabled BAR regions and will only respond with BDEVSEL# to BPCI memory accesses that its SDRAM interface

claims. BDEVSEL# will not be asserted for any translated address that match a PAM entry that would steer the

access to the LPCI bus. The 82600 cannot be configured as the subtractive decode agent for either PCI bus. A

summary of BPCI and host address space memory maps is shown in Figure 8.

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FFFF_FFFF

RBAR defines

BPCI starting

and ending

addresses

BAR1 Defines

the start and

MRBAR1

defines the

length of this

region

BAR0 Defines

the start and

MRBAR0

defines the

length of this

region

0

Figure 8: Host Address Space Memory Maps

BPCI 32-bit Address Space

General BPCI

Address Space

Region in 82600 SDRAM

defined by RBAR & RRBAR

General BPCI

Address Space

Region in BPCI address

space that is mapped from

host address space by MBL0

General BPCI

Address Space

BDEVSEL is asserted for

the region in 82600

SDRAM defined by

BAR1 & MRBAR1

General BPCI

Address Space

Region in BPCI address

space that is mapped from

host address space by MLB1

General BPCI

Address Space

BDEVSEL is asserted for

the region in 82600

SDRAM defined by

BAR0 & MRBAR0

General BPCI

Address Space

A summary of BPCI target and initiator support is given in Table 16.

Host 32-bit Address Space

82600 Flash or LPCI

Region in 82600 SDRAM

defined by RRBAR

BPCI window 1

Set by P2P MBL0

base and limit register

Region in 82600 SDRAM

defined by MRBAR1

82600 SDRAM

Region in 82600 SDRAM

defined by MRBAR0

82600 SDRAM

Host address space

mapped by

PAM registers

82600 SDRAM

R

0010_0000

000A_0000

Advance Information Subject to Change 169

LPCI

LPCI

BPCI window 0

Set by P2P MBL0

base and limit register

LPCI

0


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Table 16 BPCI Target and Initiator Support

C/BE# Command Target Support Initiator Support

0000 Interrupt Acknowledge No No

0001 Special Cycle No No

0010 I/O read No Yes

0011 I/O write No Yes

0100 reserved No No

0101 reserved No No

0110 Memory Read Yes Yes

0111 Memory Write Yes Yes

1000 reserved No No

1001 reserved No No

1010 Configuration Read Yes (when configured as

an peripheral bridge)

1011 Configuration Write Yes (when configured as an

peripheral bridge)

1100 Memory Read Multiple As Memory Read No

1101 Dual Address cycle No No

1110 Memory Read Line As Memory Read No

1111 Memory Write and Invalidate As Memory Write No

5.5 Doorbell Interrupt Support

When configured as a Peripheral Bridge, the 82600 supports two 32-bit doorbell interrupt registers. Both of these

registers appear in the 82600 BPCI target CSH. The Local to BPCI Interrupt Doorbell Register (LPID) is used by the

local processor to assert an interrupt on the BPCI bus. The PCI to Local Interrupt Doorbell Register (PLID) is used

by the BPCI Central Resource to signal an interrupt to the 82600 and the local processor.

The initial state of both of the doorbell registers is all 0s. A non-zero write to either register causes the

corresponding interrupt to be asserted. The interrupt remains asserted until the appropriate doorbell register is

cleared by writing a 1 to the bit position(s) to be cleared. For the LPID register the interrupt is caused by the local

processor and must be serviced and cleared by the BPCI Central Resource. Conversely, for the PLID register the

interrupt is caused by the BPCI Central Resource and must be serviced and cleared by the local processor.

The 82600 BPCI interface contains 4 interrupt signals, BPIRQ[A:D]#. When configured as a Peripheral Bridge, one of

these 4 signals must be selected to drive interrupts from the 82600 to the Central Resource. This selection is made in

the Interrupt Line/Interrupt Pin Register (ILIP). After the appropriate signal is selected in the ILIP register it becomes

an output to the BPCI bus. The other three interrupt signals are available as utility level sensitive interrupt inputs.

When a non-zero write is made by the local processor to the LPID register, the selected signal will be driven low

(active) to signal the interrupt and remain low until the Central Resource clears the LPID register to all 0s.

When the 82600 receives an interrupt through a Central Resource non-zero write to the PLID register, the interrupt is

steered to the proper interrupt service routine through the embedded 8259A Programmable Interrupt Controller. The

BIRQRC[A:D] register defines the relationship between incoming interrupts on the 4 interrupt lines and the

appropriate 8259A interrupt input when the 82600 is in the Central Resource mode. In the Peripheral Bridge mode this

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Yes


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register must still be configured to steer the incoming PLID generated interrupt. In the Peripheral Bridge mode, the

8259A interrupt input will be generated on the interrupt line configured for the BPIRQ[A:D] line selected to drive

BPCI interrupts in the ILIP register. To avoid conflicts with predefined interrupts, BPCI interrupts are restricted to the

8259A inputs 3-7, 9-12, or 15.

For example, if the 82600 is in Peripheral Bridge mode and is configured with the ILIP register to drive BPCI interrupts

on pin BPIRQC# and the BPIRQCC register assigns BPIRQC# interrupts to 8259A input 5 then, when the 82600

performs a non-zero write to the LPID register the BPIRQC# signal will be driven low (active) and when the Central

Resource performs a non-zero write to the PLID register the 8259A interrupt number 5 will be asserted. These

interrupts remain asserted until the servicing agent writes a 1 to the appropriate bit position in the appropriate

register.

5.6 Hot Swap Friendly Support

When configured as a Peripheral Bridge, the 82600 is CompactPCI Hot Swap Friendly as specified the CompactPCI®

Hot Swap Specification PICMG 2.1 R 1.0 dated May 14, 1999. To support the signal requirements to be Hot Swap

Friendly and conserve device pin count, several BPCI pins that are required only in the Central Resource mode are

redefined. Also, several BPCI pins that are required only in the Central Resource mode and not required in the

Peripheral Bridge mode are available to be redefined as general purpose digital I/O. These pin redefinitions are

described in Table 17.

Table 17 Hot Swap Pin Redefinition

Central Resource Mode Peripheral Bridge Mode

BREQ[6:3}# DI[19:16]

BREQ[2]# EJECTSTS

BREQ[1]# IDSEL

BREQ[0]# GNT#

BGNT[6:3]# DIO[23:20]

BGNT[2]# LEDOUT

BGNT[1]# ENUM#

BGNT[0]# REQ#

In the Peripheral Bridge Mode the intended connection of these pins is:

? DI[19:16] and DIO[23:20] are general purpose digital I/O. They do not connect to the CompactPCI bus.

? EJECTSTS is an input for connection to a faceplate ejector handle micro-switch. The signal convention is

high level = locked/closed.

? IDSEL is an input for connection directly to the CompactPCI backplane. It becomes a chip select for BPCI

configuration read and write transactions.

? GNT# is an input for connection directly to the CompactPCI backplane. This signal indicates that the 82600

has control of the CompactPCI bus.

? LEDOUT is an output for connection to the anode of the blue LED mounted on the faceplate of a

CompactPCI board and is controlled by software.

? ENUM# is an output for connection to the CompactPCI ENUM# pin. This pin signals the Central Resource

that the Peripheral Bridge is ready for initial configuration or is to be removed.

? REQ# is an output for connection directly to the CompactPCI bus. This signal indicates that the 82600 is

requesting control of the CompactPCI bus.

The 82600 also supports the Hot Swap Friendly register requirements. The Hot Swap Control and Status Register is

implemented as the HSC (Hot Swap Capability Register). The Capabilities Pointer is implemented at the location

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required in the CompactPCI Hot Swap Specification and forms the head of the linked list of Control and Status

Registers in the order and format defined in the CompactPCI specification.

The 82600 also supports the other features required for Hot Swap Friendly operation:

? BPCI outputs are 3-stated whenever BRST# (BPCI Reset) is asserted regardless of the presence of the

BPCLK (BPCI clock) signal.

? Access to BPCI configuration space is disabled during reset. After reset, the BPCI bus is logically

disconnected from the CompactPCI bus for all accesses except configuration cycles.

? The BRST# (BPCI Reset) signal can be released asynchronous to the BPCLK (BPCI Clock).

? The BPCI buffers can tolerate precharge to 1.0V+/-20% without excessive current drain or oscillation.

? The BPCI signals can tolerate the release of BRST# (BPCI Reset) while the BPCI bus is in any portion of an

active cycle.

Other Hot Swap board level functions must be provided external to the 82600. The BD_SEL# signal, a Hot Swap

board level signal pin, must be routed to an active high reset input pin of a power monitoring device that produces a

PWRGOOD signal to input into the 82600. The inversion of PWRGOOD can be used to form the Hot Swap

HEALTHY# board level output. In addition, circuitry must be added to precharge the BPCI bus to an intermediate

voltage level (typically 1.0V ? 20%) during insertion to keep from disturbing the BPCI backplane signals when the

board contacts the bus.

5.7 BPCI/SDRAM 4-Channel DMA Controller

The BPCI DMA channels in the 82600 provide a highly efficient means to move data between local SDRAM and the

BPCI bus. Two outgoing channels support moving data from SDRAM to the BPCI bus and two incoming channels

support moving data from the BPCI bus into SDRAM. Each channel can independently be set to one of two modes:

direct-host DMA control mode and a DMA chaining mode that supports scatter/gather operation. In direct-host

DMA control mode, the DMA channel control and status registers are mapped into the local host I/O address space

and are not directly accessible from the BPCI bus. In DMA chaining mode, each channel can be programmed to fetch

a linked list of DMA descriptors from the host memory; giving each DMA channel a scatter/gather capability. The

channels are available to the local host in both BPCI Central Resource mode and Peripheral Bridge mode.

When in Peripheral Bridge mode the DMA control protocol between the Central Resource and the local processor is

not defined by the hardware. It is left up to the system implementation to define this protocol through use of the

Doorbell Registers, shared memory or other provided resources. Please also note that initiation of DMA using

external DMA request/grant pins is not supported.

5.7.1 Direct-Host Control Mode

The 82600 supports four DMA channels that span the BPCI to SDRAM bus. In direct host control mode, DMAs are

initiated by the host processor writing to address and control registers that are mapped into the host I/O address

space. The 82600 maps these registers into the power management space. Each of the channels may be programmed

to transfer from 1 to (2**24 – 1) bytes starting and ending on any byte boundary. The DMA channels run

independently so no ordering between the channels is implied or guaranteed. It is up to software to insure that

address overlaps do not occur. The DMA channels are optimized for transfers of data between the BPCI bus and

main memory SDRAM. They do not support PCI to PCI bus transfers or SDRAM to SDRAM transfers.

There are four identical sets of control registers, one set for each BPCI/SDRAM DMA channel. In direct host control

mode, the host processor configures each DMA channel by writing the BPCI bus 32-bit starting physical address,

the 32-bit starting address in SDRAM, and the number of bytes to be transferred (up to 16MB –1). In this mode no

address translation occurs. The channels only support memory DMA. I/O DMA is not supported. The channel

selected determines the direction of the DMA. An outgoing DMA register set controls DMA transfers that read

SDRAM and write to the BPCI bus. An incoming DMA register set controls DMA transfers that read from the BPCI

bus and write to the local SDRAM. All SDRAM accesses are routed through the local host bus to maintain cache

coherency and will honor the local bus’ locked accesses.

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To maximize performance, each DMA channel feeds an independent, 64-byte FIFO that either buffers the read data

from the BPCI domain into the SDRAM domain (incoming) or buffers the read data from the SDRAM domain into the

BPCI domain (outgoing). Each DMA channel’s BPCI burst length is fixed at 32 bytes. The BPCI target can always

throttle this burst length, if needed, by issuing a disconnect with data and the 82600 will break the multi-Dword BPCI

access into multiple accesses as required by the PCI specification.

When using an outgoing DMA channel (SDRAM read and BPCI write), the controller reads the data from SDRAM

into the internal 64 byte BPCI write buffer. The channel will always attempt to burst read from the SDRAM up to the

first 32-byte host address boundary provided the transfer length is long enough. When the first 32 bytes of the

buffer is full the controller requests the control of the BPCI bus. The next SDRAM read is initiated when at least 32

bytes of FIFO are available. The BPCI portion of the DMA waits until its write FIFO has enough bytes to fill out a line

(unless the transfer length is at 0) in the BPCI address space before a write access to the BPCI bus is requested. After

being granted the BPCI bus the 82600 starts a burst write transaction using the PCI memory write command code on

the BPCI bus. The 82600 can perform the up to 32 byte burst transaction with zero wait states. When the 32 bytes (or

partial line for a non-aligned BPCI starting address) have been transferred, the controller gives up the BPCI bus

control and waits for the next 32 read bytes from the SDRAM and for a 2-bit pacing timer to expire before reacquiring

the BPCI bus. This is iterated until the whole data block is transferred. Any partial line accesses required to complete

the end of the DMA are handled automatically by the hardware. The DMA In Progress signal is cleared after the

transfer length is 0 and the write buffers have been emptied.

When using an incoming DMA channel (SDRAM write and BPCI read), the DMA channel first requests the control

of the BPCI bus. The channel will always attempt to burst read from the BPCI bus up to the first 32-byte BPCI

address boundary provided the transfer length is long enough. On subsequent reads, the DMA channel waits until

at least 32 bytes are available in the FIFO and also waits for a pacing timer that was started on completion of the

previous BPCI access to expire before attempting to burst the next 32 bytes. Since the 82600 can buffer the entire 32

bytes of data from the BPCI, it will receive bursted BPCI data with no wait states. The SDRAM portion of the DMA

waits until the write FIFO has enough bytes to fill out a line (unless the transfer length is at 0) in the host address

space before a write access to the SDRAM is initiated. The above process is repeated until the transfer length is 0.

Any partial line accesses required to complete the end of the DMA are handled automatically by the hardware. The

DMA In Progress signal is cleared after the transfer length is 0 and the write buffers have been emptied.

Once started, the DMA operation normally terminates under hardware control but can be aborted by software. The

DMA operation normally terminates when the byte count reaches 0 and the associated write FIFO is empty, a BPCI

master or target abort occurs, or a host address is generated that does not map to the SDRAM. When a DMA

operation terminates, the DMA In Progress bit in the associated DMA Control/Status register is cleared.

Alternatively, software may write the DMA Start bit in the associated DMA Control/Status register to 0 to terminate

the DMA transfer without waiting for entire transfer to complete. In response to this, the hardware will stop initiating

read transactions to the source bus and will wait until the pending reads and writes have completed before setting

the DMA In Progress bit to 0. After waiting for the DMA In Progress bit to be cleared, software can check the

Transfer Length register to determine if the DMA completed. The Transfer Length register will contain 0 if the DMA

completed. If the DMA did not complete it can be restarted at the point where it was terminated by setting the DMA

Start bit. In DMA chaining mode described in section 5.7.2 clearing the DMA Start bit while an access to the next

descriptor is in progress results in the DMA In Progress bit being cleared after the DMA registers have been loaded

with the next descriptor. If no descriptor access is in progress, then the DMA is terminated in the same manner as a

non-chained DMA.

The host SDRAM address register, the BPCI address register, and DMA length register contents are constantly

being updated during the DMA. If the DMA is prematurely terminated by an error condition these registers point to

the address that caused the error condition. BPCI master abort (no DEVSEL# is returned) or target abort error flags

and the SDRAM abort error flags are set in respective channel status registers by the respective error condition.

Writing a 1 into the respective bit positions of appropriate channel Control/Status registers clears these bits. If the

BPCI target terminates the DMA transaction by RETRY or DISCONNECT, the transaction is restarted immediately by

the 82600. The new request is performed immediately after time out termination.

Any number of bytes are supported from 1 up to (16MB – 1) in a single DMA transfer. The SDRAM to BPCI write

buffers in the outgoing channels are always flushed to the BPCI bus as soon as the transfer length register reaches

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zero even though the FIFO only contains a partial BPCI line. Similarly, the BPCI to SDRAM write FIFOs in the

incoming channels are always flushed to the host bus (SDRAM) as soon as the transfer length register reaches 0.

5.7.2 DMA chaining mode.

When the DMA chaining mode bit is set in the DMA Control/Status register, the BPCI address, Host address, and

Transfer length registers can no longer be loaded by host-initiated I/O writes while the chained DMA is in progress.

They can be loaded if the DMA has not yet started or has completed. Instead software must set up a linked list of

DMA descriptors in the local host’s SDRAM memory and a non-null pointer to the first descriptor by writing to the

Next Descriptor Address Register. Each descriptor describes a DMA transaction by defining the BPCI address, Host

address, and Transfer length as shown in Table 18. When a DMA is started in this mode by setting the Start DMA

bit, the 82600 uses the initial “physical” address in the Next Descriptor Address register to generate a 16-byte read

reference to the local host’s SDRAM. If this descriptor access does not map to the local SDRAM, the DMA is

stopped and the host abort flag is set; otherwise, the contents of the fetched descriptor update the respective DMA

control registers and the initial DMA operation is started. When the transfer length for the first descriptor reaches 0,

the Next Descriptor Address register is again used to fetch the next local host SDRAM memory resident DMA

descriptor that initiates the next discrete DMA operation. The individual DMA operations in chained mode reuse the

same address, control, status registers and FIFOs that are used in Direct-Host Control Mode. The direction of the

chained DMA is determined by the channel being used so a single DMA chain can only DMA in one direction. The

DMA chaining process iterates until the DMA channel fetches a “null” descriptor. When the last DMA operation

completes (Transfer length = 0) and the Next Descriptor Address is null (0), no more descriptors are fetched and the

DMA In Progress bit is cleared and the DMA start bit is cleared.

Table 18: 16 byte Chaining Descriptor

Host address offset Contents

0 BPCI address

4 Host address

8 Transfer length

12 Next Descriptor address (0 = Null)

5.8 LPCI Bridge Capabilities

5.9 LPCI Target Support

As a target, the LPCI interface claims (asserts DEVSEL) LPCI accesses that are destined to the 82600’s SDRAM

interface. The LPCI interface uses the SDRAM’s host address map as the LPCI address map for both the SDRAM

main memory and any SDRAM-bus-resident flash. For example, if 64MB of SDRAM memory is present, this memory

would appear in both the host and the LPCI address spaces starting at address 0 for both address spaces. PAM

entries and the ISA Hole Enable are honored in both address spaces: that is, if the PAM register indicates that

SDRAM is read/write enabled for a particular region of memory, then accesses to this region from either the host or

LPCI bus will go to the SDRAM. Conversely, if the PAM indicates that a region of memory is not to be directed to

SDRAM, then host accesses to this region are sent to the LPCI bus and LPCI bus accesses to this region are not

claimed by the 82600. The one exception here is an SMM access, if the SMI reclaim bit is set. Figure 9 summarizes

LPCI and host address space memory maps.

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Figure 9: LPCI and Host Address Memory Maps

Host 32 bit Address Space LPCI Address Space

FFFF_FFFF

64 MB of SDRAM Flash

FFFF_FFFF

64MB of SDRAM Flash

or BPCI or LPCI

or general purpose

FC00_0000

FC00_0000

memory space

8000_0000

0100_0000

00E0_0000

0010_0000

000F_0000

000E_0000

000D_0000

000C_0000

000A_0000

0

LPCI

BPCI Window 1 Set by

P2P MBL1 Base and

Limit Register

LPCI

BPCI Window 0 Set by

P2P MBL0 Base and

Limit Register

LPCI

SDRAM or BPCI or

LPCI (SDRAM has

priority, then BPCI

window decodes, else

LPCI)

LPCI hole or SDRAM

SDRAM

PAM0[5:4]

PAM4

PAM2 & PAM3

PAM1

PAM0[1:0]

SDRAM

Maximum top of

SDRAM memory is

2GB. Actual top is

set by DRB[3]. 8000_0000

Minimum top of

SDRAM memory is

16MB. Actual top

is set by DRB[3].

0100_0000

00E0_0000

0010_0000

000F_0000

000E_0000

000D_0000

000C_0000

000A_0000

R

Peripheral memory space

LDEVSEL is not asserted

for the BPCI windows

that appear in the host

address space

82600 SDRAM or

peripheral memory space

(82600 SDRAM has

priority)

LPCI peripheral memory

space or 82600 SDRAM

LDEVSEL is asserted

(82600 SDRAM)

PAM0[5:4]

PAM4

PAM2 & PAM3

PAM1

PAM0[1:0]

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0

LDEVSEL is asserted

(82600 SDRAM)


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A summary of LPCI target and initiator support is given in Table 19.

Table 19: LPCI Target and Initiator Support

C/BE# Command Target Support Initiator Support

0000 Interrupt Acknowledge No Yes (only when internal

south bridge is disabled)

0001 Special Cycle (Halt, shutdown,

sync, and stopclockack)

No No

0010 I/O read No Yes

0011 I/O write No Yes

0100 reserved No No

0101 reserved No No

0110 Memory Read Yes Yes

0111 Memory Write Yes Yes

1000 reserved No No

1001 reserved No No

1010 Configuration Read No Yes

1011 Configuration Write No Yes

1100 Memory Read Multiple As Memory Read No

1101 Dual Address cycle No No

1110 Memory Read Line As Memory Read No

1111 Memory Write and Invalidate As Memory Write No

5.10 Host Processor Bus Interface

The 82600 host processor bus interface connects directly to the GTL+ host bus of the Celeron, Pentium II and

Pentium III processors. The 82600 is optimized for 133MHz-host bus operation and also supports 100MHz and

66MHz host buses. The core and most other interfaces operate at 3.3V. Normally the 82600 is involved in all local bus

transactions. The 82600 segregates bus transactions as:

? 36 address-bit references

? SDRAM references

? LPCI bus cycles

? BPCI bus cycles

? Internal register

? Special cycle (includes halt/shutdown, cache flush, etc.)

? Interrupt Acknowledge

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5.11 36 Address-bit References

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The 82600 claims 36 address-bit (addresses > 4GB) references and terminates them without forwarding them to any

other unit. Writes are terminated by dropping the data. Zero data with the GTL+ data bus not driven is returned for

36-bit address reads. No error indication is signaled for these accesses.

5.12 SDRAM References

The 82600 handles accesses to memory addresses that span the programmed SDRAM address range. The region of

memory from 640K to 1MB may be optionally mapped to the LPCI bus using the Programmable Attribute Map (PAM)

registers. SDRAM in this region may also be write protected. A single 2MB SDRAM memory “hole” may be enabled

at address 0x00E0_0000-0x00FF_FFFF that allows accesses to the “hole” region to be sent to the LPCI bus instead of

SDRAM. The SDRAM behind the areas that are not mapped as SDRAM cannot be reclaimed through address

remapping; however, SMI host accesses to these SDRAM addresses can be used to access these areas. When

access to SDRAM is enabled from either PCI interface, accesses to regions within the 640K to 1MB that are mapped

as read/write SDRAM complete successfully by returning DEVSEL# and data; otherwise DEVSEL# is not asserted for

an access to this region. The 82600 will not respond with DEVSEL# to a PCI address that matches the ISA 2MB hole,

if it is enabled.

5.13 Backplane PCI References

BPCI bus memory cycles are positively decoded from the host memory space. BPCI bus memory cycles are generated

in response to local host initiated memory accesses that meet the following qualifications:

(1) Address is < 4GB when flash is configured on the LPCI bus or < 4GB – 64MB when flash is configured on

the SDRAM bus

(2) The address is > than the top of local SDRAM

(3) The address falls within one of the two base and limit regions defined within the virtual PCI to PCI Bridge

Registers. If one of the base registers is configured to start below the top of SDRAM, the SDRAM address

space takes precedence and an address that falls between the base register and the top of SDRAM will be

sequenced to SDRAM.

BPCI bus I/O is also positively decoded. BPCI I/O cycles are generated that meet the following priority qualifications:

(1) An internal 82600 peripheral is not mapped at the I/O address range used by the 82600 (EIDE, USB,

SMBus,16550, 32-bit references to 0xCF8 and 0x1CF8, all I/O addresses < 0x100 when the internal South

Bridge is enabled)

(2) The I/O address falls within the I/O base and limit region defined within the virtual PCI to PCI Bridge

Registers. Please note PCI configuration semantics for I/O addresses 0xCFC-CFF and 0x1CFC-1CFF that

address the Configuration Data Registers if enabled by the respective Configuration Index Register take

priority over the base and limit register routing control.

5.14 LPCI References

LPCI bus memory is both positively and subtractively decoded from the host address space. LPCI bus memory

cycles are generated in response to local host initiated memory accesses that meet the following qualifications:

(1) Address is < 4Gigabytes.

(2) The access falls above SDRAM or is mapped to the LPCI bus by either the PAM registers or by the “hole

enable”.

(3) The access is not routed to the BPCI bus by the P2P base and limit registers.

LPCI bus I/O is subtractively decoded from the host I/O address space. LPCI bus I/O cycles are generated that meet

the following priority qualifications:

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(1) An internal 82600 peripheral is not mapped at the I/O address range used by the 82600 (EIDE, SMBus,16550,

all I/O addresses < 0x100 when internal South bridge is enabled)

(2) The I/O address does not fall within the I/O base and limit region defined within the virtual PCI to PCI Bridge

Registers. Please note PCI configuration semantics for I/O addresses 0xCFC-CFF and 0x1CFC-1CFF that

address the Configuration Data Registers if enabled by the respective Configuration Index Register take

priority over the base and limit register routing control.

5.15 Internal Registers

The 82600 handles internal register references. All internal registers are I/O mapped. For internal register details see

the Register Description section.

5.16 Special Cycles

The 82600 accepts and returns a no data response for all of the Halt or special cycle transactions that include the

flush acknowledge cycle, flush, sync, SMI acknowledge, branch trace messages, shutdown, and stop grant

acknowledge cycles. TRDY# is additionally asserted to complete the response to branch trace messages.

When the internal South bridge is enabled, the 82600 converts an interrupt acknowledge cycle into a two cycle

handshake with the internal 8259 and then returns the highest priority interrupt vector on the local processor

HD[7:0]# data lines.

5.17 DMA and PCI Initiated SDRAM Cycles

PCI memory transactions, PC/PCI DMAs, BPCI/SDRAM DMAs, EIDE/Ultra DMAs, and USB DMAs that are

destined for the SDRAM explicitly use the local processor bus as the pathway to the SDRAM. Thus, an LPCI write

to SDRAM causes a 32-bit-address memory write transaction to be initiated on the local host processor bus. An LPCI

read to SDRAM causes a 32-bit-address memory read on the processor bus. If the read hits a modified line on the

processor, the write-back data is both written to SDRAM and supplies the data to the LPCI read. If a LPCI write hits

a modified line, the processor’s modified data is first written to SDRAM, then the LPCI write data is written to

SDRAM. I/O cycles from either PCI bus are not claimed or forwarded to the processor bus.

5.18 Locked Cycles

The 82600 supports the processors HLOCK# by not allowing any PCI or DMA accesses to break into a processor’s

locked accesses.

5.19 SDRAM Memory Controller

The 82600 integrates a main memory SDRAM controller that supports up to four banks of memory. The four banks

can support a mix of sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs, each of which

can be any size from 16MB to 512MB. Both registered (control signals buffered) and unbuffered DIMM types are

supported. Mixing of registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs is not

allowed. The 82600 SDRAM interface operates at the same frequency as the CPU bus, 66MHz, 100MHz or 133MHz.

The SDRAM interface is also fully configurable through a set of control registers. To simplify system design and

improve access speed, the 82600 SDRAM memory controller supports a glueless interface to a standard

asynchronous or asynchronous page-mode x16 flash on the SDRAM bus.

The first memory bank (RAS/CS0#) always begins at host processor’s address 0. The second memory bank

(RAS/CS1#) always contiguously follows the first. The third memory (RAS/CS2#) module contiguously follows the

second bank, etc. Any combination of banks can be populated (for example banks 0 and 2 could be depopulated and

banks 1 and 3 populated).

For the LPCI interface, this SDRAM is mapped into its PCI address space starting at address 0 in a fashion similar to

standard PC-compatible North Bridge chips. From the BPCI interface, this memory is accessible as controlled by two

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BARs (PCI Base Address Registers), two MRBARs (Memory Remap Base Address Registers), the RBAR (ROM

Base Address Register), and the RRBAR (ROM Remap Base Address Register). All or any power of 2 portion

(>1MB) of the SDRAM may be made available to the BPCI bus through these registers independent of whether the

82600 is configured as the Central Resource or Peripheral Bridge. This allows all or a portion of main memory to be

protected from BPCI bus accesses. In a system with a non power of 2 size of main memory (e.g. 48MB) requires the

use of 2 or more BARs to map the exact amount of SDRAM memory into the BPCI address space.

Detection of the presence and size of installed memory uses the 82600 SMBus to interrogate the DIMM(s) Serial

Presence Detect (SPD) mechanism as defined in the JEDEC 168-pin DIMM standard. This standard uses the SCL

(serial clock), SDA (serial data) and SA[2:0] pins on the DIMM(s) to detect the presence, size and attributes of the

installed DIMM(s). All devices on the SMBus have a seven bit address. For DRAM DIMMs the upper four bits are

defined by the JEDEC standard to be 1010. The lower three bits are determined by strapping on the SA[2:0] pins.

The SCL and SDA pins of the DIMMs are connected directly to the SMBus SMBCLK and SMBDATA pins of the

82600. After the SPD data has been read from the installed DIMM(s), the BIOS can determine the attributes of the

memory and properly configure the 82600 SDRAM memory controller.

Supported memory organizations are shown in Table 20. 2KB, 4KB, 8KB, and 16KB SDRAM page sizes are

supported; however, the 82600 page size setting should be set to 8KB when using a 16KB (11 column address bits)

device. See the supported memory configuration in Table 20 for the entire list of supported page sizes versus

memory technology. Only page sizes for each particular technology listed in this table are supported. For example,

for a 64MB row size only a 4KB-page size is supported.

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Table 20 Supported Memory Configurations

DRAM attributes DRAM DIMM DRAM device DRAM

size

Tech Depth Width SSx64

Depth

DSx64

Depth

Rows Cols Banks Min.

per side

180 Subject to Change Advance Information

Page

size

16Mb 2M 8 2M 4M 11 9 2 16MB 4KB

16Mb 4M 4 4M 8M 11 10 2 32MB 8KB

64Mb 2M 32 2M 4M 11 8 4 16MB 2KB

64Mb 4M 16 4M 8M 12 8 4 32MB 2KB

64Mb 8M 8 8M 16M 12 9 4 64MB 4KB

64Mb 16M 4 16M 32M 12 10 4 128MB 8KB

128Mb 4M 32 4M 8M 12 8 4 32MB 2KB

128Mb 8M 16 8M 16M 12 9 4 64MB 4KB

128Mb 16M 8 16M 32M 12 10 4 128MB 8KB

128Mb 32M 4 32M 64M 12 11 4 256MB 8KB

128Mb 32M 4 32M 64M 13 10 4 256MB 8KB

256Mb 8M 32 8M 16M 12 9 4 64MB 4KB

256Mb 16M 16 16M 32M 13 9 4 128MB 4KB

256Mb 32M 8 32M 64M 13 10 4 256MB 8KB

256Mb 64M 4 64M 128M 13 11 4 512MB 8KB

512Mb 32M 16 32M 64M 13 10 4 256MB 8KB

512Mb 64M 8 64M 128M 13 11 4 512MB 8KB

512Mb 128M 4 128M 256M 13 12 4 1GB 8KB

The 82600 memory controller supports the option for a single-error-correction/double-error-detection error correcting

code (SEC/DED ECC) for a 64 bit QWord. This results in a 72 bit bus including the syndrome bits. When enabled,

the SDRAM ECC mechanism automatically generates an 8 bit protection code for the 64 bit Qword during SDRAM

write operations. If the originally requested write operation transfers single or multiple Qwords, the ECC protected

SDRAM writes are completed with no overhead. If the originally requested operation transfers less than the full 64

bit QWord then the 82600 will automatically execute a read-modify-write operation to recalculate and rewrite the

proper ECC field data.

When enabled, the ECC mechanism allows a detection of single-bit and multiple-bit errors and recovery of single-bit

errors. During DRAM read operations, a full QWord of data (8 bytes) is always transferred from SDRAM to the 82600

regardless of the size of the originally requested data. Both 64-bit data and 8-bit ECC code are transferred

simultaneously. The ECC checking logic in the 82600 generates a new ECC code for the received 64-bit data and

compares it with received ECC code. If a single-bit error is detected the ECC logic generates a new “recovered” 64-bit

QWord with a pattern which corresponds to the originally received 8-bit ECC protection code. The corrected data is

returned to the requester (the CPU, or a PCI master on either PCI bus). Additionally, the 82600 ensures that the data

is corrected in main memory so that accumulation of errors is prevented. Another error within the same QWord

would result in a double-bit error that is unrecoverable. This technique is known as hardware scrubbing since it


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requires no software intervention to correct the data in memory. The ECC mechanism will also detect all errors

confined to a single nibble. For example, all multiple bit errors within the first nibble (data bits 0,1,2, and 3) would be

detected without aliasing to a “correctable” single bit error.

To assist in diagnosis and debug of main memory, an error address latch records the address of bit errors detected by

the ECC mechanism. A single bit (correctable) error flag and a multiple bit (non-correctable) error flag indicate

whether this register contains the address of a single bit or multiple bit error. Once a single or multiple bit error

occurs, the respective flag is set and the memory address associated with the error is latched. Until the error flag is

cleared by writing a 1 to the flag bit position, the offending memory address is retained. For single bit errors, an NMI

routine may be optionally invoked to allow tracking of the offending SDRAM rows. For multiple bit errors, BSERR#

and NMI can both be signaled if the appropriate enable bits are set.

The 82600 SDRAM controller also supports CAS before RAS refresh cycles at 7.8uS, 15.6uS and 125uS rates. The

refresh rate is selected in the SDRAM control register and is based on the RTC X1 input pin (32,768 Hz).

For the SDRAM multiplexing described in Table 21, 82600 signals MA[7:0] always contain the HA[22:15] addresses

during row accesses and the HA[10:3] addresses during column accesses. For entries with 8 bit column address the

page size should be set to 2KB. For entries with 9 column addresses, the page size should be set to 4KB. For entries

with 10 or more column addresses the page size should be set to 8KB. Registered DIMMs must be used for row

organizations that contain 16 chips (4 bit wide SDRAM chips).

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Row Size Addr. Split

row x col +

banksel

Table 21 DRAM Address Muxing vs. SDRAM Row and Column Size

Row

/ Col

A12

(MA14)

A11

(MA13)

BA1

(MA12)

BA0

(MA11)

A10

(MA10)

A9

(MA9)

A8

(MA8)

Row org.

#chips x (org).

16MB 11x9 + 1 Row 12 23 14 13 8x(2Mb x 8)

Col 12 AP 11

16MB 11x8 + 2 Row 12 11 23 14 13 2x(2Mb x 32)

Col 12 11 AP 8x(2Mb x 8)

32MB 11x10 + 1 Row 13 23 14 24 16x(4Mb x 4)

Col 13 AP 12 11

32MB 12x8 + 2 Row 13 12 11 23 14 24 4x(4Mb x 16)

12x8 + 2

13x8 + 1

Col 12 11 AP 2x(4Mb x 32)

16x(4Mb x 4)

64MB 12x9 + 2 Row 25 13 12 23 14 24 8x(8Mb x 8)

Col 13 12 AP 11 4x(8Mb x 16)

2x(8Mb x 32)

128MB 13x9 + 2 Row 26 25 13 12 23 14 24 4x(16Mb x 16)

Col 13 12 AP 11

128MB 12x10 + 2 Row 25 14 13 23 26 24 16x(16Mb x 4)

Col 14 13 AP 12 11 8x(16Mb x 8)

256MB 13x10 + 2 Row 27 25 14 13 23 26 24 8x(32Mb x 8)

12x11 + 2 Col 27 14 13 AP 12 11 16x(32Mb x 4)

512MB 13x11 + 2 Row 28 25 14 13 23 26 24 16x(64Mb x 4)

Col 27 14 13 AP 12 11

1GB 13x12 + 2 Row 28 25 14 13 23 26 24 16x(128Mb x

4)

5.20 Boot ROM/Flash ROM Interface

Col 29 27 14 13 AP 12 11

The Boot ROM/Flash ROM interface supports a variety of ROM/Flash devices placed on either the SDRAM bus or

the LPCI bus. A power-on strapping option bit is used to select either the SDRAM interface or the LPCI bus location

for the flash. A single generic 150ns access time (assuming a 66Mhz-host clock) x16 flash/EPROM page or non-page

mode device may be attached gluelessly to the SDRAM interface. This option maps of the top 64MB of the address

space, including the reset vector, to this interface. The 82600 supports a maximum flash address space of 64MB. To

implement a large flash area, multiple flash devices are required and external buffering and decode logic must be

added. When this option is not selected, access to this space will default to the LPCI bus where external logic is

required to handle the flash device interface.

The timing diagram in Figure 10 shows the 66MHz Host/SDRAM bus frequency non-page mode fixed read/write

timing, in Host clock quantas, that the 82600 supports to a x16 flash device located on the SDRAM interface. For

100MHz and 133MHz Host/SDRAM bus frequencies the timing is extended by 11 clocks to accommodate 150ns flash

devices. Note that OE# is held negated throughout a write access and WE# is held negated throughout a read

access. The top 64MB of the 4GB-address space is supported as flash memory by the SDRAM interface when this is

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selected as the flash interface by the MA4 power-up option bit. Note also that while any length of read is supported

to a flash device on the SDRAM interface, only 16-bit writes are supported to these devices. If page-mode flash

timing is selected in the SDRAM control register, each subsequent read access within a quad-word requires only the

lower two address bits to toggle and will only take 3 clocks (45ns at 66Mhz) per access. This timing supports

~25MB/sec. flash bandwidth from a single x16 flash device. A flash device on the SDRAM interface may also be

write-protected via a bit in the SDRAM control register.

CE#

OE#

DATAIN

ADDRESS

WE#

DATAOUT

Figure 10: Non-Page Mode Read/Write Timing

S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10/

S21

Valid Address

Valid write data

5.21 Ultra DMA/66 Enhanced IDE Interface

S11/

S22

The 82600 fast IDE interface supports up to 2 IDE devices providing an interface for IDE hard disks, flash disks, CD-

ROMs and DVD-ROMs. Since each IDE device can have independent timings, the EIDE interface fully supports the

PIO (programmed I/O – processor issues I/O read/write to transfer disk data) modes as well as Ultra DMA mode that

allows a disk transfer to be completed directly to/from system memory at up to 66MB/sec. The 82600 EIDE

implementation uses an independent high-speed bus for control and data transfer. With this architecture, EIDE

transactions do not consume bandwidth on either PCI bus and can be concurrent with PCI transactions.

To support legacy software, the EIDE configuration registers are located in the Configuration Space Header (CSH) at

device 0, function 1 of the LPCI bus. When enabled as the primary interface, I/O addresses 0x1F0-1F7 are decoded for

CS1# and 0x3F6 is decoded for CS3#. In addition, the BAR within the function 2 CSH points to a separate 16-byte,

local host processor’s I/O region that contains the EIDE Ultra-DMA control/data registers.

To minimize system component count and complexity, all the EIDE control and data signals connect directly to the

82600. This interface may be configured as a primary drive interface. When the EIDE is not needed, the EIDE device

pins can be reconfigured for use as general purpose Digital I/O pins.

5.22 Enhanced Universal Serial Bus (USB) Controller

The 82600 contains a USB Host Controller that includes the root hub and two USB ports. The USB Host Controller

supports the standard Universal Host Controller Interface (UHCI) Rev. 1.1. In conformance to the Rev. 1.1

specification, an overcurrent condition will power down both the USB ports and provide an overcurrent indication to

the local processor. The two USB ports allow two USB peripheral devices to directly connect to the 82600 without an

external hub. If more than two external USB devices are required, external USB hubs can be connected to either or

both of the 82600 built-in ports.

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To support legacy software, the USB configuration registers are located in the CSH at device 0, function 2 of the

LPCI bus. The actual USB Host Controller registers consume 32 bytes of the host’s I/O address space as located by

the BAR within the function 2 CSH.

5.23 Core PC Logic

An integrated 82C206 is contained within the 82600 to implement the core PC logic. This includes all of the legacy

PCAT compatible peripherals including the interrupt controllers (8259s), DMA controllers (8237s), timer/counter

(8254), address mapper (74LS612), and RTC. The 82600 provides a configuration option to completely disable the

“82C206” peripherals. All of these peripherals reside on an internal 8-bit peripheral bus and are accessed in less than

10 host clocks. This approximates a pseudo one wait-state 16Mhz AT bus clock rate. The 8237 DMA controller is

clocked by the LPCI clock (LPCLK).

5.24 Interrupt Controllers

There are two fully compatible 8259A interrupt controllers in the 82600, providing up to 13 external interrupts. The

8259s have been enhanced to support PCI level sensitive interrupts: an “Edge/Level” interrupt control register

controls whether each interrupt input is considered to be an edge-triggered interrupt or a level sensitive interrupt.

Interrupts from both PCI buses can be routed to the 8259s through the use of the LIRQ and BIRQ Routing Control

Registers. The four LPCI interrupt pins can be routed to any of the IRQs: IRQ[3:7,9:12,15]. When the 82600 is acting

as the BPCI Central Resource, the four BPCI interrupt pins can be routed to any one or more of the IRQs:

IRQ[3:7,9:12,15]. If the routing registers focus more than one BPCI or LPCI interrupt to the same 8259 interrupt input,

then these PCI interrupts are internally ORed together so that the assertion of either PCI interrupt will cause the

“level-sensitive” assertion of the 8259’s interrupt input.

Several interrupt inputs are fixed by the PC architecture. IRQ0 is always connected internally to the 8254 counter 0

output. IRQ1, IRQ8, IRQ9, and IRQ12 can also be optionally driven internally from the keyboard controller, the RTC,

power management functions, and the internal PS2 mouse controller respectively. IRQ14 is always sourced from a

dedicated pin and cannot be set using SERIRQ protocol.

5.25 8259 Overview

The ISA compatible Programmable Interrupt Controller (PIC) incorporates the functionality of two 8259A interrupt

controllers. The PIC is implemented as a portion of the 82C206 megacell. These controllers provide system interrupts

for the ISA compatible interrupts. Such interrupts include the system timer, keyboard controller, serial ports, IDE

interface, mouse, and DMA channels. In addition, this interrupt controller can support the PCI based interrupts, by

mapping the LPCI or BPCI interrupts onto ISA interrupt lines. When configured in this fashion the mapped 8259A

interrupts must be set to detect level sensitive interrupts. Each 8259A core supports 8 interrupts, numbered 0 - 7. The

two 8259 interrupt controllers are connected as shown in Table 22.

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8259 8259 Input Typical Interrupt

Source

Table 22: 8259A Interrupt Controller Connections

Connected Pin / Function

Master 0 Internal Internal Timer / Counter 0 output

1 Internal/Generic Keyboard or IRQ1

2 Internal Slave Controller INTR output

3 Internal/Generic COM2 or IRQ3

4 Internal/Generic COM1 or IRQ4

5 Generic IRQ5

6 Generic IRQ6

7 Generic IRQ7

Slave 0(8) Internal RTC or IRQ8

1(9) Internal/Generic SCI (power management, watchdog, SMBus, DMA, and

BIST) or IRQ9

2(10) Generic IRQ10

3(11) Generic IRQ11

4(12) Internal/Generic PS/2 Mouse or IRQ12

5(13) Internal State Machine output based on processor FERR# assertion.

6(14) Primary IDE cable IRQ14 from input pin

7(15) Secondary IDE/Generic IRQ15

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Several interrupt lines are dedicated. The slave controller is cascaded into the master controller through the master

controller interrupt input #2. IRQ0 is hardwired to the system internal timer/counter #0 output. IRQ13 is hardwired to

the processor FERR# assertion. This leaves 13 interrupts available for other functions. By convention, several other

interrupts are used for PC/AT functions as described in Table 22. Interrupts can individually be programmed to be

edge or level except for IRQ0, IRQ1, IRQ2, and IRQ8.

5.25.1 Interrupt Controller I/O Register Location

The addresses for the interrupt controller registers are located in the I/O memory space at 20h and 21h for the master

controller (IRQ0 - 7), and at A0h and A1h for the slave controller (IRQ8 - 15). These registers have multiple functions,

depending upon the data written to them. Table 23 describes the different register possibilities for each address. For

details on the register functionality see the Register Descriptions.

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Table 23: PIC Registers

Port Register Name/Function Default Value Type

20h Master PIC ICW1 Initilization Command Word 1 Register Undefined Write Only

Master PIC OCW2 Operation Control Word 2 Register 001XXXXXb Write Only

Master PIC OCW3 Operation Control Word 3 Register X01XXX10b Read/Write

21h Master PIC ICW2 Initilization Command Word 2 Register Undefined Write Only

Master PIC ICW3 Initilization Command Word 3 Register Undefined Write Only

Master PIC ICW4 Initilization Command Word 4 Register 01h Write Only

Master PIC OCW1 Operation Control Word 1 Register 00h Read/Write

A0h Slave PIC ICW1 Initilization Command Word 1 Register Undefined Write Only

Slave PIC OCW2 Operation Control Word 2 Register 001XXXXXb Write Only

Slave PIC OCW3 Operation Control Word 3 Register X01XXX10b Read/Write

A1h Slave PIC ICW2 Initilization Command Word 2 Register Undefined Write Only

Slave PIC ICW3 Initilization Command Word 3 Register Undefined Write Only

Slave PIC ICW4 Initilization Command Word 4 Register 01h Write Only

Slave PIC OCW1 Operation Control Word 1 Register 00h Read/Write

4D0h Master PIC Edge/Level Triggered Register 00h Read/Write

4D1h Slave PIC Edge/Level Triggered Register 00h Read/Write

5.25.2 Interrupt Handling

5.25.2.1 Generating Interrupts

The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt level. These bits are

used to determine the interrupt vector returned, and status of any other pending interrupts. These bits are defined in

Table 24.

Bit Description

Table 24: Interrupt Status Registers

IRR Interrupt Request Register. This bit is set on a low to high transition of the interrupt line in edge mode, and by an

active high level in level mode. This bit is set whether or not the interrupt is masked. However, a masked interrupt will

not generate INTR.

ISR Interrupt Service Register: This bit is set, and the corresponding IRR bit cleared, when an interrupt acknowledge

cycle is seen, and the vector returned is for that interrupt.

IMR Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts will not generate

INTR.

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5.25.2.2 Acknowledging Interrupts

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The CPU generates a single interrupt acknowledge cycle. The 82600 translates this command into two internal INTA#

pulses expected by the 8259A cores. The PIC uses the first internal INTA# pulse to freeze the state of the interrupts

for priority resolution. On the second INTA# pulse, the master or slave will sends the interrupt vector to the

processor with the acknowledged interrupt code. This code is based upon bits [7:3] of the corresponding ICW2

register, combined with three bits representing the interrupt within that controller as described in Table 25.

Table 25: Content of Interrupt Vector Byte

Master,Slave Interrupt Bits [7:3] Bits [2:0]

IRQ7,15 111

IRQ6,14 110

IRQ5,13 101

IRQ4,12 ICW2[7:3] 100

IRQ3,11 011

IRQ2,10 010

IRQ1,9 001

IRQ0,8 000

5.25.2.3 Hardware/Software Interrupt Sequence

1. One or more of the Interrupt Request Lines (IRQ) are raised high in edge mode, or seen high in level

mode, setting the corresponding IRR bit.

2. The PIC sends INTR to the CPU if an asserted interrupt is not masked.

3. The CPU acknowledges the INTR and responds with an interrupt acknowledge cycle.

4. Upon observing its own interrupt acknowledge cycle, the 82600 converts it into the two cycles that

the internal 8259A pair can respond to. Each cycle appears as an interrupt acknowledge pulse on the

internal INTA# pin of the cascaded interrupt controllers.

5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR bit is set and the

corresponding IRR bit is reset. On the trailing edge of the first pulse, a slave identification code is

broadcast by the master to the slave on a private, internal three bit wide bus. The slave controller

uses these bits to determine if it must respond with an interrupt vector during the second INTA#

pulse.

6. Upon receiving the second internally generated INTA# pulse, the PIC returns the interrupt vector. If

no interrupt request is present because the request was too short in duration, the PIC will return

vector 7 from the master controller.

7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of the second INTA#

pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the

interrupt subroutine.

5.25.3 Initialization Command Words (ICW)

Before operation can begin, each 8259A must be initialized. In the 82600, this is a four-byte sequence. The four

initialization command words are referred to by their acronyms: ICW1, ICW2, ICW3, and ICW4.

The base address for each 8259 initialization command word is a fixed location in the I/O memory space: 20h for the

master controller, and A0h for the slave controller.

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5.25.3.1 ICW1

An I/O write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to ICW1.

Upon sensing this write, the PIC expects three more byte writes to “base address + 1” (21h for the master controller

and A1h for the slave controller) to complete the ICW sequence.

A write to ICW1 starts the initialization sequence during which the following automatically occur:

1. Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to

generate an interrupt.

2. The Interrupt Mask Register is cleared.

3. IRQ7 input is assigned priority 7.

4. The slave mode address is set to 7.

5. Special Mask Mode is cleared and Status Read is set to IRR.

5.25.3.2 ICW2

The second write in the sequence, ICW2, is programmed to provide bits [7:3] of the interrupt vector that will be

released onto the data bus by the interrupt controller during an interrupt acknowledge. A different base is selected

for each interrupt controller.

5.25.3.3 ICW3

The third write in the sequence, ICW3, has a different meaning for each controller.

? For the master controller, ICW3 is used to indicate which IRQ input line is used to cascade the slave

controller. Within the 82600, IRQ2 is used. Therefore, bit 2 of ICW3 on the master controller is set to a 1,

and the other bits are set to 0's.

? For the slave controller, ICW3 is the slave identification code used during an interrupt acknowledge cycle.

On interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller over three

internal cascade lines if an IRQ line from the slave won arbitration on the master controller and was granted

an interrupt acknowledge by the CPU. The slave controller compares this identification code to the value

stored in its ICW3, and if it matches, the slave controller assumes responsibility for broadcasting the

interrupt vector.

5.25.3.4 ICW4

The final write in the sequence, ICW4, must be programmed both controllers. At the very least, bit 0 must be set to a

1 to indicate that the controllers are operating in an Intel Architecture-based system.

5.25.4 Operation Command Words (OCW)

These command words dynamically reprogram the Interrupt Controller to operate in various interrupt modes.

? OCW1 masks and unmasks interrupt lines.

? OCW2 controls the rotation of interrupt priorities when in rotating priority mode and controls the EOI

function.

? OCW3 is sets up ISR/IRR reads, enables/disables the Special Mask Mode SMM, and enables/disables

polled interrupt mode.

The OCWs can be written to the interrupt controllers any time after initialization.

5.25.5 Modes of Operation

5.25.5.1 Fully Nested Mode

This is the default operation mode after initialization. In this mode, interrupt requests are ordered in priority from 0

through 7, with 0 being the highest. When an interrupt is acknowledged, the highest priority request is determined

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and its vector placed on the bus. Additionally, a bit in the In Service Register (ISR[7:0]) for the interrupt is set. This

ISR bit remains set until: the CPU issues an EOI command immediately before returning from the service routine; or if

in Automatic End Of Interrupt (AEOI) mode, on the trailing edge of the second INTA#. While the ISR bit is set, all

further interrupts of the same or lower priority are inhibited, while higher levels will generate another interrupt. This

higher priority interrupt will be acknowledged only if the CPU interrupt enable has been re-enabled.

Interrupt priorities can be changed from the initialization default of IRQ0 being the highest and IRQ7 being the lowest

in the rotating priority mode.

5.25.5.2 Special Fully Nested Mode

This mode will be used in the case of a system where cascading is used, and the priority has to be conserved within

each slave. In this case, the special fully nested mode will be programmed to the master controller. This mode is

similar to the fully nested mode with the following exceptions:

? When an interrupt request from a certain slave is in service, this slave is not locked out from the master's

priority logic and further interrupt requests from higher priority interrupts within the slave will be recognized

by the master and will initiate interrupts to the processor. In the normal nested mode, a slave is masked out

when its request is in service.

? When exiting the Interrupt Service routine, software has to check whether the interrupt serviced was the

only one from that slave. This is done by sending a Non-Specific EOI command to the slave and then

reading its ISR. If it is 0, a non-specific EOI can also be sent to the master.

5.25.5.3 Automatic Rotation Mode (Equal Priority Devices)

In some applications, there are a number of interrupting devices of equal priority. Automatic rotation mode provides

for a sequential 8-way rotation. In this mode, a device receives the lowest priority after being serviced. In the worst

case, a device requesting an interrupt will have to wait until each of seven other devices are serviced at most once.

There are two ways to accomplish automatic rotation using OCW2; the Rotation on Non-Specific EOI Command (R =

1, SL = 0, EOI = 1) and the Rotate in Automatic EOI Mode which is set by (R = 1, SL = 0, EOI = 0) and cleared by (R =

0, SL = 0, EOI = 0).

5.25.5.4 Specific Rotation Mode (Specific Priority)

Software can change interrupt priorities by programming the bottom priority and thus fixing all other properties. For

example, if IRQ5 is programmed as the bottom priority device, then IRQ6 will be the highest priority device. The Set

Priority Command is issued in OCW2 to accomplish this, where: R = 1, SL = 1, and LO-L2 is the binary priority level

code of the bottom priority device.

In this mode, internal status is updated by software control during OCW2. However, it is independent of the EOI

command. Priority changes can be executed during an EOI command by using the Rotate on Specific EOI Command

in OCW2 (R = 1, SL = 1, EOI = 1 and LO-L2 = IRQ level to receive bottom priority).

5.25.5.5 Poll Mode

Poll Mode can be used to conserve space in the interrupt vector table. Multiple interrupts that can be serviced by

one interrupt service routine do not need separate vectors if the service routine uses the poll command. Polled Mode

can also be used to expand the number of interrupts. The polling interrupt service routine can call the appropriate

service routine, instead of providing the interrupt vectors in the vector table. In this mode, the INTR output is not

used and the CPU internal Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is

achieved by software using a Poll Command.

The Poll command is issued by setting P = 1 in OCW3. The PIC treats its next I/O read as an interrupt acknowledge,

sets the appropriate ISR bit if there is a request, and reads the priority level. Interrupts are frozen from the OCW3

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write to the I/O read. The byte returned during the I/O read will contain a ‘1’ in bit 7 if there is an interrupt, and the

binary code of the highest priority level in bits 2:0.

5.25.5.6 Cascade Mode

The PIC in the 82600 has one master 8259 and one slave 8259 cascaded onto the master through IRQ2. This

configuration can handle up to 15 separate priority levels. The master controls the slaves through a three bit internal

bus. In the 82600, when the master drives 010b on this bus, the slave controller takes responsibility for returning the

interrupt vector. An EOI Command must be issued twice: once for the master and once for the slave.

5.25.5.7 Edge and Level Triggered Mode

In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the entire controller. In the

82600, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is

included. This is the Edge/Level control Registers ELCR1 and ELCR2.

If an ELCR bit is ‘0’, an interrupt request will be recognized by a low to high transition on the corresponding IRQ

input. The IRQ input can remain high without generating another interrupt. If an ELCR bit is ‘1’, an interrupt request

will be recognized by a high level on the corresponding IRQ input and there is no need for an edge detection. The

interrupt request must be removed before the EOI command is issued to prevent a second interrupt from occurring.

In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling edge of the first

internal INTA#. If the IRQ input goes inactive before this time, a default IRQ7 occurs when the CPU acknowledges

the interrupt. This can be a useful safeguard for detecting interrupts caused by spurious noise glitches on the IRQ

inputs. To implement this feature, the IRQ7 routine is used for “clean up” simply executing a return instruction, thus

ignoring the interrupt. If IRQ7 is needed for other purposes, a default IRQ7 can still be detected by reading the ISR. A

normal IRQ7 interrupt sets the corresponding ISR bit; a default IRQ7 does not set this bit. However, If a default IRQ7

routine occurs during a normal IRQ7 routine, the ISR remains set. In this case, it is necessary to keep track of whether

or not the IRQ7 routine was previously entered. If another IRQ7 occurs, it is a default.

5.25.5.8 End of Interrupt Operations

An EOI can occur in one of two fashions: by a command word write issued to the PIC before returning from a service

routine, the EOI command; or automatically when AEOI bit in ICW1 is set to 1.

5.25.5.9 Normal End of Interrupt

In Normal EOI, software writes an EOI command before leaving the interrupt service routine to mark the interrupt as

completed. There are two forms of EOI commands: Specific and Non-Specific. When a Non-Specific EOI command is

issued, the PIC will clear the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of

operation of the PIC within the 82600, as the interrupt being serviced currently is the interrupt entered with the

interrupt acknowledge. When the PIC is operated in modes that preserve the fully nested structure, software can

determine which ISR bit to clear by issuing a Specific EOI.

An ISR bit that is masked will not be cleared by a Non-Specific EOI if the PIC is in the Special Mask Mode. An EOI

command must be issued for both the master and slave controller.

5.25.5.10 Automatic End of Interrupt Mode

In this mode, the PIC will automatically perform a Non-Specific EOI operation at the trailing edge of the last interrupt

acknowledge pulse. From a system standpoint, this mode should be used only when a nested multi-level interrupt

structure is not required within a single PIC. The AEOI mode can only be used in the master controller and not the

slave controller.

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5.25.6 Masking Interrupts

5.25.6.1 Masking on an Individual Interrupt Request

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Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This register is programmed

through OCW1. Each bit in the IMR masks one interrupt channel. Masking IRQ2 on the master controller will mask

all requests for service from the slave controller.

5.25.6.2 Special Mask Mode

Some applications may require an interrupt service routine to dynamically alter the system priority structure during its

execution under software control. For example, the routine may wish to inhibit lower priority requests for a portion of

its execution but enable some of them for another portion.

The Special Mask Mode enables all interrupts not masked by a bit set in the Mask Register. Normally, when an

interrupt service routine acknowledges an interrupt without issuing an EOI to clear the ISR bit, the interrupt controller

inhibits all lower priority requests. In the Special Mask Mode, any interrupts may be selectively enabled by loading

the Mask Register with the appropriate pattern.

The special Mask Mode is set by OCW3 where: ESMM = 1, SMM = 1, and cleared where ESMM = 1, SMM = 0

5.25.7 Steering PCI Interrupts

The 82600 can be programmed to allow PIRQA#-PIRQD# signals from both PCI interfaces to be internally routed to

interrupts 3-7, 9-12, or 15. The assignment is programmable through the LIRQx and BIRQx Route Control registers.

One or more PCI interrupt lines can be routed to the same IRQx input. If interrupt steering is not required, the Route

Registers can be programmed to disable steering.

The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on PCI devices to share a

single line. When a PCI interrupt is routed to specified IRQ line, software must change the IRQ's corresponding

ELCR bit to level sensitive mode. The 82600 will internally invert the PIRQx# line to send an active high level to the

PIC. When a PCI interrupt is routed onto the PIC, an internal or serial interrupt device can no longer use the selected

IRQ.

If an external PS2 keyboard controller is used, care must be taken to insure that IRQ1 and IRQ12 are signaled

properly. Some old PS2 keyboard controllers incorrectly pulse IRQ1 and IRQ12. If this is the case, the SERIRQ logic

would be required to extend the IRQ1 and IRQ12 signaling.

5.26 Serial IRQ (SERIRQ) Support

The 82600 supports a serial IRQ scheme. This allows a single pin to be used to report ISA-style interrupt requests.

Internal interrupt pins fed from enabled internal peripherals or either PCI interrupt routing register take precedence

over the SERIRQ interrupts. For example, if an internal COM1 is enabled to drive its IRQ signal, then the source of

IRQ4 would be the internal UART and IRQ4 from the SERIRQ output would be ignored. In the case that an internal

peripheral and a PCI interrupt are configured to use the same interrupt, the PCI interrupt signal is used.

All serial interrupt timing is based on the LPCI clock. If the LPCI clock is not running the 82600 will not see a serial

interrupt.

5.26.1 SERIRQ Protocol

Serial interrupt information is transferred using three types of frames: a Start frame, one or more IRQ Data frames, and

one Stop frame. There are also two modes of operation for generating the Start frame: Quiet Mode and Continuous

Mode.

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5.26.1.1 Quiet (Active) Mode Start Frame

To indicate an interrupt, the peripheral brings the SERIRQ signal active for one clock and then 3-states the signal.

This brings all the state machines from IDLE to the ACTIVE states. The 82600 then takes control of the SERIRQ

signal by driving it low on the next clock, and continues driving it low for 3–7 clocks more (programmable). The total

number of clocks low will be 4–8. After those clocks, the 82600 drives SERIRQ high for one clock and then 3-states

the signal.

5.26.1.2 Continuous (Idle) Mode Start Frame

In this mode the 82600 rather than the peripherals initiates the Start frame. Typically, this is done to update the IRQ

status (acknowledges). The 82600 drives SERIRQ low for 4–8 clocks. This is the default mode after reset, and can be

used to enter the Quiet mode.

5.26.1.3 Data Frame

Once the Start frame has been initiated, all of the serial interrupt peripherals must start counting frames based on the

rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly three phases of one clock each: a Sample phase, a

Recovery phase, and a Turn-around phase.

During the Sample phase, peripherals see the start, reset their state machines, and drive SERIRQ low in the

appropriate data frame. See Table 26. Since each frame consists of 3 LPCI clocks, the peripheral is responsible for

asserting SERIRQ in the first clock of the frame and then executing recovery and turnaround cycles during the last

two cycles of a frame. The peripheral devices drive SERIRQ low if the corresponding interrupt signal should be

active. If the corresponding interrupt is inactive, then the devices should not drive the SERIRQ signal. It will remain

high due to pull-up resistors. During the other two phases (Turn around and Recovery), no device should drive the

SERIRQ signal. The IRQ/DATA frames have a specific order and usage, as shown in Table 26.

5.26.1.4 Stop Frame

After all of the data frames, a Stop frame is performed done by the 82600. This is accomplished by making SERIRQ

low for 2–3 clocks. The number of clocks determines the next mode:

If SERIRQ is low for 2 clocks, the next mode is the Quite Mode. Any device may initiate a Start frame in the second

clock (or more) after the rising edge of the Stop frame.

If SERIRQ is low for 3 clocks, the next mode is the Continuous Mode. Only the 82600 may initiate a Start frame in the

second clock (or more) after the rising edge of the Stop frame.

For a 33Mhz PCI bus, this protocol allows the interrupts to be updated once every 3 microseconds. Note that 2

cycles past the start clock in the table below would correspond to the first cycle past the recovery and 3-state cycles

executed by the 82600 at the end of a Start cycle.

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Table 26: SERIRQ Frames

Data Frame Number Usage # Clocks Past Start Internal Source, Comments

1 Unassigned 2 Timer 0

2 IRQ1 5 Keyboard, if enabled

3 SMI 8 ORed with internal SMI sources

4 IRQ3 11 COM2, if enabled

5 IRQ4 14 COM1, if enabled

6 IRQ5 17

7 IRQ6 20

8 IRQ7 23

9 IRQ8 26 RTC, if enabled

10 IRQ9 29

11 IRQ10 32

12 IRQ11 35

13 IRQ12 38 Mouse, if keyboard is enabled

14 unassigned 41 Numeric error logic

15 unassigned 44 IRQ14 pin (actual 82600 pin)

16 IRQ15 47

17 IOCHK 50

18 LPCI INTA 53 ORed internally with LPIRQA#

19 LPCI INTB 56 ORed internally with LPIRQB#

20 LPCI INTC 59 ORed internally with LPIRQC#

21 LPCI INTD 62 ORed internally with LPIRQD#

22:32 unassigned 65:95

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When IOCHK# status is available to be read in bit 6 of PORTB (0x61), if bit3 of PORTB is low (Enable IOCHK NMI)

and NMIs are enabled (via a write of a 1 to bit 7 to the RTC Index Register at address 0070), then an NMI is signaled

to the processor.

5.27 8237 Compatible DMA

The 8237 compatible DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven

independently programmable channels as shown in Figure 11. DMA Controller 1 (DMA-1) corresponds to DMA

Channels 0–3 and DMA Controller 2 (DMA-2) corresponds to Channels 5–7. DMA Channel 4 is used to cascade the

two controllers and will default to cascade mode in the DMA Channel Mode (DCM) Register. This channel is not

available for any other purpose. In addition to accepting requests from DMA slaves, the DMA controller also

responds to requests that are initiated by software. The integral 74LS612 compatible memory mapper provides the

upper 8-bits of the 24-bit DMA address that is sourced during an access.

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Channel 0

Channel 1

Channel 2

Channel 3

5.27.1 8237 Compatible DMA Overview

Figure 11: 8237A DMA Controller

Channel 4

Channel 5

DMA-1 DMA-2

Channel 6

Channel 7

The 82600 embedded 8237 compatible DMA supports PC/PCI DMA protocol. To use the 8237 compatible DMA

controller, the ISA bridge support bit must be set in the Miscellaneous Function Enable register.

Main features of the 82600 DMA controller are:

1) Channels 0-3 provide 8-bit, count-by-bytes transfers.

2) Channels 5-7 provide 16-bit, count-by-words transfers.

3) 24-bit addressing. Each channel includes a 16-bit ISA-compatible Current Address Register (CAR) which

holds the 16 least-significant bits, and an ISA Compatible Page Register, which contains the eight next most

significant bits of address.

4) Auto-initialization following a DMA termination.

The DMA controller has registers that are fixed in the lower 64 KB of I/O space. For a complete description of the

DMA controller registers se the Register Description section.

5.27.2 DMA Channel Arbitration

The 82600 DMA controller consists of two logical channel groups: Channels 0-3 and Channels 4-7. Each group may

be in either fixed mode or rotate mode described in detail below. The DMA Command Registers determine the mode

of operation for each controller. Since channels 0-3 are cascaded onto channel 4, any request seen on channel 0 - 3

appears as a request on channel 4.

In fixed mode, the lowest numbered channel in a channel group receives highest priority. Therefore, channel 0 is the

highest priority device of channels 0 - 3, and channel 4 is the highest priority device of channels 4 - 7. When both

channels are programmed in fixed mode, channel 0 has highest priority, and channel 7 the lowest.

In rotating mode, the lowest numbered channel starts out with highest priority. When it is serviced, the next

numbered channel receives highest priority, and the previous channel receives lowest priority. For example, if

channel 0 has highest priority and is requesting, it will win arbitration, then will be the lowest priority channel until

channel 1, 2, and 3 have been serviced.

Due to the nature of channel 0 - 3 being cascaded onto channel 4, rotating mode adds some peculiarities to the

arbitration scheme. Table 27 lists arbitration winners, assuming all channels were requesting.

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Table 27: DMA Channel Priority

R

Current Both Fixed Lower Fixed, Upper Rotating Lower Rotating, Upper Fixed Both Rotating

0 0, 1, 2, 3, 5, 6, 7 5, 6, 7, 0, 1, 2, 3 1, 2, 3, 0, 5, 6, 7 5, 6, 7, 1, 2, 3, 0

1 0, 1, 2, 3, 5, 6, 7 5, 6, 7, 0, 1, 2, 3 2, 3, 0, 1, 5, 6, 7 5, 6, 7, 2, 3, 0, 1

2 0, 1, 2, 3, 5, 6, 7 5, 6, 7, 0, 1, 2, 3 3, 0, 1, 2, 5, 6, 7 5, 6, 7, 3, 0, 1, 2

3 0, 1, 2, 3, 5, 6, 7 5, 6, 7, 0, 1, 2, 3 0, 1, 2, 3, 5, 6, 7 5, 6, 7, 0, 1, 2, 3

5 0, 1, 2, 3, 5, 6, 7 6, 7, 0, 1, 2, 3, 5 0, 1, 2, 3, 5, 6, 7 6, 7, 0, 1, 2, 3, 5

6 0, 1, 2, 3, 5, 6, 7 7, 0, 1, 2, 3, 5, 6 0, 1, 2, 3, 5, 6, 7 7, 0, 1, 2, 3, 5, 6

7 0, 1, 2, 3, 5, 6, 7 0, 1, 2, 3, 5, 6, 7 0, 1, 2, 3, 5, 6, 7 0, 1, 2, 3, 5, 6, 7

5.27.3 Special Cases in Address / Count

5.27.3.1 Address Overrun / Under-run

Whenever the DMA is operating, the addresses do not increment or decrement through the High and Low Page

Registers. Therefore, if a 24 bit address is 01FFFFh and increments, the next address will be 010000h, not 020000h.

Similarly, if a 24 bit address is 020000h and decrements, the next address will be 02FFFFh, not 01FFFFh.

5.27.3.2 16 Bit Channels

For 16 bit channels, the DMA controller addressing is different than for 8 bit channels. The DMA controller shifts

the lower 16 bits of address left 1 bit and shifts in a ‘0’, as shown in Table 28. The count register is also redefined to

represent words instead of bytes.

Register

Table 28: Address Shifting in 16-bit DMA Transfers

Page High Byte Low Byte Address on 8 bit channels (hex) Address on 16 bit channels (hex)

00 01 01 00.01.01 00.02.02

01 7F 85 01.7E.85 01.FF.0A

01 FF FF 01.FF.FF 01.FF.FE

5.27.4 Theory of Operation for PC/PCI

5.27.4.1 Overview

The PC/PCI protocol uses the 8237 DMA controller, yet performs both the I/O and memory transfer via the LPCI bus.

The PC/PCI implementation on 82600 is for ISA bridge support.

The 82600 supports an LPCI REQ#/GNT# pair which can encode the 7 valid 8237 DMA channels. A channel is

programmed to be PC/PCI through the ISA bridge support bit in the Miscellaneous Function Enable register.

5.27.4.2 Protocol

The PC/PCI protocol uses a pair of side band signals to communicate DMA Request / DMA Acknowledge

information between the PC/PCI device and the 8237 within the 82600. The LPCI bus to transfer data between memory

and the I/O device. The protocol involves two signal lines, a REQ# line, which serializes DMA requests from the

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PC/PCI device to the 82600, and a GNT# line, which serializes DMA acknowledges from the 82600 to the PC/PCI

device. The basic signaling mechanism is shown in Figure 12. The PCICLK used for timing the transfer is the LPCI

clock LPCLK.

LPCLK

LREQ3#

LGNT3#

Figure 12: Basic DMA Serial Channel Passing Protocol

0ns 100ns 200ns 300ns 400ns

start CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

start bit0 bit1 bit2

1. Channel 4 is ignored by the 82600. Channel 4 is defined as a LPCI request, and is not supported by the 82600.

2. Since Channel 4 is ignored by the 82600, the 82600 will never generate a grant for channel 4.

The REQ#/GNT# lines in the 82600 are LREQ3# and LGNT3#. It is the responsibility of software to ensure that the

PC/PCI devices do not request the same DMA channels.

The encoding for the PC/PCI grant message delivered for the 82600 is shown in Table 29.

Table 29: Grant Bit Encoding

Grant Bits

2 1 0 Granted Channel

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 82600 will not generate

1 0 1 5

1 1 0 6

1 1 1 7

The 82600 PC/PCI REQ# de-serializer must obey the following rules:

1. The REQ# and GNT# state machines run independently and concurrently. A GNT# could be received by the

device while it is in the middle of sending a serial REQ#, and a GNT# could be active while REQ# is inactive.

2. If a PC/PCI device has more than one request active, it will resend the request serial protocol after one of the

requests has been granted the bus and it has completed its transfer (i.e. it has de-asserted its DREQ). It will

drive its REQ# inactive for 2 clocks and then transmit the serial channel passing protocol again. This is

shown in Figure 13.

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PCICLK

REQA#

DREQ0

DREQ1

DREQ2

DREQ3

Figure 13: PC/PCI Request de-assertion with Additional Requests Pending

s 0 1 2 3 4 5 6 s 0 1 2 3 4 5 6

2 clks

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3. If a PC/PCI device has another internal request go active or inactive before 82600 asserts GNT#, it will resend

the expansion channel passing protocol to update the 82600 with this new request information. It will deassert

REQ# for 1 clock, then retransmit with the updated information. The 82600 is able to handle the one

clock de-assertion of REQ# up to 5 LPCI clocks after the start frame of the grant message. An example is

shown in Figure 14.

Figure 14: PC/PCI Request Protocol - New Requests Pending

PCICLK

REQA#

DREQ0

DREQ1

DREQ2

DREQ3

s 0 1 2 3 4 5 6 7

1 CLK

S 0 1 2 3 4 5 6 7

4. If a PC/PCI device has only one request active and that request goes inactive before the 82600 asserts GNT#,

the PC/PCI device must resend the expansion channel passing protocol to update the 82600 that the request

has been de-asserted. It will de-assert REQ# for 1 clock, then retransmit 9 clocks of 0. (Start + 8 channels deasserted.)

Then it will de-assert REQ#. The 82600 is able to handle the one clock de-assertion of REQ# up to

5 PCI clocks after the start frame of the grant message. An example is shown in Figure 15.

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PCICLK

REQ#

DREQ0

DREQ1-7

5.27.4.3 PC/PCI DMA Cycles

5.27.4.3.1 Overview

Figure 15: PC/PCI Request Protocol - No Requests Pending

S 0 1 2 3 4 5 6 7 S 0 1 2 3 4 5 6 7

82600 supports 3 types of DMA cycles: DMA Memory to I/O, DMA I/O to Memory and Verify cycles. For DMA

transfers between memory and the I/O device (i.e. non-verify transfers), the DMA controller performs a load followed

by a store as opposed to the ISA "fly-by" cycle.

Table 30: PC/PCI Cycle I/O Address Table

5.27.4.3.2 DMA Addresses

Cycle Type PCI AD (hex) PCI Command (hex)

Normal 00000000 2 (read), 3 (write)

Normal Terminal Count 00000004 2 (read), 3 (write)

Verify 000000C0 2

Verify Terminal Count 000000C4 2

The memory portion of the cycle will generate a DRAM memory read or memory write bus cycle, its address

representing the selected memory location. The I/O portion of the DMA cycle will generate a LPCI I/O cycle to one

of four I/O addresses, as illustrated in Table 30

These I/O addresses are ones that the 82600 would normally respond to as hits to the DMA controller.

5.27.4.3.3 DMA Data / Byte Enable Generation

The data generated by PC/PCI devices on I/O reads when they have an active GNT# appears in the lower two bytes

of the LPCI LAD bus. For 8 bit channels, the data appears on LAD[7:0]. For 16 bit channels, the data appears on

LAD[15:0]. On I/O writes the 82600 places the data to be written in these same locations on the LPCI bus.

The byte enables generated by the 82600 on I/O reads and writes must correspond to the size of the I/O device. I/O

devices on channels 0 - 3 are 8 bit channels and will result in LC/BE#[3:0] = 1110, and I/O devices on channels 5 - 7

are 16 bit channels and will result in LC/BE#[3:0] = 1100.

Each I/O read will result in one memory write, and each memory read will result in one I/O write. If the I/O device is 8

bit, an 8 bit memory write will be performed. The 82600 does not assemble the I/O read into a Dword for writing to

memory. Similarly, the 82600 will not disassemble a Dword read from memory to the I/O device. The 82600 will

assemble up to a Qword for the memory portion of a block or demand DMA

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5.27.4.3.4 DMA Cycle Termination

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DMA cycles are terminated when a terminal count is reached in the DMA controller and the channel is not in autoinitialization

mode, or when the PC/PCI device de-asserts its request. The PC/PCI device must follow explicit rules

when de-asserting its request, or the 82600 may not see it in time and run an extra I/O and memory cycle.

The PC/PCI device must de-assert its request 7 LPCLKs before it generates LTRDY# on the I/O read or write cycle, or

the 82600 is allowed to generate another DMA cycle. For transfers to memory, this means that the memory portion of

the cycle will be run without an asserted PC/PCI LREQ#.

5.27.4.3.5 Normal DMA Cycles

Figure 16 and Figure 17 show a normal transfer between main memory and a 16 bit I/O device. On the second

transfer, the device has de-asserted its DREQ, so the PC/PCI device does not drive TRDY# on the I/O cycle until it

has driven REQ# inactive and guaranteed that the 82600 will see it as inactive. The memory portion of a DMA

transfer never appears on the LPCI bus.

Cycle

LPCLK

LAD

LC/BE#

LFRAME#

LIRDY#

LTRDY#

LREQ3#

Figure 16: Transfer from Memory to 16 Bit PC/PCI DMA Device

Mem Read. I/O Write Mem Read. I/O Write

0 D0 0 D1

3 C 3 C

7 Cycles

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Cycle

LPCLK

LAD

LC/BE#

LFRAME#

LIRDY#

LTRDY#

LREQ3#

Figure 17: Transfer from 16 Bit PC/PCI DMA Device to Memory

I/O Read Mem Write I/O Read Mem Write.

0 0

2 C 2 C

5.27.4.3.6 Normal DMA Cycles with Terminal Count

Figure 18and Figure 19show a normal DMA transfer between memory and a 16 bit I/O device where the DMA

controller reaches a terminal count condition and the channel is not programmed in auto-initialization mode, meaning

this will be the last transfer. On these transfers, the state of the REQ# line is irrelevant, because the 82600 will be

performing no more transfers.

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Cycle

LPCLK

LAD

LC/BE#

LFRAME#

LIRDY#

LTRDY#

LREQ3#

Cycle

LPCLK

LAD

LC/BE#

LFRAME#

LIRDY#

LTRDY#

LREQ3#

Figure 18: Transfer from Memory to 16 bit PC/PCI DMA Device

Mem Read I/O Write Mem Read I/O Write

0 D0 4 D1

3 C 3 C

Figure 19: Transfer From 16 bit PC/PCI DMA Device to Memory

I/O Read Mem Write I/O Read Mem Write

0 4

2 C 2 C

5.27.4.3.7 Verify DMA Cycles

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Figure 20 and Figure 21 show PC/PCI verify cycles. There is no memory transfer performed on a verify cycle, and the

byte enables are all invalid. In the non-terminal count case, the I/O device has de-asserted its DREQ, so the PC/PCI

device does not generate TRDY# until REQ# has been driven inactive and can be seen by the 82600 as inactive. In

the terminal count case, the state of the REQ# line is irrelevant, because the 82600 will be performing no more

transfers.

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Cycle

LPCLK

LAD

LC/BE#

LFRAME#

LIRDY#

LTRDY#

LREQ3#

Cycle

LPCLK

LAD

LC/BE#

LFRAME#

LIRDY#

LTRDY#

LREQ3#

Figure 20: PC/PCI DMA Verify Cycle

Verify Verify

C0 xx C0 xx

2 F 2 F

Figure 21: PC/PCI DMA Verify Cycle with Terminal Count

Verify Verify

C0 xx C4 xx

2 F 2 F

5.28 8254 Compatible Timer/Counter

The 82600 contains a fully compatible 8254 that supports three counter/timers with fixed uses. A 1.19Mhz clock

derived from the 14.31818 MHZ OSCIN signal divided by 12 drives each counter/timer clock input. The output of

counter 0 drives IRQ0 and is normally used to keep track of the time of day. The output of Counter2 is connected to

the SPKOUT and its TMRGATE is driven from a PORTB Register bit. By PC convention, Counter 1 has been used to

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generate DRAM refresh cycles. The 82600 refresh timing is generated independently by the SDRAM controller so

counter1 on the 82600 can be used as a general-purpose timer.

5.28.1 Counter 0, System Timer

This counter functions as the system timer by controlling the state of IRQ0 and is typically programmed for Mode 3

operation. The counter produces a square wave with a period equal to the product of the counter period (838 ns) and

the initial count value. The counter loads the initial count value one counter period after software writes the count

value to the counter I/O address. The counter initially asserts IRQ0 and decrements the count value by two each

counter period. The counter negates IRQ0 when the count value reaches 0. It then reloads the initial count value and

again decrements the initial count value by two each counter period. The counter then asserts IRQ0 when the count

value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating IRQ0.

5.28.2 Counter 1

This counter has been historically used in a PC to provide a refresh request signal to the DRAM controller and ISA

bus. Since the refresh logic already exists inside the 82600 SDRAM controller, this counter is available to be used by

software as a general-purpose timer.

5.28.3 Counter 2, Speaker Tone

This counter provides the speaker tone and is typically programmed for Mode 3 operation. The counter provides a

speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count value. The speaker

must be enabled by a write to the PortB Register. When the speaker is not enabled, this counter can be used by

software to time functions.

5.28.4 Timer Programming

The counter/timers are programmed in the following fashion:

1. Write a control word to select a counter

2. Write an initial count for that counter.

3. Load the least and/or most significant bytes (as required by Control Word bits 5, 4) of the 16-bit counter.

4. Repeat with other counters.

Only two conventions need to be observed when programming the counters. First, for each counter, the control word

must be written before the initial count is written. Second, the initial count must follow the count format specified in

the control word (least significant byte only, most significant byte only or least significant byte and then most

significant byte).

A new initial count may be written to a counter at any time without affecting that counters programmed mode.

Counting will be affected as described in the mode definitions. The new count must follow the programmed count

format.

If a counter is programmed to read/write two-byte counts, the following precaution applies: A program must not

transfer control between writing the first and second byte to another routine which also writes into that same

counter. This can cause the counter to be loaded with an incorrect count.

The Control Word Register at port 43h controls the operation of all three counters. Several commands are available:

? Control Word Command: Specifies which counter to read or write, the operating mode, and the count format

(binary or BCD).

? Counter Latch Command: Latches the current count so that it can be read by the system. The countdown

process continues.

? Read Back Command: Reads the count value, programmed mode, the current state of the OUT pins, and the

state of the Null Count Flag of the selected counter.

Table 31 lists the six operating modes for the interval counters.

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Mode Function Description

Table 31. Counter Operating Modes

0 Out signal on end of count ( = 0) Output is ‘0’. When count goes to 0, output goes to ‘1’ and stays at

‘1’ until counter is reprogrammed.

1 Hardware retriggerable one-shot Output is ‘0’. When count goes to 0, output goes to ‘1’ for one clock

time.

2 Rate generator (divide by n

counter)

Output is ‘1’. Output goes to ‘0’ for one clock time, then back to ‘1’

and counter is reloaded.

3 Square wave output Output is ‘1’. Output goes to ‘0’ when counter rolls over, and

counter is reloaded. Output goes to ‘1’ when counter rolls over, and

counnter is reloaded, etc.

4 Software triggered strobe Output is ‘1’. Output goes to ‘0’ when count expires for one clock

time.

5 Hardware triggered strobe Output is ‘1’. Output goes to ‘0’ when count expires for one clock

time.

5.28.5 Reading from the Interval Timer

It is often desirable to read the value of a counter without disturbing the count in progress. There are three methods

for reading the counters: a simple read operation, Counter Latch Command, and the Read-Back Command. Each is

explained below.

With the simple read and counter latch command methods, the count must be read according to the programmed

format; specifically, if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not

have to be read one right after the other. Read, write, or programming operations for other counters may be inserted

between them.

5.28.5.1 Simple Read

The first method is to perform a simple read operation. The counter is selected through port 40h (counter 0), 41h

(counter 1), or 42h (counter 2).

Note, performing a direct read from the counter will not return a determinate value, because the counting process is

asynchronous to read operations. However, in the case of counter 2, the count can be stopped by writing to the

GATE bit in port 61h.

5.28.5.2 Counter Latch Command

The Counter Latch Command, written to port 43h, latches the count of a specific counter at the time the command is

received. This command is used to ensure that the count read from the counter is accurate, particularly when reading

a two-byte count. The count value is then read from each counter's count register through the Count Ports Access

Ports Register.

The count is held in the latch until it is read or the counter is reprogrammed. The count is then unlatched. This

allows reading the contents of the counters on the fly without affecting counting in progress. Multiple Counter

Latch Commands may be used to latch more than one counter. Counter Latch Commands do not affect the

programmed mode of the counter in any way.

If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch

Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued.

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5.28.5.3 Read Back Command

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The Read Back Command, written to port 43h, latches the count value, programmed mode, and current states of the

OUT pin and Null Count flag of the selected counter or counters. The value of the counter and its status may then

be read by I/O access to the counter address.

The Read Back Command may be used to latch multiple counter outputs at one time. This single command is

functionally equivalent to several counter latch commands, one for each counter latched. Each counter's latched

count is held until it is read or reprogrammed. Once read, a counter is unlatched. The other counters remain latched

until they are read. If multiple count Read Back Commands are issued to the same counter without reading the count,

all but the first are ignored.

The Read Back Command may additionally be used to latch status information of selected counters. The status of a

counter is accessed by a read from that counter's I/O port address. If multiple counter status latch operations are

performed without reading the status, all but the first are ignored.

Both count and status of the selected counters may be latched simultaneously. This is functionally the same as

issuing two consecutive, separate Read Back Commands. If multiple count and/or status Read Back Commands are

issued to the same counters without any intervening reads, all but the first are ignored.

If both count and status of a counter are latched, the first read operation from that counter will return the latched

status, regardless of which was latched first. The next one or two reads, depending on whether the counter is

programmed for one or two type counts, return the latched count. Subsequent reads return unlatched count.

5.29 Real Time Clock

The 82600 contains an integrated real-time clock, providing the functions of the date/time clock, alarm, programmable

periodic interrupt, 114 bytes of standard and 128 bytes of extended battery backed CMOS RAM, crystal input and

battery input.

The RTC has a pin for the battery source (RTCVDD), a reset signal for the CMOS RAM (RTCPS), two crystal pins

(RTCX1, and RTCX2) for a 32.768khz crystal.

The RTC is integrated into the 82600 because it is a part of most PC-compatible embedded designs. However, since

some designs may want to use an external RTC solution, the ability to completely disable the RTC is provided by pin

strapping.

5.29.1 RTC Overview

Three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of

122?s to 500ms, and end of update cycle notification. Seconds, minutes, hours, days, day of week, month, and year

are counted. Daylight savings compensation is optional. The hour is represented in twelve or twenty-four hour

format and data can be represented in BCD or binary format. The design is functionally compatible with the Motorola

MS146818B. The time keeping comes from a 32.768 kHz oscillating source, which is divided to achieve an update

every second. The lower 14 bytes on the lower RAM block have very specific functions. The first ten are for time

and date information. The next four (0Ah to 0Dh) are registers, which configure and report RTC functions.

The time and calendar data should match the data mode (BCD or binary) and hour mode (12 or 24 hour) as selected in

register B. It is up to the programmer to make sure that data stored in these locations is within the reasonable ranges

and represents a possible date and time. The exception to these ranges is to store a value of C0 - FF in the Alarm

bytes to indicate a don’t care situation. All Alarm conditions must match to trigger an Alarm Flag, which could

trigger an Alarm Interrupt if enabled. The SET bit of register B should be 1 while programming these locations to

avoid clashes with an update cycle. Access to time and date information is done through the RAM locations. If a

RAM read from the ten time and date bytes is attempted during an update cycle, the value read will not necessarily

represent the true contents of those locations. Any RAM writes under the same conditions will be ignored.

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5.29.2 Update Cycles

An update cycle occurs once a second, if the SET bit of register B is not asserted and the divide chain is properly

configured. During this procedure, the stored time and date will be incremented, overflow will be checked, a matching

alarm condition will be checked, and the time and date will be rewritten to the RAM locations. To maintain

compatibility with the Motorola MS146818B, the update cycle will start at least 244?s after the UIP bit of register A is

asserted, and the entire cycle will not take more than 1984?s to complete. The time and date RAM locations (0-9) will

be disconnected from the external bus during this time.

To avoid update and data corruption conditions, external RAM access to these locations can safely occur at two

times. When a updated-ended interrupt is detected, almost 999ms is available to read and write the valid time and

date data. If the UIP bit of Register A is detected to be low, there is at least 244?s before the update cycle begins.

Warning:

The overflow conditions for leap years and daylight savings adjustments are based on more than one date

or time item. To ensure proper operation when adjusting the time, the new time and date values should be

set at least two seconds before leap year or daylight savings time adjustments occur.

5.29.3 Interrupts

The real-time clock interrupt is internally routed to the 8259. It is mapped to interrupt vector 8. This interrupt is not

shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored.

5.30 PC Speaker Interface

The 82600 contains a speaker output (SPKROUT), that is the logical AND of bit 1 of the port B register and the

integral 82C54’s OUT2 timer 2 signal.

5.31 Miscellaneous Logic (PortA, PortB, & NPX)

The 82600 performs a number of functions in support of the PC hardware architecture. The 82600 contains the

floating-point error (NPX) PC compatible logic. The 82600 also contains PC-compatible register 061h (port B) and

register 092h (port A). See register descriptions for more details on these registers.

The floating-point error support consists of two external pins (FERR# and IGNNE#). FERR# is signaled by the

processor when a floating-point error occurs and is input into the 82600. The assertion edge of FERR# clocks a flipflop

that asserts IRQ13 into the internal 8259 interrupt controller. The IRQ13 flip-flop is asynchronously cleared by an

I/O write to 0x00F0 or 0x00F1. This I/O write should be issued from within the IRQ13 handling routine. In addition

the I/O write to 0x00F0 or 0x00F1 clocks a flip-flop that causes the assertion of IGNNE# (provided FERR# is still

asserted) . The IGNNE# flip-flop is asynchronously “preset” so IGNNE# is negated whenever FERR# is negated.

5.32 Integrated Peripherals

5.33 16C550 UARTs

The 82600 includes two 16C550 UARTs. One can be enabled as COM1 and the other as COM2. The COM2

configurable port shares eight pins with the SDRAM ECC pins. If the ECC function is enabled with a power-on

option bit, the COM2 port pins are not available externally and COM2 must be disabled in the Miscellaneous

Function Enable register. The COM1 port may be configured to support IRDA at data rates up to 115Kbaud. As in a

standard PC, COM1 is accessed in the I/O address space at 0x3f8-3ff and signals interrupts on IRQ4. COM2 is

accessed at 0x2f8-0x2ff and signals interrupts on IRQ3. If the COM1 port is disabled, Digital I/O pins, DIO[31:24], that

are multiplexed with the COM port pins become available.

These COM ports can share the IRQ3 and IRQ4 interrupt lines with external COM ports or other devices that require

the use of these IRQ lines. This is done by using each internal UARTs OUT2 pin, that is normally used in PC-

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compatible designs to 3-state its IRQ signal, to steer the appropriate internal or external IRQ signal into the internal

8259 via the SERIRQ protocol.

The clock to the COM ports are fed by HCLK divided by an even divisor of up to 64 that can be programmed in the

Divisor Latch Upper and Lower registers. Divisor values of 54 and 36 (27 and 18 placed in the divisor register

respectively) allow the COM clock to operate at ~1.85Mhz clock for HCLK frequencies of 100MHz and 66.6MHz

respectively. The divisor in the COM Divisor Latch Upper and Lower registers defaults to 18 (0x12 … for 66Mhz local

bus operation) at power-on. Settings other than this PC compatible value allow the UARTs to operate up to 1.25

Mbaud with a maximum 20MHz-clock frequency sourced into the UART.

For a complete description of the UART registers se the Register Description section.

5.34 Digital I/O

The 82600 includes support for 32 Digital I/O (DIO) pins. All DIO pins are multiplexed with other pin functions; thus

the competing function (EIDE, COM1, or extended BPCI arbitration signals) must be disabled in the Miscellaneous

Function Enable register to allow the shared pins to be used as DIO pins. The digital I/O pins that are shared with

the BREQ#[6:3] signal lines can be used as digital inputs only. In the pin definitions these are noted as DI[19:16]

signal names. Driving an output value to these pins and enabling the output function will have no effect. The DIO

input register always reads the value of the actual pin, even when the competing function is enabled. Power-on

option bits initially define whether the pin functions are defined as DIO or as the competing function. To access the

DIO functions, the PWRMGT/Extended Functions Configuration Register must be configured and enabled. 82600

supports three 32-bit DIO registers: a DIO input register, a DIO output register, and a DIO direction register. These

registers allow each DIO pin to independently support either a digital input only, a digital output only, or a Digital I/O

pin functions. To drive a DIO output, the pin must be configured as a DIO pin and the respective DIO direction bit

must be set to output mode. These registers are reset by a negation of PWRGOOD to an initial state that configures

all of the DIO pins to be input-only functions.

5.35 Watchdog Timer Support

The watchdog timer is a countdown timer that can have the count restarted before reaching 0 and can cause interrupt

events to occur if the count reaches 0. It is generally used as an automatic reset mechanism in the event of a local

system lockup. The duration of the watchdog timer countdown is programmable from 1ms to 2048 seconds, ~34.13

minutes. For the watchdog timer to count the SCI Enable bit, the Reset Enable bit or both of these bits in the

Watchdog Control/Status Register must be set.

The watchdog timer is reset to the latch value and the countdown time restarts when:

1) A local processor or memory access causes assertion of LDEV1 and bit 5 is enabled in the Watchdog

Control/Status Register

2) A local processor or memory access causes assertion of LDEV0 and bit 4 is enabled in the Watchdog

Control/Status Register

3) Assertion of the BPCI BDEVSEL# by the 82600 when bit 3 is enabled in the Watchdog Control/Status

Register

4) Assertion of the BPCI BFRAME# by the 82600 when bit 2 is enabled in the Watchdog Control/Status

Register

5) A software write to the Watchdog Timer Register

6) Countdown of the watchdog timer to 0. This will also cause an interrupt or reset event depending on the

programming of the SCI Enable and Reset Enable bits of the Watchdog Control/Status Register.

If the watchdog timer counts down to 0 this is an indication that there is a problem with the local processor that can

be corrected with an interrupt or a warm restart. If the SCI Enable bit in the Watchdog Control/Status Register is set

and the SCI Enable bit in the Power Management Control Register then an SCI (IRQ9) is asserted. If the Reset Enable

bit in the Watchdog Control/Status Register is set then a warm reset occurs. A warm reset consists of:

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1) Assertion of CPURST#

2) Assertion of the LPCI LRST#

3) Reset of the 82600 internal logic and registers

4) Assertion of the BPCI BRST# if the 82600 is configured as the BPCI Central Resource

5) Driving of the local processor power-on option bits

If both the SCI Enable and Reset Enable bits in the Watchdog Control/Status Register are set then only the warm

reset occurs.

5.36 SMBus

The 82600 includes one SMBus interface that conforms to the System Management Bus Specification, Revision 1.1.

This interface operates at 16.384 KHz derived from the RTC input. The SMBus Transmit and Receive registers are

located in the Power Management register space. The two SMBus registers are the SMBus Transmit/Status/Control

Register located at PWRBASE+0x30 and the SMBus Input/Control/Status Register located at PWRBASE+0x32. The

accessible base address must be set in the PWRBASE PWRMGT/Extended Functions Configuration Register before

accesses can commence. To reduce software complexity and reduce the burden on the local processor, IRQ9 can be

configured in the PWRBASE PWRMGT/Extended Functions Configuration Register to be level signaled whenever

any of the following SMBus events occur:

1) Transmit Done

2) Negative Acknowledge

3) Lost Arbitration

4) Time-out

5) SMBus Data Available.

The 82600 cannot be configured to act as a slave on the SMBus.

5.37 Keyboard/Mouse Controller

The 82600 contains a PC/AT compatible keyboard controller with PS/2 compatible mouse controller extensions. If it

is not needed or an external keyboard controller is desired, it may be disabled in the Miscellaneous Function Enable

Register.

The keyboard controller is clocked by LPCLK divided by 10. Response to keyboard commands is immediate, usually

within one keyboard clock because this function is implemented as a hard-wired state machine.

The keyboard controller responds to the Keyboard Controller Data Register at I/O addresses 0x60 and the Keyboard

Controller Status/Command Register at I/O address 0x64. An I/O write to the Keyboard Controller Data Register will

fill the keyboard controller’s “Input Buffer”. An I/O read from the Keyboard Controller Data Register will return the

contents of the keyboard controller’s “Output Buffer”. Commands are issued to the keyboard controller by

performing I/O writes to the Keyboard Controller Status/Command Register. The integrated keyboard controller will

support the commands listed in Table 32. All commands except Fx and D4 will be executed in the same bus cycle that

they are issued.

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Table 32 Keyboard Controller Commands

Command (hex) Function

20 Read Command Byte

21-2F Read RAM

60 Write Command Byte

61-6F Write RAM

A7 Disable Mouse

A8 Enable Mouse

A9 Mouse Interface Test

AA Self Test

AB Keyboard Interface Test

AD Disable Keyboard

AE Enable Keyboard

C0 Read Input Port

D0 Read Output Port

D1 Write Output Port

D4 Transmit to Mouse

E0 Read Test Inputs

Fx Pulse Output Port

5.37.1 Keyboard Controller Command Descriptions

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Read Command Byte (20)

A Read Command byte will place the Command Byte in the Output buffer. A read of the Keyboard Controller Data

Register returns the output buffer contents.

Read RAM (21-2F)

The keyboard controller contains one extra byte of RAM beyond the Command byte. Execution of a 0x21 to 0x2F

command will cause the contents of this RAM to be dumped into the Output buffer.

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Write Command Byte (60)

The Write Command Byte will place the next data byte written to the Keyboard Controller Data Register into the

Command Byte. Upon reset, the Command Byte is set to 70. The bit functions are:

Bit Function

0 Enable Key Interrupt

1 Enable Mouse Interrupt

2 System Flag

3 Inhibit Override

4 Disable Keyboard

5 Disable Mouse

6 Enable Scan Code Translation

7 0

Write RAM (61-6F)

The internal keyboard controller contains one byte of RAM. A command of 0x21-0x2F will cause this RAM location

to be updated by the write to the Keyboard Controller Data Register.

Disable Mouse (A7)

A Disable Mouse command will clear bit 5 of the Command Byte.

Enable Mouse (A8)

An Enable Mouse command will set bit 5 of the Command Byte.

Mouse Interface Test (A9)

A Test Mouse Interface command will place a 00 in the Output Buffer. An Interface test will not actually occur.

Self Test (AA)

A Self Test Command will place a 55 in the Output Buffer.

Keyboard Interface Test (AB)

A Test Keyboard Interface command will place a 00 in the Output Buffer. An Interface test will not actually occur.

Disable Keyboard (AD)

A Disable Keyboard command will set bit 4 of the Command Byte.

Enable Keyboard (AE)

An Enable Keyboard command will clear bit 4 of the Command Byte.

Read Input Port (C0)

A Read Input Port command will place the contents of the Input Port in the Output Buffer.

Read Output Port (D0)

A Read Output Port command will place the contents of the Output Port in the Output Buffer.

Write Output Port (D1)

The Write Output Port command will place the next data byte written to the Keyboard Controller Data Register to the

Output Port.

Transmit to Mouse (D4)

This command will cause the next byte written to the Keyboard Controller Data Register to be sent to the mouse. The

execution time of this of this command will depend upon the mouse.

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Read Test Inputs (E0)

A Read Test Inputs command will place T0 and T1 in D0 and D1, respectively, of the Output Buffer. Bits D2 - D7 will

be 0.

Pulse Output Port (Fx)

The Pulse Output Port Command will pulse bits 0-3 of the Output Port low for at least 6 microseconds. Bits 0-3 of this

command determine which bits will be pulsed. A command of FF will execute in the same bus cycle it is issued.

5.37.2 GATEA20 and RESET

Since the D1 command takes place in the same bus cycle it is issued, a change in GATEA20 will happen immediately.

An Fx command will take from 6.4 to 128 us to generate a reset depending on the clock speed. An FF command will

take place in the same bus cycle it is issued.

Table 33: Keyboard Status Register

Bit Function

0 Output Buffer Full

1 Input Buffer Full

2 System Flag

3 Command/Data

4 Inhibit Switch

5 Mouse Data

6 Timeout

7 0

Upon reset the Keyboard Status Register will be set to 00.

5.37.3 Keyboard and Mouse Interface

The keyboard interface will support a standard AT keyboard. The mouse interface will support a standard PS/2

mouse. The internal port pins (P1 = Input Port, P2 = Output Port) are configured as shown in Table 34:

Table 34: Mouse Internal Port Pins

Signal Function

P1(0) Key data

P1(1) Mouse data

P2(0) CPURESET

P2(1) GATEA20

P2(4) IRQ1

P2(5) IRQ12

Upon Reset all P2 port bits will be set high.

The keyboard controller clock is driven at LPCLK/10 frequency. The clock speed will determine certain timings as

shown in Table 35. Note that the FF command will execute in one bus cycle.

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Table 35: Keyboard Controller Timings

Timing LPCLK/10@ 4.16MHz

Fx Command execution (except FF) 9.99 us

Transmission backoff 153.6 us

Transmission Timeout 4.8 ms

5.38 Power Management

The 82600 contains some basic support for both OS-independent and OS-dependent power management. The OS

independent power management relies on System Management Mode (SMM) for power management of the system

environment. The 82600 also supports power management registers that several Operating Systems support.

5.39 Power Management Support

To support power management, the 82600 contains a Power Management Status Register (PMSTS), a Power

Management Resume Enable Register (PMEN), a Power Management Control Register (PMC