Chapter 4 PA-RISC Computer Systems - OpenPA.net

PA-RISC Processors Early PA-RISC
� Off-chip L1 cache up to 1024 KB, split into I/D
� Physical address space of 29-bit (512 MB main memory could be addressed)
� CPU attaches via System Main Bus (SMB) to memory and I/O (controllers)
SMB is a synchronous, pipelined bus with 64-bit wide address and data transfers
� 27.5 MHz clock speed (or maximum of 30 MHz?), power dissipation of 26W
� One circuit board, CPU implemented in NMOS-III, 183,000 FETs, 1.5µNMOS-III, die size 14.0×14.0
mm 2 die, packaged in 408-pin PGA
Used in: 822, 832, 845, 855, 860
PCX (CMOS26B)
The last PA-RISC 1.0 design was the PCX, introduced 1990 and the first PA-RISC processor fabricated
in a CMOS process. It implemented the NS-1/NS-2 NMOS design and several of the processor
functions previously supplied on external VLSI chips onto a single CPU chip. The PCX still was supplemented
by external support chips, including three CMUX (cache multiplexer — one instruction, two
data; equivalent to the earlier CCUs), SPI (SMB to processor interface — SMB is the system main bus),
FPC (floating point coprocessor) and two FP chips (MUL/DIV and ADD/SUB) [not completely clear if
the latter two or latter three chips are third-party].
� PA-RISC version 1.0 32-bit
� First multi-processor-capable PA-RISC CPU (up to four-way SMP)
� Direct predecessor of the PA-7000 (PCXS) processor which integrated most processor logic minus
the FPU onto a single die/chip
� External FPU (apparently ECL logic)
� 8192-entry TLB on-chip
� Off-chip L1 cache up to 1024 KB, split into I/D (apparently asymmetrical 1:2 I/D)
� Physical address space of 29-bit (512 MB main memory could be addressed)
� CPU attaches via System Main Bus (SMB) to memory and I/O (controllers)
SMB is a synchronous, pipelined bus with 64-bit wide address and data transfers
� 50 MHz clock speed
� One circuit board, 196,000 FETs, 1.0µ(micron), implemented in three-level CMOS (CMOS26B)
� CPU is a single chip, needs seven other (VLSI) support chips for memory/bus interfaces and I/O
Used in: 842, 852, 865, 870 There are sources which also mention a “CS-1” processor — from the
nomenclatura this would point to a CMOS design but the performance figures/charts do not really
match up with the CMOS26B/PCX described here.
References
1. Wayne E. Holt (ed.), Beyond RISC! An Essential Guide to Hewlett-Packard Precision Architecture
(January 1988: Software Research Northwest Inc.)
8