KOMPRESI CITRA JPEG BERBASIS FPGA XILINX SPARTAN-3E ...

signal dct_out2: std_logic_vector(lebar_max downto 0);--masukan dari dcta ke memorisignal en_dct,en_dct2: std_logic;signal rdy,rdy2: std_logic;signal wen,wen2: std_logic;signal ain: std_logic_vector(7 downto 0);signal aout: std_logic_vector(7 downto 0);signal aout_ram2: std_logic_vector(7 downto 0);--signal dct2_out:std_logic_vector(lebar_max downto 0);signal romrdy:std_logic;signal ain2,aout2,alamat_bc:std_logic_vector(7 downto 0);signal dct2_out,dat2_out:std_logic_vector(lebar_max downto 0);signal alamat_ram2_lo:std_logic_vector(5 downto 0);signal dc_en: std_logic;signal qmul:std_logic_vector(7 downto 0);signal dat_out_tmp: std_logic_vector(lebar_ot downto 0);beginalamat_bcdat_in,cnt_out=>open,en_out=>rdy,vout=>dct_out);mem: memori port map(ctr: controller port map(dctb: dct8b port map(addr_baca=>aout,addr_tls=>ain,data_tls=>dct_out2,data_baca=>dout,we=>wen,clk=>clk);clk=>clk,rst=>rst,a_in=>ain,a_out=>aout,en_dct=>en_dct,en_dct2=>en_dct2,we=>wen,ctr_en=>en,dct_rdy2=>rdy2,dct_rdy=>rdy,rom_rdy=>romrdy,we2=>wen2,dc_en=>dc_en,a2in=>ain2,a2out=>aout2);--aout2=aout2_hi&loclk=>clk,B - 9