KOMPRESI CITRA JPEG BERBASIS FPGA XILINX SPARTAN-3E ...

xvABSTRACTImplementation of image compression on a chip used for the compression thatrequires real-time speed. Image compression in hardware for use on various storagedevices such as digital cameras and image transmission such as video conferencingsystems.This thesis discuss about implementation of the JPEG image compressionmethod in the FPGA chip Xilinx Spartan-3E. This research aims to create an imagecompression system which can match its performance image compression chip on themarket. Designed chip can be used for storage and transmission. Image compressioncircuit is designed to fit for low-cost FPGA such as Xilinx Spartan-3E.Input images are gray scale images for testing. The compression systemconsists of modules-2D DCT, quantizer, zig-zag unit, and entropy coding.Compression circuits are described using VHDL.Circuit has been successfully simulated in Xilinx ISE software and synthesizedfor FPGA 10 and executed in hardware. Serial port is used as a medium of imageinput into the FPGA.Pipeline latency in the circuit obtained is 170 clock cycles. Data wereprocessed divided into different sized blocks of 8x8 pixels. For compression of blockn + 1280n required 170 clock cycles. Maximum clock frequency allowed in thedesign of this system is 25.724MHz. It makes rapid data that allowed the 25 724Mega bytes per second. Utilization circuit synthesis process that is obtained from aslice of 1421, look up table (LUT) of multipliers 2485 and as many as 11 units. Meanmaximum frame rate that can be achieved by a series of JPEG compression ongrayscale images is 370.04 fps (frames per second) for the size of 240x320 while thesize is 480x640 92.73 fps. The compression ratio achieved by a series of JPEGcompression can be achieved by matching the ratio of the image processing software.For small images (80x80 and 40x40), a series of compression ratio even smaller thansoftware compression ratio.keyword : compression, image, JPEG, DCT-2D, FPGA