KOMPRESI CITRA JPEG BERBASIS FPGA XILINX SPARTAN-3E ...

entity controller isport(clk: in std_logic;rst: in std_logic;a_in: out std_logic_vector(7 downto 0);a_out: out std_logic_vector(7 downto 0);en_dct: out std_logic;en_dct2: out std_logic;we: out std_logic;ctr_en: in std_logic;dct_rdy2: in std_logic;--penanda dct2 sudah ready datanyadct_rdy: in std_logic;rom_rdy: out std_logic; --menandai apakah rom zigzag sudah bisa diakseswe2: out std_logic;dc_en:out std_logic;a2in: out std_logic_vector(7 downto 0);a2out: out std_logic_vector(7 downto 0));end entity;architecture behav of controller issignal en2,rom_rd: std_logic;signal a_in1,a_out1:std_logic_vector(7 downto 0);signal a_in2a,a_out2a:std_logic_vector(7 downto 0);signal cntia,cntoa:std_logic_vector(2 downto 0);signal cntib,cntob:std_logic_vector(7 downto 0);signal cnti1a,cnto1a:std_logic_vector(2 downto 0);signal cnti1b,cnto1b:std_logic_vector(7 downto 0);signal dc:std_logic;begindc_en