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54321U31-4DCB42 CLKOUT42 TIM4_OUT42 TIM5_OUT42 TIM6_OUT42 TIM7_OUT42 SC0_VCCEN42 SC0_C442 SC0_CLK42 SC0_DATA42 SC0_DET42 SC0_RST42 SC0_VPPEN42 SC1_VCCEN42 SC1_C442 SC1_CLK42 SC1_DATA42 SC1_DET42 SC1_RST42 SC1_VPPEN31,41 SPI_MISO31,41 SPI_MOSI31,41 SPI_SCLK31,41 SPI_CS041 SPI_CS142 SPI_CS241 SPI_CS3CLKOUTTIM4_OUTTIM5_OUTTIM6_OUTTIM7_OUTSC0_VCCENSC0_C4SC0_CLKSC0_DATASC0_DETSC0_RSTSC0_VPPENSC1_VCCENSC1_C4SC1_CLKSC1_DATASC1_DETSC1_RSTSC1_VPPENSPI_MISOSPI_MOSISPI_SCLKSPI_CS0SPI_CS1SPI_CS2SPI_CS3R185 221 2R171 221 2CPU.CLKOUTCPU.SPI_SCLKF1H33H34H1G1J4J5J6J7K8K2J3H3H4H5H6J2J1H2N11P13R2R1P2P3P1CLKOUTTIM4_OUT/GP0[28]TIM5_OUT/GP0[29]TIM6_OUT/GPMC_A[24]/GP0[30]TIM7_OUT/GPMC_A[12]/GP0[31]GPMC_A[23]/GP1[14]GP1[13]GPMC_A[26]/GP1[11]GPMC_A[25]/GP1[12]GPMC_A[27]/GP1[9GPMC_A[22]/GP1[10]GPMC_A[24]/GP1[15]GPMC_A[21]/GP0[26]GP0[25]GPMC_A[14]/GP0[23]GPMC_A[13]/GP0[24]GPMC_A[16]/GP0[21]GPMC_A[15]/GP0[22]GPMC_A[12]/GP0[27]SPI_D[0]SPI_D[1]SPI_SCLKSPI_SCS[0]nSPI_SCS[1]n/GPMC_A[23]SPI_SCS[2]n/GPMC_A[22]SPI_SCS[3]n/GPMC_[A21]/GP1[22]SD_POW/GPMC_A[14]/GP1[0]SD_CLK/GPMC_A[13]/GP1[1]U4U2CPU.MMC_CLKR168 221 2R427 22SD_CMD/GPMC_A[21]/GP1[2]U3 CPU.MMC_CMD1 2I2C[1]_SDA N35 MMC_DAT0SD_DAT[0]/GPMC_A[20]/GP1[3]U1MMC_DAT1SD_DAT[1]_SDIRQ/GPMC_A[19]/GP1[4]T1MMC_DAT2SD_DAT[2]_SDRW/GPMC_A[18]/GP1[5]T2MMC_DAT3SD_DAT[3]/GPMC_A[17]/GP1[6]T13SD_SDWP/GPMC_A[15]/GP1[8]R5SD_SDCD/GPMC_A[16]/GP1[7]R13UART0_TXDN8UART0_RXDN10UART0_RIN/GPMC_A[17]/GPMC_A[22]/GP1[19]N3UART0_RTSn/GP1[27]N9UART0_DTRn/GPMC_A[20]/GPMC_A[12]/GP1[16]N6UART0_DSRn/GPMC_A[19]/GPMC_A[24]/GP1[17]N4UART0_CTSn/GP1[28]N7UART0_DCDn/GPMC_A[18]/GPMC_A[23]/GP1[18]N5UART1_TXD/GPMC_A[25]/GPMC_A[19]N2UART1_RXD/GPMC_A[26]/GPMC_A[20]N1UART1_RTSn/GPMC_A[14]/GPMC_A[18]/GP1[25]M2UART1_CTSn/GPMC_A[13]/GPMC_A[17]/GP1[26]L3UART2_TXDL2UART2_RXDM1UART2_RTSn/GPMC_A[15]/GPMC_A[26]/GP1[23]L9UART2_CTSn/GPMC_A[16]/GPMC_A[25]/GP1[24]K7EVM_3V3I2C[0]_SCLN32I2C[0]_SDAN33R20I2C[1]_SCLN342.2KR142.2KMMC_POWMMC_CLKMMC_CMDMMC_SD_WPMMC_SD_CDUART0_TXDUART0_RXDUART0_RINUART0_RTSNUART0_DTRNUART0_DSRNUART0_CTSNUART0_DCDNUART1_TXDUART1_RXDUART1_RTSNUART1_CTSNUART2_TXDUART2_RXDUART2_RTSNUART2_CTSNR2892.2KEVM_3V3MMC_POW 30MMC_CLK 30MMC_CMD 30MMC_DAT0 30MMC_DAT1 30MMC_DAT2 30MMC_DAT3 30R2792.2KMMC_SD_WP 30MMC_SD_CD 30UART0_TXD 41UART0_RXD 41UART0_RIN 42UART0_RTSN 41UART0_DTRN 42UART0_DSRN 42UART0_CTSN 42UART0_DCDN 42UART1_TXD 41UART1_RXD 29,41UART1_RTSN 42UART1_CTSN 42UART2_TXD 28,42UART2_RXD 28,41UART2_RTSN 42UART2_CTSN 42DCBNETRA_3IIC0_SCL 26,27,36,43,45IIC0_SDA 26,27,36,43,45IIC1_SCL 27,43IIC1_SDA 27,43ASPECTRUM DIGITAL INCORPORATEDAEVM_3V3Title:NETRA EVM with DIMM MEMORYEVM_3V3 2,5,6,11,13,14,15,18,21,22,23,24,26,27,28,29,30,31,32,33,34,35,36,37,38,39,41,43,44,45,46,48,49,50,51Page Contents:NETRA SERIAL I/OSize: BDWG NO513832-0001Revision:ADate:Wednesday, December 01, 2010 Sheet 3 o f 5254321