ZQA SOLE UMA SYSTEM DIAGRAM - Data Sheet Gadget
ZQA SOLE UMA SYSTEM DIAGRAM - Data Sheet Gadget
ZQA SOLE UMA SYSTEM DIAGRAM - Data Sheet Gadget
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5<br />
REQUIRED STRAPS<br />
SB820M is<br />
supported<br />
Gen.1 mode<br />
only.<br />
4<br />
For internal clock GEN.<br />
+3V_S5 +3V +3V +3V<br />
+3V +3V_S5 +3V_S5<br />
+3V_S5<br />
3<br />
2<br />
OVERLAP COMMON PADS WHERE<br />
POSSIBLE FOR DUAL-OP RESISTORS.<br />
1<br />
14<br />
D<br />
D<br />
R293<br />
*10K_4<br />
R304<br />
*10K_4<br />
R306<br />
*10K_4<br />
R310<br />
*10K_4<br />
R308<br />
10K_4<br />
R289<br />
10K_4<br />
R273<br />
*10K_4<br />
R272<br />
*10K_4<br />
[11] GPIO199<br />
[11] GPIO200<br />
[10] LPC_CLK1<br />
[10] LPC_CLK0<br />
[10] PCI_CLK4<br />
[10] PCI_CLK3<br />
[10] PCI_CLK2<br />
[10] PCI_CLK1<br />
[11] ACZ_SDOUT<br />
1<br />
1<br />
R292<br />
10K_4<br />
R303<br />
10K_4<br />
R305<br />
10K_4<br />
R309<br />
10K_4<br />
R307<br />
*10K_4<br />
R282<br />
10K_4<br />
2<br />
R286<br />
2.2K_4<br />
2<br />
R285<br />
*2.2K_4<br />
AZ_SDOUT<br />
PCI_CLK1<br />
PCI_CLK2<br />
PCI_CLK3<br />
PCI_CLK4<br />
LPC_CLK0<br />
LPC_CLK1<br />
GPIO200 GPIO199<br />
C<br />
PULL<br />
HIGH<br />
LOW POWER<br />
MODE<br />
ALLOW<br />
PCIE Gen2<br />
Watchdog<br />
Timer Enable<br />
USE<br />
DEBUG<br />
STRAPS<br />
non_Fusion<br />
CLOCK MODE<br />
DEFAULT<br />
EC<br />
ENABLED<br />
CLKGEN<br />
ENABLED<br />
DEFAULT<br />
H, H=Reserved<br />
H, L=SPI ROM<br />
C<br />
PULL<br />
LOW<br />
PERFORMANCE<br />
MODE<br />
DEFAULT<br />
FORCE<br />
PCIE Gen1<br />
Watchdog<br />
Timer Disable<br />
IGNORE<br />
DEBUG<br />
STRAPS<br />
DEFAULT DEFAULT DEFAULT<br />
Fusion<br />
CLOCK MODE<br />
EC<br />
DISABLED<br />
DEFAULT<br />
CLKGEN<br />
DISABLED<br />
L, H=LPC ROM DEFAULT<br />
L, L=FWH ROM<br />
internal have<br />
pull Hi 10K<br />
DEBUG STRAPS<br />
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]<br />
B<br />
[10]<br />
[10]<br />
[10]<br />
[10]<br />
[10]<br />
AD23<br />
AD24<br />
AD25<br />
AD26<br />
AD27<br />
2 1<br />
R43<br />
*2.2K_4<br />
2 1<br />
R45<br />
*2.2K_4<br />
1<br />
2<br />
R36<br />
*2.2K_4<br />
1<br />
2<br />
R41<br />
*2.2K_4<br />
1<br />
2<br />
R44<br />
*2.2K_4<br />
+3V_S5<br />
R17<br />
10K_4<br />
C16<br />
*2.2u/6.3V_6<br />
NB_PWRGD_IN:<br />
RS880/RX881 = 1.8V;<br />
Do NOT share it with SB_PWRGD when use Internal Clk Gen (Need SB PLL initialize firstly)<br />
R19<br />
+1.8V<br />
*Short_4<br />
SB_PWRGD_IN<br />
SB_PWRGD_IN [11]<br />
NB/SB POWER GOOD CIRCUIT<br />
B<br />
PULL<br />
HIGH<br />
PCI_AD27<br />
USE PCI<br />
PLL<br />
DEFAULT<br />
PCI_AD26<br />
DISABLE ILA<br />
AUTORUN<br />
DEFAULT<br />
PCI_AD25<br />
USE FC<br />
PLL<br />
DEFAULT<br />
PCI_AD24<br />
USE DEFAULT<br />
PCIE STRAPS<br />
DEFAULT<br />
PCI_AD23<br />
DISABLE PCI<br />
MEM BOOT<br />
DEFAULT<br />
[34,37,39] CPU_COREPG<br />
[34] PWROK_EC<br />
D2<br />
D3<br />
*BAS316<br />
BAS316<br />
U2<br />
1<br />
NC VCC 5<br />
2<br />
A<br />
3<br />
GND Y 4<br />
*NL17SZ17DFT2G<br />
SOT-353<br />
C17<br />
R20<br />
*.1u/10V_4<br />
*33_4<br />
NB_PWRGD_IN [8,11]<br />
A<br />
PULL<br />
LOW<br />
BYPASS<br />
PCI PLL<br />
ENABLE ILA<br />
AUTORUN<br />
BYPASS FC<br />
PLL<br />
USE EEPROM<br />
PCIE STRAPS<br />
ENABLE PCI<br />
MEM BOOT<br />
AL17SZ17000<br />
ALUC1G17000<br />
IC(5P) NL17SZ17DFT2G(SOT-353)<br />
IC OTHER(5P) SN74AUC1G17DBVR(SOT23-5)<br />
SOT-353<br />
SOT23-5<br />
A<br />
http://hobi-elektronika.net<br />
Size<br />
<br />
<br />
Document Number<br />
SB820-STRAPS<br />
Rev<br />
1A<br />
5<br />
4<br />
3<br />
2<br />
Date: Monday, May 31, 2010<br />
<strong>Sheet</strong> 14 of<br />
48<br />
1
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