TRIUMPH TECHNOLOGY Javad Ashjaee

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<strong>TRIUMPH</strong> Chip (CPU/FPU/MEM/I-O) • 32-bit CPU compliant with the SPARC V8 architecture • 64-bit FPU compliant with IEEE 754 standard • Up to 220 MHz CPU/FPU clock speed • 128 KB instruction/data cache size • Memory Management Unit • 4 MB internal RAM • Up to 9 UART’s • Up to 5 advanced SPI-s (four-wire serial with master/slave mode). • Up to 3 CAN 2.0 controllers • Up to 21 PWM (pulse-width modulation) outputs • Up to 67 general purpose input/output pins • External bus supported up to 512 MB SDRAM, 128 MB SRAM, 128 MB PROM and memory mapped I/O devices 12
OEM BOARDS • G2: GPS + Galileo • G3: GPS + Galileo + GLONASS • D: GPS L1/L2 + Galileo E1 • T: GPS L1/L2/L5, GLO. GAL. Dual Freq. Galileo is optional in all boards 13
Page 1 and 2: TRIUMPH TECHNOLOGY Javad Ashjaee JA
Page 3 and 4: TRIUMPH Technology At the heart of
Page 5 and 6: TRIUMPH Chip (GNSS DSP) • 216 cha
Page 7 and 8: TRIUMPH Chip (GNSS DSP) 48 PLC (96
Page 9 and 10: TRIUMPH Chip (GNSS DSP) Fast Acquis
Page 11: TRIUMPH Chip (Viterbi Decoder) •
Page 15 and 16: TR-G2 16 each of GPS L1, Galileo E1
Page 17 and 18: DUO BOARDS Two synchronized sets of
Page 19 and 20: ALPHA SERIES • Internal battery
Page 21 and 22: SIGMA SERIES • Internal battery
Page 23 and 24: GISmore Precision GNSS antenna GSM
Page 25 and 26: TRIUMPH-1 25
Page 27 and 28: GNSS RF and Communication Board wit
Page 29 and 30: FUNCTIONALITY 29
Page 31 and 32: TRIUMPH-4X 4 x 4 ALL WILL DRIVE RTK
Page 33 and 34: RTK Caddy & Umbrella To make handli
Page 35 and 36: TRIUMPH-4X 35
Page 37 and 38: GNSS RF and Communication Board wit
Page 39 and 40: Antennas GrAnt TriAnt AirAnt 39
Page 41 and 42: Antenna + GNSS TyrAnt - G2 TyrAnt -
Page 43 and 44: SOFTWARE •Justin: A comprehensive
Page 45 and 46: GLONASS ISSUES Why sometimes GLONAS
Page 47 and 48: RECEIVER BIASES Receiver biases can
Page 49 and 50: GLONASS BIASES • Some manufacture
Page 51 and 52: Triumph Palace The new generation o

TRIUMPH TECHNOLOGY Javad Ashjaee

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