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Massive Parallel Programing (MPP) of kMC with graphic cards (GPUs) BEDMOD Workshop, March 26 - 29, 2012, Dresden 24 Weigel, Int. J. of Mod. Phys. C (2011) Tesla: - 30 multiprocessors - 8 processors each 240 cores Fermi: - 14-16 multiprocessors - 32 processors each 512 cores Member of the Helmholtz Association Karl-Heinz Heinig | Institute Ion-Beam Physics and Materials Research | http://www.hzdr.de
BEDMOD Workshop, March 26 - 29, 2012, Dresden Registers: each multiprocessor is equipped with several thousand registers with local, zero-latency access; Shared memory: processors of a multiprocessor have of on chip, small latency shared memory; L1 and L2 caches: 16/48 kB L1 cache and 768 kB L2 cache; Global memory: large amount (currently up to 6 GB) of memory on separate DRAM chips with access from every thread on each multiprocessor with a latency of several hundred clock cycles; Constant and texture memory: read-only memories of the same speed as global memory, but cached; Host memory: cannot be accessed from inside GPU functions, relatively slow transfers. 25 Member of the Helmholtz Association Karl-Heinz Heinig | Institute Ion-Beam Physics and Materials Research | http://www.hzdr.de
Page 1 and 2: Supported by DFG, BMBF, DAAD Kineti
Page 3 and 4: Bit-coded, cellular automaton based
Page 5 and 6: Bit-coded, cellular automaton based
Page 7 and 8: Application #1 (European FP6 projec
Page 9 and 10: Application #1 (European FP6 projec
Page 11 and 12: BEDMOD Workshop, March 26 - 29, 201
Page 13 and 14: Co + Focused ion beam internal ener
Page 15 and 16: Co + Focused ion beam surface FF Co
Page 17 and 18: Beyond standard lattice kMC ? a) Ma
Page 19 and 20: Fine-grained lattice kMC for silico
Page 21 and 22: Fine-grained lattice kMC for silico
Page 23: Massive Parallel Programing (MPP) o
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Page 29 and 30: hierarchical level 1: parallelisati
Page 31 and 32: Application #3 (int. BMBF project):
Page 33 and 34: Application #3 (int. BMBF project):
Page 35 and 36: Comparison E5530 @ 2.4 GHz vs NVIDI

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