Felice Pantaleo - Desy

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Results - Throughput The throughput behaviour for a varying number of events inside a packet is a typical many-core device behaviour: • constant time to process a varying number of events, activating more SMs as the packet size increases • discrete oscillations due to the discrete nature of the GPU • saturation plateau (1.4GB/s and 2.7GB/s ) The right choice of packet dimension is not unique. It depends on the maximum latency we don't want to exceed and on the input rate of events. Considering that the maximum rate per subdetector (@10MHz particles rate) for NA62 experiment is ~500MB/s, I would consider the throughput test PASSED felice.pantaleo@cern.ch 48
Results - Latency Latency pretty stable wrt event size. • A lower number of event inside a package is better to achieve a low latency. • A larger number of event guarantees a better performance and a lower overhead. The choice of the packet size depends on the technical requirements. 15/10/2012 felice.pantaleo@cern.ch 49
Page 1 and 2: Use of GPUs for trigger application
Page 3 and 4: Introduction
Page 5 and 6: Generic Detector Structure 15/10/20
Page 7 and 8: Low Level Trigger • Time needed f
Page 9 and 10: Current Proposals: steps beyond Man
Page 11 and 12: Opportunities for HEP experiments
Page 13 and 14: GPUs (1/2) • Exceptional raw powe
Page 15 and 16: CUDA - Kepler Architecture • SMX
Page 17 and 18: ALICE High Level Trigger Thanks to
Page 19 and 20: ALICE Detector ALICE is one of the
Page 21 and 22: ALICE TPC • TPC clusters of a hea
Page 23 and 24: ALICE HLT • Alice HLT tracker div
Page 25 and 26: Neighbors Finding 15/10/2012 felice
Page 27 and 28: Tracklet reconstruction • The alg
Page 29 and 30: Tracklet construction 15/10/2012 fe
Page 31 and 32: ALICE GPU Tracker Screenshot of ALI
Page 33 and 34: K + → π + νν in the Standard M
Page 35 and 36: NA62 Trigger RICH MUV CEDAR STRAWS
Page 37 and 38: Data Flow Max time O(100us) Receive
Page 39 and 40: RICH • ~17 m RICH • 1 atm Neon
Page 41 and 42: Crawford Algorithm Consider a circl
Page 43 and 44: GPU grid organization threadIdx.y =
Page 45 and 46: NA62 RICH Tests
Page 47: Hardware configuration (2/2) Second
Page 51 and 52: NA62 CHOD Level0 Trigger
Page 53 and 54: CHOD - Kernel • Assuming the cond
Page 55 and 56: NA62 CHOD Tests
Page 57 and 58: Kernel 64x64 Texture memory is slow
Page 59 and 60: Throughput Saturation at ~3GB/s (I/
Page 61 and 62: Conclusion • I will test a comple
Page 63 and 64: Questions?

Felice Pantaleo - Desy

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