DDI0419C_arm_architecture_v6m_reference_manual

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ARMv6-M CoreSight Infrastructure IDs See the CoreSight Architecture Specification for the complete description of the CoreSight management registers A.1.1 Architectural requirements for the Software Lock mechanism The LAR and LSR registers shown in Table A-2 on page AppxA-361 provide the Software Lock mechanism for a CoreSight component. Access to these registers is defined independently for each interface to a component. This means that support for the Software Lock mechanism is defined independently for each interface. For a particular interface: • if the Software Lock is supported, the LAR and LSR must be accessible using that interface, and: — LSR is read-only — LAR is write-only. • if the Software Lock is not supported, the LAR and LSR locations are RAZ/WI. ARM recommends that the Software Lock is not supported for accesses from the DAP. For the ARMv6-M architecture and the ARMv7-M architecture profile, it is IMPLEMENTATION DEFINED whether the Software Lock is supported for accesses from the DAP. In addition, for ARMv6-M, the behavior of software accesses to a CoreSight component from the processor is IMPLEMENTATION DEFINED. AppxA-362 Copyright © 2007-2008, 2010 ARM Limited. All rights reserved. ARM DDI 0419C Non-Confidential ID092410
Appendix B Deprecated and Obsolete Features This appendix identifies deprecated and obsolete features in the ARMv6-M architecture. It contains the following sections: • Deprecated features of the ARMv6-M architecture on page AppxB-364 • Obsolete features of the ARMv6-M architecture on page AppxB-365. ARM DDI 0419C Copyright © 2007-2008, 2010 ARM Limited. All rights reserved. AppxB-363 ID092410 Non-Confidential
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ARMv6-M Architecture Reference Manu
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This document is Non-Confidential b
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Contents ARMv6-M Architecture Refer
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Contents Chapter B2 System Memory M
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List of Tables ARMv6-M Architecture
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List of Tables Table C1-7 Debug ste
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List of Figures ARMv6-M Architectur
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Preface This preface introduces the
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Using this manual The information i
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Conventions This manual employs typ
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Feedback ARM welcomes feedback on i
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Part A Application Level Architectu
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Introduction A1.1 About the ARM arc
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Introduction A1-28 Copyright © 200
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Application Level Programmers’ Mo
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ARM Architecture Memory Model A3.1
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ARM Architecture Memory Model Instr
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ARM Architecture Memory Model The o
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ARM Architecture Memory Model incoh
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ARM Architecture Memory Model An im
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ARM Architecture Memory Model Side
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ARM Architecture Memory Model Data
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ARM Architecture Memory Model In a
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The ARMv6-M Instruction Set A4.1 Ab
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The ARMv6-M Instruction Set A4.2 Un
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The ARMv6-M Instruction Set A4.3 Br
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The ARMv6-M Instruction Set Mnemoni
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The ARMv6-M Instruction Set A4.5 St
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The ARMv6-M Instruction Set A4.6.2
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The ARMv6-M Instruction Set A4.8 Mi
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The ARMv6-M Instruction Set A4-80 C
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The Thumb Instruction Set Encoding
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Thumb Instruction Details A6.1 Form
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Thumb Instruction Details • The l
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Thumb Instruction Details A6.2 Stan
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Thumb Instruction Details A6.3.1 Ps
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Thumb Instruction Details (result,
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Thumb Instruction Details A6.6 Hint
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Thumb Instruction Details A6.7.1 AD
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Thumb Instruction Details Operation
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Thumb Instruction Details A6.7.7 AN
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Thumb Instruction Details A6.7.9 AS
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Thumb Instruction Details A6.7.12 B
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Thumb Instruction Details A6.7.14 B
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Thumb Instruction Details A6.7.16 C
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Thumb Instruction Details A6.7.20 C
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Thumb Instruction Details A6.7.22 D
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Thumb Instruction Details A6.7.24 I
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Thumb Instruction Details A6.7.29 L
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Thumb Instruction Details A6.7.39 M
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Thumb Instruction Details A6.7.42 M
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Thumb Instruction Details A6.7.46 N
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Thumb Instruction Details A6.7.48 O
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Thumb Instruction Details A6.7.51 R
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Thumb Instruction Details A6.7.57 S
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Thumb Instruction Details A6.7.71 T
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Thumb Instruction Details A6.7.74 U
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Thumb Instruction Details A6.7.76 W
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Thumb Instruction Details A6-200 Co
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Chapter B1 System Level Programmers
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B1.2 About the ARMv6-M memory mappe
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Mode Privilege Stack pointer Typica
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System Level Programmers’ Model
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B1.4 Registers System Level Program
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The IPSR System Level Programmers
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B1.4.4 The special-purpose CONTROL
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R[] - assignment form // ==========
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System Level Programmers’ Model H
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Note System Level Programmers’ Mo
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for (i=2, i= 2 && n = 16 then r = (
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The ARMv6-M architecture uses a ful
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Note • IRQ behavior also applies
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System Level Programmers’ Model I
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System Level Programmers’ Model p
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System Level Programmers’ Model I
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Note System Level Programmers’ Mo
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Fault Cause System Level Programmer
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Fault cause Occurrence Behavior VEC
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System Level Programmers’ Model W
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System Level Programmers’ Model
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Chapter B2 System Memory Model This
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B2.2 Declarations and support funct
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memattrs.innerattrs = '01'; memattr
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B2.3 Memory accesses System Memory
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case perms.ap of when '000' fault =
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B2.5 Barrier support for system cor
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Chapter B3 System Address Map This
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System Address Map See Chapter A2 A
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Note System Address Map This is dif
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B3.2.1 About the System Control Blo
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Table B3-5 shows the CPUID Base Reg
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Bits Type Name Function [21] - - Re
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Table B3-8 shows the AIRCR bit assi
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Bits Name Function System Address M
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Table B3-11 shows the SHPR2 bit ass
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B3.3 The system timer, SysTick Syst
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B3.3.3 SysTick Control and Status R
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Table B3-15 shows the SYST_RVR bit
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B3.4 Nested Vectored Interrupt Cont
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clearPend = ExceptionIN(INTNUM) ||
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B3.4.4 Interrupt Clear Enable Regis
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B3.4.6 Interrupt Clear-Pending Regi
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B3.5 Protected Memory System Archit
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if MPU_CTRL.HFNMIENA == '1' then UN
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B3.5.2 Register support for PMSAv6
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B3.5.4 MPU Control Register, MPU_CT
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Table B3-27 shows the MPU_RNR bit a
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Figure B3-22 shows the MPU_RASR bit
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The AP bits, AP[2:0], are used for
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Chapter B4 ARMv6-M System Instructi
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B4.2 ARMv6-M system instruction des
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Notes Privilege Any unprivileged co
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Exceptions None. Notes Privilege An
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Page 313: Part C Debug Architecture
Page 316 and 317: ARMv6-M Debug C1.1 Introduction to
Page 318 and 319: ARMv6-M Debug C1.2 The Debug Access
Page 320 and 321: ARMv6-M Debug C1.3 Overview of the
Page 322 and 323: ARMv6-M Debug Figure C1-1 on page C
Page 324 and 325: ARMv6-M Debug C1.5 Debug event beha
Page 326 and 327: ARMv6-M Debug DHCSR write a C_HALT
Page 328 and 329: ARMv6-M Debug C1.6 Debug register s
Page 330 and 331: ARMv6-M Debug C1.6.2 Debug Fault St
Page 332 and 333: ARMv6-M Debug 31 26 25 24 23 20 19
Page 334 and 335: ARMv6-M Debug Bits Name Access Func
Page 336 and 337: ARMv6-M Debug Table C1-12 shows the
Page 338 and 339: ARMv6-M Debug Use of DCRSR and DCRD
Page 340 and 341: ARMv6-M Debug The conditions for a
Page 342 and 343: ARMv6-M Debug DWT_COMPx contains th
Page 344 and 345: ARMv6-M Debug case DWT_FUNCTION[N].
Page 346 and 347: ARMv6-M Debug Control register, DWT
Page 348 and 349: ARMv6-M Debug Attributes See Table
Page 350 and 351: ARMv6-M Debug Bits Name TYPE Functi
Page 352 and 353: ARMv6-M Debug C1.8.2 BPU register s
Page 354 and 355: ARMv6-M Debug Breakpoint Comparator
Page 356 and 357: ARMv6-M Debug C1-356 Copyright © 2
Page 359 and 360: Appendix A ARMv6-M CoreSight Infras
Page 361: Address offset 0xFDC 0x00000000 PID
Page 365 and 366: B.2 Obsolete features of the ARMv6-
Page 367 and 368: Appendix C ARMv7-M Differences This
Page 369 and 370: C.2 About the ARMv6-M and ARMv7-M a
Page 371 and 372: C.4 Programmers’ model support AR
Page 373 and 374: C.5 Memory model support ARMv7-M Di
Page 375 and 376: C.6 System Control Space register s
Page 377 and 378: C.7 Debug support ARMv7-M Differenc
Page 379 and 380: Appendix D Legacy Instruction Mnemo
Page 381 and 382: Pre-UAL Thumb syntax Equivalent UAL
Page 383 and 384: Pre-UAL Thumb syntax Equivalent UAL
Page 385 and 386: Appendix E Pseudocode Definition Th
Page 387 and 388: Pseudocode Definition If there are
Page 389 and 390: E.3 Data types This section describ
Page 391 and 392: E.3.7 Lists Pseudocode Definition A
Page 393 and 394: E.4 Expressions This section descri
Page 395 and 396: E.5 Operators and built-in function
Page 397 and 398: Pseudocode Definition Encoding diag
Page 399 and 400: Unary plus, minus and absolute valu
Page 401 and 402: E.6 Statements and program structur
Page 403 and 404: elsif then ... else ... The
Page 405 and 406: Procedure and function definitions
Page 407 and 408: E.7.7 ConditionPassed() This functi
Page 409 and 410: Appendix F Pseudocode Index This ap
Page 411 and 412: Operator Meaning See // Introduces
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Operator Meaning See repeat ... unt
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ClearEventRegister() Clear the Even
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InstrAddressMatch() DWT comparator
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SCS_UpdateStatusRegs() On taking an
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Appendix G Register Index This appe
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G.2 Memory mapped system registers
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Glossary AAPCS Procedure Call Stand
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Glossary Cache miss Is a memory acc
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Glossary IMPLEMENTATION DEFINED Mea
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Glossary Pseudo-instruction UAL ass
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Glossary Should-Be-Zero fields (SBZ
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UNK/SBZP field UNKNOWN on reads, Sh
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