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Beyond Flat Page Tables Assume most of PageTable is empty How to translate addresses? Multi-level PageTable PTBR 10 bits PDEntry Page Directory * x86 does exactly this 10 bits 10 bits 2 vaddr PTEntry Page Table Word Page 14
Page Table Review x86 Example: 2 level page tables, assume… 32 bit vaddr, 32 bit paddr 4k PDir, 4k PTables, 4k Pages Q:How many bits for a physical page number? A: 20 Q: What is stored in each PageTableEntry? A: ppn, valid/dirty/r/w/x/… Q: What is stored in each PageDirEntry? A: ppn, valid/?/… Q: How many entries in a PageDirectory? A: 1024 four-byte PDEs Q: How many entires in each PageTable? A: 1024 four-byte PTEs PTBR PDE PDE PDE PDE PTE PTE PTE PTE 15
Page 1 and 2: P & H Chapter 5.4 Virtual Memory 3
Page 3 and 4: Virtual Memory 3
Page 5 and 6: memory PC new pc Big Picture: (Virt
Page 7 and 8: Processor & Memory CPU address/data
Page 9 and 10: Multiple Processes Q: Can we reloca
Page 11 and 12: All problems in computer science ca
Page 13: Performance Review Virtual Memory S
Page 17 and 18: Performance Review Virtual Memory S
Page 19 and 20: Translation Lookaside Buffer (TLB)
Page 21 and 22: CPU A TLB in the Memory Hierarchy T
Page 23 and 24: Translation Lookaside Buffers (TLBs
Page 25 and 26: Virtual Memory meets Caching Virtua
Page 27 and 28: CPU CPU Virtual vs. Physical Caches
Page 29 and 30: Indexing vs. Tagging 29
Page 31 and 32: Summary of Caches/TLBs/VM Caches, V
Page 33: Summary of Cache Design Parameters

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