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This provides the FADEC system with back up electrical<br />

power in the event of a HMU integral alternator failure<br />

thus preventing loss of the PRI mode. Placing the B/U<br />

PWR swit<strong>ch</strong> to OFF will reduce operating time on the<br />

FADEC circuitry. The B/U PWR swit<strong>ch</strong> should always be<br />

ON during engine operation.<br />

d. OSPD 1, 2 Swit<strong>ch</strong>. The Over Speed test swit<strong>ch</strong> is<br />

a three position swit<strong>ch</strong> used to test the FADEC overspeed<br />

system. In the event of a NR overspeed of 114.8<br />

percent, FADEC reduces fuel flow to a ground idle condition.<br />

The system remains activated until the overspeed<br />

condition no longer exists, and will re-activate as soon as<br />

an overspeed re-occurs. The system contains provisions<br />

to inhibit overspeed trip command if the other engine has<br />

experienced a overspeed trip condition. To prevent inadvertent<br />

operation during flight, this test is locked out if NR<br />

is greater than 81.3 percent. When per<strong>for</strong>ming an overspeed<br />

test with the engine running and the RRPM<br />

79.01%, pressing the test swit<strong>ch</strong> to 1 or 2, lowers the<br />

overspeed trip threshold to 79.01% NR. At this time the<br />

system senses an overspeed and reduces the fuel flow.<br />

e. LOAD SHARE, PTIT/TRQ Swit<strong>ch</strong>. The primary<br />

FADEC system provides pilot selectable engine torque<br />

PTIT mat<strong>ch</strong>ing to govern the engines. Torque mat<strong>ch</strong>ing<br />

is normally the preferred option. The selected parameter<br />

is constantly compared between the two engines until the<br />

RRPM stabilizes at datum figure. The PTIT option may<br />

be used when one engine is running hot. N1 mat<strong>ch</strong>ing is<br />

engaged automatically if the selected mat<strong>ch</strong>ing mode<br />

fails.<br />

f. ENG START Swit<strong>ch</strong>. It is a three position swit<strong>ch</strong>,<br />

spring loaded to the center position, labeled 1 and 2. It is<br />

used to commence the start sequence on the respective<br />

engine.<br />

2-3-33. DECU Unit. 714A<br />

The two airframe mounted DECU’s, one <strong>for</strong> ea<strong>ch</strong> engine,<br />

contain the primary and reversionary mode electronics.<br />

The DECUs are located on the left (sta 390) and right (sta<br />

4<strong>10</strong>) side of the aft cabin.<br />

Figure 2-3-6. FADEC Panel 714A<br />

2-3-34. BIT. 714A<br />

TM 1-<strong>1520</strong>-<strong>240</strong>-<strong>10</strong><br />

The DECU contains a two-digit BIT display. When active,<br />

the display indicates the operating status of the FADEC<br />

system and power assurance test results. A complete list<br />

of the FADEC BIT fault codes are located at Table 2-3-1.<br />

The fault monitoring carried out by the DECU consists of:<br />

a. Power up tests.<br />

b. Fault tests designed to discover dormant faults.<br />

c. A set of repeated monitoring tests to detect faults<br />

occurring during normal operation.<br />

Fault in<strong>for</strong>mation <strong>for</strong> the previous or current engine cycle<br />

can be seen on the DECU BIT display. The last engine<br />

cycle is reset on the first occurrence of start mode and not<br />

on engine shutdown. During engine shutdown (when<br />

ECL is at STOP or N1 is less than <strong>10</strong> percent) faults are<br />

not stored. Fault indications are stored in the DECU and<br />

are retained throughout the life of the control unit. However,<br />

fault in<strong>for</strong>mation prior to the previous cycle can only<br />

be accessed with specialized test equipment. During engine<br />

start the DECU BIT displays 88 <strong>for</strong> satisfactory test<br />

or if the test fails, a fault code. Faults are classified as<br />

either “HARD” or “SOFT”. In primary mode a hard fault<br />

will cause the FADEC to transfer to Reversionary , while<br />

in Reversionary a hard fault will cause the FADEC to “fail<br />

fixed” to a constant power condition. If a hard fault occurs<br />

in Primary after a hard fault exists in reversionary then<br />

the primary will fail fixed. In the event of a soft fault the<br />

FADEC will remain in the mode it was in prior to the fault<br />

but there may be some degradation or redundancy. All<br />

soft faults are less severe than a hard fault since the<br />

FADEC will not swit<strong>ch</strong> modes due to a soft fault.<br />

The activation of the BIT display is dependent upon the<br />

position of the ECL as follows:<br />

a. With the ECL at STOP, the fault in<strong>for</strong>mation <strong>for</strong><br />

the last engine cycle and current faults are displayed.<br />

b. When the ECL is positioned at GROUND only<br />

current faults are displayed.<br />

c. When the ECL is positioned at FLIGHT the display<br />

will be turned off except as required <strong>for</strong> Power Assurance<br />

Test (PAT).<br />

2-3-35. Starting in Primary Mode. 714A<br />

CAUTION<br />

The (P3) compressor pressure signal line<br />

going to the DECU contains a <strong>manual</strong>ly<br />

operated moisture drain valve. This valve<br />

shall not be drained while the engine is<br />

running.<br />

NOTE<br />

Engine may not start if REV fail caution is<br />

illuminated.<br />

In primary mode, engine start is initiated with the ECL in<br />

the GND position. Select and hold the respective ENG<br />

START swit<strong>ch</strong> and allow the engine to accelerate to <strong>10</strong><br />

2-3-9

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