Busser - Valle´s Bedste Hjemmeside.

Busser
Se senere
Acknoledge kan opfattes som det 9. bit, hvor slaven trækker dataledningen lav.
Der findes større kredse, hvor det er nødvendigt at sende 2 adressebytes.
Det er ikke nødvendigt, at opretholde en konstant klockrate. Derfor kan processoren godt servicere
interruptrutiner undervejs.
Se evt. tysk kodegenerator.
Der findes ny protokol med 10 bit adressing og op til 400 Kbit / sek.
Her et par gaflede tekster, der på fin vis forklarer baggrunden for IIC-protokollen:
I2C Baggrund
I2C, or 2-wire
communication, is a form of
synchronous serial
communication that was
developed by Phillips
Semiconductor. Two wires,
serial data (SDA) and serial
clock (SCL), carry information
between the devices
connected to the bus. Each
byte put on the SDA line
must be 8-bits long, but the
number of bytes transmitter
per transfer is unrestricted.
Term
Transmitter
Receiver
Master
Slave
Definition
The device which is currently sending data
to the buss.
The device which is currently receiving
data from the buss.
The device which initiates a transfer,
generates clock signals and terminates a
transfer. In our case, this is always the
BS2.
The device addressed by the MASTER.
Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a pull-up
resistor (usually between 4.7k and 10k). When the bus is free, both lines are high. Each device
is recognized by a unique address (whether it's an EEPROM, RTC or I/O expander) and can
operate as either a transmitter or receiver. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when performing data transfers. The BASIC Stamp
cannot operate as an I2C slave device, however. The table below defines I2C terminology:
All I2C communication must begin with a START condition and terminate with a STOP
condition. START and STOP conditions are generated by the master and are defined as:
/: Valle Thorø
Side 15 af 43