CISC, RISC, and DSP Microprocessors

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RISC Processors circa 1984 • Academic research topic • 12-16 instructions • Single-cycle execute • No microcode! 4/6/00 CISC, RISC, and DSP D.L. Jones 12
Arguments Advanced for RISC • Small, heavily optimized instruction set executable in single short cycle • All instructions same size • No microcode = faster execution • Extra speed more than offsets increased code size, reduced functionality • Better compiler target 4/6/00 CISC, RISC, and DSP D.L. Jones 13
Page 1 and 2: CISC, RISC, and DSP Microprocessors
Page 3 and 4: Goals for this Lecture • Understa
Page 5 and 6: • Many addressing modes • Relat
Page 7 and 8: • Wider buses for high-performanc
Page 9 and 10: • Harvard architecture: separate
Page 11: • Meanwhile, there was RISC ... 4
Page 15 and 16: Arguments Advanced for CISC • Few
Page 17 and 18: CISC Processors circa 1999 • Cloc
Page 19 and 20: • Very expensive (100s of dollars
Page 21 and 22: DSP Microprocessors circa 1999 •
Page 23 and 24: Questions • If CISC and RISC have
Page 25 and 26: • Market needs in DSP embedded sy
Page 27 and 28: Myth and Reality in RISC vs CISC
Page 29 and 30: The Real Answer (Opinion!) • The
Page 31 and 32: Implications • These curves STRON
Page 33 and 34: • It wasn’t about RISC at all,
Page 35 and 36: Even More Transistors ... • Then
Page 37 and 38: • This pushed CISC designs to be
Page 39 and 40: Question • Are there other embedd
Page 41 and 42: Future of DSP Microprocessors • D

CISC, RISC, and DSP Microprocessors

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