Systems Reference Library IBM 1800 System Summary

SYSTEM UN ITS AND FEATURES
PROCESSOR- CONTROLLER
Two processor- controllers are available : the IBM
1801 and the IBM 1802 .(Figure I), Each has tell
models based on speed and s ize of cor e storage.
(Core storage si ze may be expanded w ith the addition
of a n IBIVl 1803 Core Storage Unit.) T he 1801
has no provision for magnetic tape, wh il e the 1802
includes the Tape Control Unit [or the IBM 2401/2402
IVl agnetic T a pe Units .
The processor- controllers are fixed-word-Iength.
binary computers. Five core storage s izes (4, 096;
8,192; 16,384 ; 24 , 576; or 32 , 768 words of 18 bits
each) with core storage cycle times of 2 or 4 m icroseconds
(u see) are available. With the addition of
an IBI'vJ 1803 Core Storage Unit, four additional
system core storage s izes (40,960 ; 49,152; 57,344;
and G5, 536 words of 18 b its each) with core storage
cycle t ime of 2. 25 Jlsec are a lso available. One of
the 18 bits in a core storage word is used for
stor age protection and one bit is used for parity
checking. The r emain ing 16 bits in each core
storage word a r e data bits .
These features are standard on a ll processorcontrollers:
1. Data channels .
2. Index r egisters .
3. Indirect addreSSing.
4 . Interval timers .
5 . Operation mon itor.
6, Interrupt.
7, Parity a nd storage protect.
Data Channel: T he high- speed input/output channe l
enables asynchronous I/o unit operations. In these
operations the use of core storage to read or store
data affects the ma in program execution on ly by a
cycle delay per word (Ull operation called "cycle
steali ng") . The feature enables input/output operat
ions at rates up to 500,000 words (8, ODD, 00 0 bits)
per second with the two- microsecond core storage.
Three data channe ls are pr ovided as standard
features; twelve addit ional data channels are a vailable
as special features.
Index Registers: Three index registers provide a
means of saving program steps, core storage, and
computer processing t ime. Indexing an instruction
callses the contents of an index register to be addcd
to the instruction address to form the desired effective
address (or that instruction . The 1800 instruction
set includes instructions to load, store, and
modify index registers.
Indirect AddreSS ing: Indirect addreSSing alters
normal e ffective addr ess generation by us ing the
value stored in the core storage location defincd
by the address (or address + index register if
specified) as the effective address, instead of
directly using the address (or addr ess + index
register if specified) as the effective address.
• Figure I. 180 I or 1802 Processor-Controller
Interva l Timers : Three interval timers are
provided to supply e lapsed-time information to
the program. Each timer has one permanent
time base which can be selected from the follow
ing time base periods:
•
System Un its and Features :1
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