DRAM and Memory System Trends - IBM Research

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Improving Signal Integrity With On-Die Termination Memory Controller ISMM 2004 Keynote
Improving Signal Integrity With On-Die Termination Memory Controller • Signal reflections handled with on-die terminators • Improved signal quality enables higher speed signaling On-die termination becoming standard in DRAMs ISMM 2004 Keynote
Page 1 and 2: DRAM and Memory System Trends Steve
Page 3 and 4: Amdahl’s Law and The Processor- M
Page 5 and 6: What Makes A Good Memory System? Hi
Page 7 and 8: Memory Latency Trends CPU 1990 2004
Page 9 and 10: Addressing Memory Latency “Bandwi
Page 11 and 12: Integration of Mem Controller Into
Page 13 and 14: Rising Front Side Bus Speeds Fuel t
Page 15 and 16: Physical Constraints Increase Per-p
Page 17 and 18: Signaling Speed Limited by Capacita
Page 19 and 20: Reflections Limit Signal Integrity
Page 27 and 28: Signal Quality at DRAM Changes With
Page 29 and 30: Signal Quality at DRAM Changes With
Page 31 and 32: Signal Integrity Issues Limiting Si
Page 33 and 34: Improving Signal Integrity With On-
Page 35: Improving Signal Integrity With On-
Page 39 and 40: Coming to a Server Near You: The Ad
Page 41 and 42: Memory Latency and Bandwidth are no
Page 43 and 44: Why Memory Systems Need More Banks
Page 45 and 46: Memory System Trends and Issues •
Page 47 and 48: Cost Reduction Critical in Some Con
Page 49 and 50: Reduced Power Consumption Critical
Page 51 and 52: Signaling Rates Limited by Signalin
Page 53 and 54: Equalization Enables Even Higher Si
Page 55: Summary • Latency continues to be

DRAM and Memory System Trends - IBM Research

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