Logic Synthesis for Look-Up Table based FPGAs using Functional

1
(LUT: Look-Up Table) FPGA(Field
Programmable Gate Array)
LUT LUT
m(m 4 5 )
[1]
LUT
[2, 3]
[4, 5, 6, 7, 8]
[5, 6, 7] (ordered
binary decision diagram: OBDD BDD)
[9]
BDD
LUT
LUT disjunctive
disjunctive
nondisjunctive
LUT
[1, 10] LUT
[11, 12, 13]
LUT SDC(Satisability
Don't Care)
2
BDD
3
LUT
4
LUT
5
6
bound
set
2
0
f
x 2 1
x 1
x 1
0 1 0 1
0 1
x 4 x 4 x 4
0 1 01
x 3
0 1
v 2
level
1
2
3
4
v 0 v 1
0 1
2.1 BDD
π
π
π
π
index
2
1
4
3
cut_ set( f , π, 3) = { v0, v1, v2}
cut_ set_ nd( f , π,,,) 330 = { v0, v2}
cut_ set_ nd( f , π, 331 , , ) = { v1, v2}
x 4 x 1 x 2
1: BDD
x 4 x 1 x 2
x 3 αα x 3 1 2
α 1
g g
f f
f : f0; 1g n ! f0; 1g (x 1 ;:::;x n )
f xi = f(x 1 ;:::;x i01 ; 1;
x i+1 ;:::;x n ) f xi = f(x 1 ;:::;x i01 ; 0; x i+1 ;:::;x n )
f (support) sup(f)
8x 2 sup(f);f x 6= f x 8x 62 sup(f);f x = f x
f jsup(f)j m m-
feasible m-infeasible
(BDD) [9]
( 1) BDD
2
0 1
0 1 2
v i v j
v i v j
1 1
BDD
2.2
f(x 1 ;:::;x n )
f = g( 1(X B );:::; t(X B );X F )=g(~(X B );X F ); (1)
X B X F X B [ X F = fx 1 ;:::;x n g
X B , X F
bound set, free set X B \X F = ;
disjunctive
nondisjunctive g
2