INTEGRATED AUDIOMETER SYSTEM (IASY) - FUSE

COREP TTN: FUSE Application Experiment No. 22949 

FUSE Application Experiment 

Dissemination / Demonstrator document 

Amplifon SpA 

INTEGRATED AUDIOMETER SYSTEM (IASY) 

A Full Custom Mixed ASIC allows the doubling of market share 

AE number: 22949 

New Technology: Mixed Signal ASIC 

Industrial Sector: Medical and Surgical Equipment and Orthopaedic Appliances (3310) 

Contact TTN: 

COREP 

Start date: 01/11/96 

Ending date: 30/04/98 

Duration: 

18 months 

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Amplifon SpA 

Abstract 

The company Amplifon S.p.a. with 411 employees designs implements and produces instruments for ear, 

nose and throat (ENT) since 1950. Its Biomedical Division (AMPLAID) with 4.5 MEUR annual turnover 

and 42 employees, designs and sells advanced hearing assessment equipment (audiometers) and it is also 

responsible of taking high level courses relating to the problems of hearing, ways to detect them and possible 

solutions. It. intends to integrate on a single proprietary chip all the circuits required to generate and control 

the audio signals in ENT instruments. 

The actual electronic product are PCB based, but this technology is far from being competitive on the actual 

market. The mixed signal ASIC (46% digital, 54% analogue) solution results in low cost of the product, it is 

smaller, more reliable and more difficult to copy. The market share has been increased and the 

microelectronics knowledge acquired will allow the company to exploit it for future projects. It will also take 

benefit from the training on the job and from the experience acquired in complex management. 

The total cost of the Application Experiment. is 150 KEUR and its duration has been 18 months. The 

estimated Return on Investment (ROI) is 43 times, over 4 years product life time, and the investment will be 

paid back in less than one year. 

The lesson learned is the importance of the economical, technological and managerial information in 

addition to the strictly technical ones. This allow to define according to the complexity of the project and to 

the forecasted production volumes, which are the right technology and the right approach to be used for a 

specific problem. 

Keywords and signature 

Keywords: Audiometer, hearing instruments, hear phones, mixed ASIC, AHDL, audio frequency filters, test 

vehicles, second run 

Signature: 5-0130 513 0132-3-3310-233-I 

1. Company name and address 

Company Name: Amplifon S.p.a. 

Company Address: Via Ripamonti 133, 20141 Milan, Italy 

Web Site: 

http://www.amplifon.it 

Contact Person: Guido Grassi 

Tel ++39 02 5747250 

Fax: ++39 02 57472349 

e-mail: grassi@amplifon.it 

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Amplifon SpA 

2. Company Size 

The Company has 411 employees in the whole. 

The Amplifon group structure is shown in the following diagram: 

AMPLIARE AMPLIFON AMPLAID AMPLIFON 

IBERICA 

The Research & Development division of AMPLAID (with a turnover in 1997 of 4.5 MEUR),is composed 

by 22 employees that take care of the production of all Amplifon’s medical equipment, designing for each of 

them the necessary parts such as: 

- sound amplifiers; 

- acoustic generators; 

- signal attenuators; 

- electrical stimulus generators; 

- CPU boards on different microprocessors. 

3. Company business description 

Amplifon S.p.A is an Italian Company created on 1950 and it is the biggest company in Europe devoted to 

hearing. During the first years the medical instrumentation area was carried on by Amplaid S.p.A. an 

affiliated company that since 1991 has become an integrated division of Amplifon S.p.A. 

Thanks to its 40-year experience, Amplifon is a leading organisation in research, technology, service to the 

medical professions and to the hearing impaired, providing solutions to auditory disorders. Its service 

capability is based on its distribution and assistance network of more than 200 branches and 2000 centres in 

Spain, through more than 500 high-qualified audiologists. Amplifon offers a complete range of services for 

an improved approach to hearing aid fitting. For the ENT specialist the organisation provides continuous 

information updating of a high scientific content. 

There have been two milestones in this support activity for ENT specialists, scholars and researchers: in 

1970 with the start of Amplaid, the line of equipment for diagnosis and investigation in ENT and in 1971 

with the start of the Research and Studies Centre «CRS», finalised to research into of hearing and auditory 

disorders. With Amplaid Amplifon offers the most advanced equipment to ENT specialists and contributes 

to the development of testing and investigation methods. Furthermore, its aim is to provide professionals and 

hospitals with essential know-how for both clinical routine and research. In 1970 Amplaid started 

development and production of a line of equipment for Audiometry, Impedance Audiometry and Evoked 

Potentials Recording. The Amplaid trademark is well-known all over the world and its products, distribuited 

in over 50 countries, represent the outcome of the most advanced research and the basis for progress in 

audiological technology. Today, the Amplaid Biomedical Line represents a complete range of systems for 

otology and audiology. Amplaid is heavily involved in further developments of advanced applications of 

Evoked Potentials and of systems for computerised and integrated management of audiological equipment. 

Most recent results confirming this trend are the multichannel systems for electrodiagnosis and release of 

software programs for audiological data handling. Together with Amplaid equipment, Amplifon offers a full 

range of services: form application and technical training to qualified technical assistance. From the start 

Amplaid’s policy has always been to develop new testing methods to improve clinical differential diagnosis 

of auditory disorders, co-operating intensively with the leading ENT and Audiology Clinical and Research 

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Amplifon SpA 

Centres in the world. Amplaid, making available high-tech user-friendly equipment, is thus contributing in 

disseminating world-wide innovative testing technologies. 

Amplifon operates according to stringent quality control systems and procedures, taking special care to 

ensure that all Amplaid equipment complies with international performance and safety standards. 

The Research and Studies Centre CRS is an independent, no-profit body, whose activities are entirely 

financed by Amplifon. Founded in 1971, CRS is keeping up with scientific developments and findings on 

hearing and auditory disorders. 

CSR activities have developed in various fields: 

• information and updating: congress, symposia, seminars and round-tables on audiology, audiological and 

otoneurological diagnostics, phoniatrics, ear surgery, hearing aid fitting, noise pollution; 

• educational programs: courses on audiometry, diagnosis of auditory disorders, impedance audiometry, 

vestibology, otoneurology, communication disorders, aphasia, auditory evoked potentials; 

• bibliographical services: one of the most comprehensive libraries with over 10000 scientific publications, 

open to specialist and researchers, on-line connection with international data-banks, bibliographical 

research. 

4. Company markets and competitive position at the start of the AE 

The current product at the beginning of the A.E. had a turnover of 4.500 KEUR. 

Amplifon is presently recognised as leader in the Italian market with a share of 90%. In addition it covers 

10% of the European market and 4% of the world market. One of the commercial goals is to consolidate its 

position in the world market, where the competitors are: Interacoustic, Grason Steadler (GSI), Madsen, 

Damplex, Maico, Beltone, Rexton, Finnigam and otherIn the following graph the company market shares are 

WORLD MARKET SHARE 

Amplaid 4% 

Company A 11% 

Company B 24% 

Company C 12% 

Company D 2% 

Company E 9% 

Company F 5% 

Company G 2% 

Company H 12% 

Other 19% 

given (the competitors are identified by symbolic letters) 

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Amplifon SpA 

The indicated companies are not yet selling instruments with such technology, then the present A.E. will 

allow the FU to have competitive advantage against them. The previous picture shows the world-wide 

market share and its competitors. 

WORLD-WIDE MARKET SHARE OF AMPLAID AND ITS COMPETITORS 

Being IASY a component of some of the product portfolio (Audiometer, Impedancemeter, Evoked 

Potential Systems and Otoemission Systems), the FU will acquire market share benefits in all the 

segments constituting the overall market and here below reported: 

TABLE 1 (Market share in percentage) 

Screening Industrial Clinical 

Share (%) 

TOTAL 

2 1 5 4 

Amplaid 

2 

13 11 

Company A 

Company B 3 42 24 

Company C 11 18 12 

Company D 2 2 

Company E 27 17 3 9 

Company F 22 3 3 5 

Company G 10 1 2 2 

Company H 56 13 

Other 18 

The following table shows the world-wide market at the end of 1996 (when the A. E. started). 

TABLE II (unit used Millions of dollars) 

Screening Industrial Clinical TOTAL 

8,4M$ 8.6M$ 21,4M$ 38,M$ 

The following table shows the final statement for current product for 1996 

TABLE III (Unit used KEUR) 

1994 1995 1996 

Turnover current product 4,000 4,250 4,500 

Profit current product 1,800 1,900 2,000 

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Amplifon SpA 

The following graph shows the turnover and the profit of the current product trend as estimated at the 

beginning of the experiment 

GRAPH I (Unit used KEUR) 

7 

6 

5 

4 

3 

Turnover current product 

Profit current product 

2 

1 

0 

1995 1996 1997 

It can be stated that the new range of products built around IASY are positioned at the top of present 

Amplifon product range for their specifications and performance. Using a mixed IC technology Amplifon 

S.p.a. improved their functionality and improved the following features: 

• The product is smaller, more reliable, impossible to be copied and available at lower costs 

• Its flexibility is greatly increased providing totally innovative performances for audiometric and 

audiological testing 

• The new audiometer represents a total breakthrough providing the market with a totally digital PC 

based audiometer. 

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Amplifon SpA 

5. Product to be improved and its industrial sector 

The picture below shows the existing product. As can be seen the old product is based on a large PCB with 

several discrete components, a lot of trimmers and can include up to 5 FPGAs. 

The functions covered are nearly the same of the new one but with a much more cumbersome requested 

trimming procedure. 

The ASIC developed in this A.E. will be used in four families of instruments: audiometers, 

impedancemeters, evoked potentials systems and otoemission systems. This instruments are part of the 

necessary biomedical instrumentation that is used in the modern diagnosis of hearing problems and 

Amplifon is leader in producing them. In all these instruments, audio signals, narrow band noise, speech 

noise and white noise are generated. The above tasks are achieved in the currently available instruments 

using printed circuit boards (PCB's) based on off-the-shelf components. This approach is, of course, not 

optimum since the design relies on the performance of low-cost discrete components and requires continuous 

redesigns of the PCB's in view of the fluctuations of the IC market. Each instrument has the electronics 

strictly sufficient to generate the signals that are needed for the specific instrument. In other way this imply 

that two different instruments have two different core architecture. Consequently, when changes are needed 

it is necessary to modify different board in different ways. This takes to an unjustified multiplication of the 

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Amplifon SpA 

effort in designing task. Also different implementation attitude are to be used and different testing procedure 

must be used. A unique, reliable, integrated core is the best solution to be adopted since the same multifunction 

chip can be controlled by a microprocessor to have the chip generating the required function. 

Therefore, the core (the most critical part) of the system has been integrated on a single ASIC. 

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Amplifon SpA 

6. Description of the technical product improvements 

Figure below shows the final block diagram of the IASY. It implements an integrated audiometer generating 

several kinds of signals in the audio band useful for audiometric tests. The circuit under test is able to 

provide a variety of audio signals, like pure tones and various kinds of noise, and processing capabilities to 

modify the frequency and the amplitude of generated signals and of other external signals even through 

suitable modulations. The circuit integrates two independent analog processing channels for left and right 

ears. Noise signals are typically used as masking signals on one ear during the test of the other ear. One or 

more IASY circuits can be allocated in the same audiometer. The programming of all the IASY circuits can 

be easily done with the help of a microprocessor. The circuits mainly consists of: 

1. A digital section working at 40 MHz master clock frequency, interfacing with an external 

microprocessor through a 4 bit address bus and an 8 bits data bus. The communication with the 

microprocessor is regulated using two signals: a chip select (CSIASY) and a Read/write (RD) signal. 

This section generates two different kinds of signals: 

q Pure tone with variable frequency in the range 100 Hz to 20 KHz; 

q White noise over the frequency range 100 HZ to 16 KHz; 

2. An analog section which converts the generated signals into the analog domain (10bit) resolution) and 

processes them to give a pure tone with variable frequency in the audio band and several kinds of noise: 

white, pink, speech and narrow-band noise. Moreover, two identical audio channels are present 

performing some kind of analog processing on the generated signals and on some external signals 

(MIKE, TAPE and CD). The analog processing mainly consists of a volume control. Other functions are 

also present in each channel: attenuation level and amplitude modulation (SISI & DLI modulations) to 

program an external electronic attenuator and an 8 bit ADC driving an external VU-meter. 

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Amplifon SpA 

The IASY is supplied with a single 5V supply voltage. An external reference voltage nominally 2.5V) is 

used as analogue ground reference for continuos-time and switched-capacitor filters. A very high stability of 

external power supply is guaranteed. The chip is a mixed analogue/digital circuit. The chip is implemented 

in a 0.8 µm CMOS double-poly, double-metal technology and occupies 24.2 mm2 (46% digital and 54% 

analogue). The complexity in gate of the digital part can be estimated about 3500 equivalent gates. 

Thanks to the mixed analogue/digital technology some functions, now implemented with critical analogue 

circuits, is more comfortably achieved with digital techniques. An example is the pure tone generation that 

enjoys the benefits of the direct digital synthesis (DDS). Starting from a 40 MHz master clock it is possible 

to synthesise any frequency in the range 100 Hz-18 kHz with 1 Hz steps. This feature is at least 10 times 

better than commercially available instruments with similar cost. 

The key analogue processing functions of the IC include conditioning of the external input signals, filtering 

(wide-band and narrow-band) and data conversion. Fulfilling these specification is the main goal of the AE. 

The analogue part is necessary since the signals to be generated have to interact with the human ears which 

are very sensible and need an high fidelity reproduction of the frequency tones currently used in audiometric 

analysis. The filters used in the chip are based on the switched-capacitor technique, which allows the 

response of the circuit to be locked (when required) to the frequency of the generated tone. 

Technical Details. 

The IASY includes two identical analogue channels. Each of them has three analogue inputs (mike, tape, 

CD) which can be optionally amplified by a factor of 7. An additional amplifier with adjustable gain 

(Controlled Gain Amplifier, CGA) common to the three inputs must regulate the signal level to achieve at 

the output a 2 V pp,rms signal level. A fourth input named Talk is directly sent to the output after a suitable 

level regulation done by another CGA. 

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Amplifon SpA 

On each channel is available an 8 bit A/D converter driving an external V:U: meter. Each channel also 

includes two 7 bit D/A converters (Range Attenuator and Range DACs) used to control an external 

electronic attenuator. 

They generate the following output levels: 

• The warble function represents a frequency modulation of the selected sinewave (frequency f o ) up to 

f o -10% and back. 

The white noise generator provides noise with uniform power spectral density in the frequency range from 

100 Hz to 16 kHz. The noise output amplitude must be 2Vpp over 2kΩ resistive load. If the generated noise 

presents periodical sequences, their repetition period is assured to be longer than 5 s. 

The speech noise low-pass filter is a maximally-flat second-order low-pass filter with a corner frequency of 1 

kHz. It is needed to filter the white noise to produce a masking signal used during voice tests. 

To filter the pure tone and to generate the narrow-band noise two second-order band-pass filters with a 

centre frequency equal to f o and very high quality factor (Q) are used. The narrow-band noise presents a 

constant power in each frequency band. This can be achieved by placing a pink-noise filter in cascade to the 

white noise generator. This is a half-order (3dB/octave) low-pass filter with a corner frequency of 100 Hz. It 

converts the white noise to pink noise, that is with constant power per octave. 

Regarding the signal-to-noise ratio when the input signal selected is mike, tape or CD is at least 60 dB, when 

the input signal selected is the pure tone it must be at least 80 dB. 

When two different signals are selected on the two channels, the crosstalk between the two outputs are better 

than 70 dB. 

To reduce crosstalk between the two IASY channels, separate power and ground buses were used for each 

analogue channel, the common analogue section (which include D/A conversion and filtering) and the digital 

section. 

The design risk was limited because of two main advantages: the availability of a silicon foundry library 

with a good number of basic cells and the technical support offered by the silicon provider for the most 

critical design issues (mixed-system noise reduction, packaging, assembly). 

A substantial technical and economical improvement was achieved, but, at the same time, the final user 

(normally a technician with limited electronic expertise) did not urge further specific training. 

The main advantage that we planned to achieve with this new realization was the consistent (at least 40% 

size reduction (at least 40%) of the audiometer motherboard in order to fit in a smaller audiometer case. 

To this purpose we eliminated more than 100 discrete components and 5 FPGAs 

With the use of the new technology we obtained quite useful additional advantages like: 

‣ Manufacturing cost and test reduction: there are less components to buy and the same ones are inside 

different instruments. The average cost reduction on each instruments is of 90 EUR. The test cost have a 

reduction because there are less components to be tested. 

The improvement is characterised by the use of a good quantity of discrete components. The reduction 

on number of components augments automatically reliability and guarantees a greater flexibility on 

configurability of the final product. 

‣ Functionality improvement: from the clinical standpoint, features such as 1 Hz frequency increments 

and 0.25 dB intensity increments, prove outstanding in detecting cochlea pathology (recruitment) and in 

differential diagnosis between cochlea and retro cochlea lesions (the former indicative of VIII nervebrainstem 

tumours). 

‣ Accuracy and precision improvement : IASY permits frequency scansion till 1Hz (the old attenuators, 

such as the A 460 could guarantee steps of 5 Hz) with an accuracy +- 1%; and a range of attenuation 

from – 20 to + 125 dBHL (instead the A 460 from – 10 dBHL to + 120 dBHL) with step of 0.25 dBHL 

(instead the A460 step of 0.50 – 0.75 dB). 

‣ Maintainability enhancement:. the trend in the rather flat market of audiometry aims at products 

capable of exploiting the advantages of informatics/computer technologies. Success in the market also 

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Amplifon SpA 

implies accuracy and stability over time of all calibrations as well as consistent decrease in the time 

needed for repair/service, thus ensuring longer lapses of time between two successive failures (MTBF). 

This is achieved only through technological innovation capable of reducing the number of components 

used in a single instrument. Thanks to cost reduction maintainability costs are also reduced of the 20%. 

‣ Reduction in power consumption and in weight : the less number of components to be included 

reduces the size of the mother-board and therefore the space needed for it. This justify smaller and 

lighter case. Power consumption is as a consequence reduced, view the smaller number of components 

to feed. 

‣ Compliance improvement : less components to feed reduce radio emissions. This is due to a smaller 

mother-board, included with all components related to it, which reduce the neeeded space. Therefore 

they can be inserted in an iron box in order to influence radio emissions and reduce them. 

The iron box is covered by a plastic case which follows specific ergonomics request, in order to reduce 

the user’s wearying and giving more importance to the instruments. Last but not least is the facility of 

customisation of a plastic case. 

‣ Reduction in design cycle time: the use of IASY in the R & D of equipment targeted to auditory 

diagnosis greatly improves performance (number of tests made available), making also the device more 

flexible and easy to use. It thus helps diminish the number of dedicated models, with the advantage of 

generating new models by simply stripping down performances by means of software without any 

hardware modifications. This could mean up to 50% reduction of the design cycle time. 

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Amplifon SpA 

7. Choices and rationale for the selected technologies and methodologies position 

Selected technologies. 

When we considered the possible options for the technology to adopt we have taken into account the main 

requirements for the new product. And particularly: 

- Technical Benefits 

‣ The motherboard size reduction (at least 40%) in order to fit in a different case with the 

elimination of more than 100 discrete components (5 FPGAs) 

‣ Enhanced performance and flexibility 

‣ The increased reliability of the global equipment (better MTBF) 

‣ Modularity (same component used in more audiometers) 

‣ Better EMC compliance 

− Economic benefits: 

‣ Cost reduction of the motherboard 

‣ Reduced time to market 

‣ The reduced cost of testing and manufacturing phases 

We realised immediately that all these goals pushed toward a technology which allowed a much increased 

integration than the previously used one and: 

• Would allow to reduce the size of the board 

• Would allow to realise both analogue and digital functions 

• Would be easily interfaced to a CPU 

• Would reduce the time to market by decreasing the manufacturing and testing duration 

• Would greatly improve the system reliability 

We evaluated several possible alternatives: 

a) FPGA plus analogue discrete components. 

This is the currently used solution and has the already mentioned drawbacks; a possible improvement to 

get the requested size reduction. would have been to increase the number of the PCB layers, but this 

would have increased (more than 60%) the board manufacturing costs 

b) An hybrid solution was also considered (chip on board plus thick film technology), but it was also 

discarded for the following reasons 

♦ The cost and difficulties in providing the good dies of the FPGA components 

♦ The need for a laser trimming procedure of the most critical analogue 

components 

♦ The stiffness and poor modularity of the implementation 

An ASIC solution was present to us since the beginning of the investigation, but we had means neither to 

translate the requirements of our product into the features requested to the target semiconductor technology 

nor assess the finally obtainable performance. Moreover it appeared to us that the small requested volume 

(some thousands per year) would have not been compatible with an ASIC choice. 

But we were persuaded from the discussions with our subcontractor and the TTN since: 

1. A mixed signal ASIC was certainly the technology able to guarantee size reduction , analogue 

and digital functions implementation at the lowest cost 

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2. When dealing with small volumes (as it was the case of Amplifon product) the NRE costs should 

be shared on a small number of components and be all the same compatible with the final target 

cost. 

As a matter of fact it turned out that the final costs of the board with a mixed ASIC component 

(even considering the NRE costs) was nearly 60% of the one of the current solution mainly due 

to the highly reduced count of components 

3. The package cost which is in general the real nightmare of an ASIC component was not critical 

in this case because of the not large pin count and the requirements in speed and power 

dissipation 

4. Manufacturing and testing costs could be reduced of more than 30% with a significant 

improvement in reliability (about 10 times improvement that is the square root of the 

component reduction rate). 

On the other side it should be considered theat mixed ASIC is certainly a risky implementation and one 

should be very confident into the expertise of his DAS, befofore deciding to proceed with such a 

development. 

We selected a plain CMOS technology as the most suitable for a low cost realisation which did not present 

special requirements for speed or low voltage. The foundry was selected according to the need of availability 

of a rich, high performance analogue cell library including macro blocks like SC filters and data conversion 

elements. 

The chip was implemented in a 0.8 µm CMOS double-poly, double-metal technology with an area of 24.2 

mm2 (46% digital and 54% analogue). Package was a 68 PLCC. Power dissipation was limited to 45 mW 

Selected methodologies: design. 

The main goals to be pursued with the choice of the design tools were: 

♦ High design productivity to ensure time to market 

♦ Effective description and simulation facilities 

♦ Capability to handle analogue functions 

♦ Compatibility with selected foundry design kit 

It was decided to use VHDL language to describe and simulate the digital part of the ASIC as it enables to 

manage complex digital functions from the usual system designer without a deep knowledge of the 

technology features and constraints. 

VHDL has the further advantage to ensure the maximum of portability to the design. The logic netlist was 

obtained with a digital synthesis tool. 

For the analogue part the analogue high level description language was used (AHDL) for the most complex 

functions, while conventional schematic and electric simulation tools were exploited for designing the simple 

cells. 

Both digital and analogue part generated a netlist, which allowed carrying out in a semiautomatic way, the 

physical part of the design (i.e. floorplan, placement & routing and design verification). In such a way the 

most critical paths of the layout like clock distribution and power supply rings were placed manually, 

separating the analogue and digital power & ground so as to obtain a strong reduction of the internal chip 

crosstalk and noise. 

This should be considered a general best practice when developing complex mixed signal ASICs since the 

commercial automatic tools very often provide insufficient solutions for the power supply lines routing 

problem. 

All these tools are integrated in a complete design framework which assures full consistency of the design 

database and the matching of data format between the different tools. 

The cost of such framework is generally very high and the FU looked for a subcontractor that owned the 

framework and was experienced enough in running the tools. 

This is also to suggest to other FUs because the skill in using the proper design tools is a key for success in 

ASIC design. 

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With this high productivity methodology it was possible to design a first MPW in less than 5 months, with 

minor mistakes. A second MPW, planned in the initial work plan, as good risk reduction policy, allowed to 

correct the first run errors and to reach the fulfilment of all the specifications in only six months design 

(excluding the gaps for fabrication). This is an outstanding result with a complex mixed signal ASIC. 

Selected methodologies: testing. 

The large number of analogue functions to be implemented makes the test of the circuit of crucial 

importance. For the analogue section a very high fault coverage test pattern has been defined that permitted a 

full automatic testing of the circuit. The choice for the automatic testing came from the idea that this testing 

methodology could be exploited for the future testing of the produced chips. For the digital section a similar 

approach has been defined. 

8. Expertise and experience in microelectronics of the company and the staff allocated to the project. 

In all the products presently on the market PCB, FPGA and discrete acoustic sensor technologies are applied. 

From the technical point of view Amplifon lacks many important skills that are necessary to design and 

implement a full custom IC. 

Before the A.E, Mr. Guido Grassi, Dr. Proserpio and Dr. Nobile directly involved in the project, had the 

knowledge to develop project based on µprocessors , µcontroller, and DSPs . There were not relevant 

knowledge concerning ASIC, and the expected know-how increase was a further motivation for the new 

development. 

Thanks to this project the company acquired microelectronics design capabilities in medical instrumentation 

through on-the-job training, a step-by-step tools acquisition and continuous interactions with dynamic and 

qualified University departments. The main effort has been the acquisition of knowledge about this new 

technology and on its management. After the experiment Amplifon, by combining the acquired knowledge 

with the previous experience on discrete components design, has the full capability to design and to 

manufacture integrated audiometers using advanced technologies. 

Personnel Involved in the A.E. 

Personnel included in the A.E. is: 

• the responsible of the R&D division, is the manager for the entire project; 

• a senior engineer ,.with background has been trained different subjects of design analogue integrated 

circuits. 

• a design engineer , whose background is that of a hardware designer has been involved in several design 

tasks for small IC building blocks. 

This A.E. has of course improved their know-how of the microelectronic world, understanding its rules and 

its limits. At the end Amplifon personnel has reached a point in which autonomously it can carry the 

technological assessment for future projects. 

9. Workplan and rationale 

The following Time table shows the original Workplan, divided into 5 Workpackages. 

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Training (WP1) 

Specifications (WP2) 

Design 1st prototype (WP3) 

Integration 1st prototype (WP4) 

Test 1st prototype (WP5) 

First prototype 

Redesigns (WP3) 

Design 2nd prototype (WP3) 

Integration 2nd prototype (WP4) 

Test 2nd prototype (WP5) 

Second prototype 

Underneath the descrition of each Workplan. 

WP1: Training 

The work package leader was the Training Subcontractor. In the frame of this work package the Training 

Subcontractor has transfered to Amplifon (one or two engineers were devoted by Amplifon to this task) the 

information, the know-how and the expertise required for the transition from a discrete component design 

culture to an integrated circuit (IC) approach. The Training Subcontractor taught the use of the equipment, 

workstations (SUN Sparc Stations and PC) and software (Cadence DFII and Tanner Tools) required for 

education and on-job training. At the end of the A. E. Amplifon is able to start its own activity in IC design. 

Deliverables: D1 - Training test material. 

WP2: Specifications 

0 10 20 30 40 50 60 70 80 90 

Week 

The work package leader was Amplifon. The aim of this task was to determine the actual specifications of 

IASY. A detailed report on the system architecture, the functional and electrical requirements of the building 

blocks and the definition of the test patterns for device characterisation has been provided. The specifications 

take into account the constraints introduced by the monolithic fabrication technology (e. g. 5 V power supply 

voltage). 

Deliverables: D2 - Specifications. 

WP3: Design 

The work package leader was the Design Subcontractor. In this work package the IASY was designed and 

implemented according to the architecture defined in the WP2. Attention has been given to keep the system 

noise low. Careful definition of the chip floor plan is of crucial importance to avoid cross-talk between the 

analogue and the digital sections. In addition, test structures were included in the chip to accomplish the 

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defined test strategy. The Training Subcontractor assisted the Design Subcontractor and Amplifon in the 

design of the system providing some useful suggestions for the analogue architectures. 

Deliverables: D3 - Simulation results and a PG tape containing the layout. 

WP4: Production of Prototype 

The work package leader was Design Subcontractor. Design Subcontractor has assisted Amplifon in all the 

phases required for transferring of the designed chip to the Foundry, which produced 10 engineering samples 

of the IASY. In view of the complexity of the system two multi-product wafer runs (30 mm2 each) were 

necessary to achieve the final chip. 

In the first the inclusion of additional test structures and test points ensured complete testability and 

observability of the system. In particular, it was necessary to identify and eliminate inter-channel cross talk 

sources (these phenomena were not predictable at the simulation level). 

Deliverables: D4 - 10 prototypes for Run. 

WP5: Testing 

The work package leader was Amplifon. In this work package the functional characterisation of the circuit 

was carried out. Amplifon prepared the necessary test resources in its test system set-up. This task also 

includes the development of the interface board for the Device Under Test (DUT). The test has been 

performed on the devices produced in the WP4 according to the test strategy defined in the WP2. 

Deliverables: D5 - Test report. 

Workpackage 6 has been added during the A.E. 

WP 6: Dissemination 

The Workpackage leader was Amplifon. During the all A.E. an internal dissemination has taken 

place. Different meetings have been organised together with the Marketing & Commercial 

Responsible in order to discuss the modalities of internal dissemination both of the results and the 

expertise achieved during the A.E. The preparation of the Dissemination report and the Flyer has 

been one of the main topics discussed 

- At national at international level Amplifon has worked on the organisation and the planning of 

its participation to different meetings and exhibitions (BIAS and IST). 

The participation to those events was very important for the project. In this framework Amplifon 

intends to disseminate and discuss its experience during the A.E. in order to be an example for other 

European industries. 

The following Time table shows the all A.E, including Workpackage 6. 

WORKPLAN 

MONTH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 

TRAINING 

SPECIFICATIONS 

DESIGN 

INTEGRATION 

TESTING 

DISSEMINATION 

17


Amplifon SpA 

Both from a technical point of view and from a management point of view the division into WP 

demonstrated very helpful, even though once in a while the WP shows some rigidity. The company was 

already used in working with WP and this helped it very much. In general the amount of activities to be 

carried out in each work package had been previously examined and weighted. 

Analysis of variances 

No major modification has been done to the original workplan. 

♦ During the first audit meeting the TTN has asked to make some adjustments in the Work plan to make it 

more controllable. The adjustments regarded the introduction of a work package specifically devoted the 

management, thus showing the number of labour hours actually devoted to management, and the request 

to report also on the second silicon run instead of leaving it unreported. The last adjustment ended up 

with the introduction of two addendum at the deliverables (D3 and D5). 

♦ In general the amount of activities to be carried out in each workpackage has been previously examined 

and weighted. Some adjustments had to be made when the European Commission has asked to develop 

the demonstrator and flier. In order to ensure a clear schedule to this new deliverables a new 

Workpackage number 6 was created completely devoted to Dissemination. 

The F.U. is very satisfied with the accuracy maintained in following the workplan and with the way the 

timing of each task has been respected. This is a very difficult goal to reach with an ASIC and is certainly a 

consequence of the careful risk assessment made by Amplifon and its design assistance subcontractor at the 

start of the project 

This risk assessment was based on the identification of the critical pal paths in the design (mainly the 

analogue part), and the main strategy to reduce the risk was, beyond allocating more room for the design, 

to have two different MPWs, so that the first could be used for checking the most critical architectures and 

the second to assemble the complete system. 

We do believe this is one of the most important lesson to be taught other companies during the dissemination 

activity. 

More than 30% of the budget for the development was subcontracted and specifically: 

7% for subcontractor training, 15% for the design assistance, 13% for the ASIC fabrication. 

Total effort was 2 persons year; about 70% was supported by the company. 

The following table resumes the effort percentage spent by FU and its design assistance subcontractor in the 

different tasks during the full development 

First User 

Subcontractor 

Effort Cost (kEUR) 

(Person/days) 

Management 44 

Training 110 10 

Design 88 15 

Prototype 5 19 

Evaluation 154 2 

Dissemination 22 

Total 423 46 

18


Amplifon SpA 

10 . Subcontractor information 

The success of the A. E. is also due to the proficient help given by the design and training subcontractor and 

by the foundry all along the duration of the project. Help has been given in: 

• Choosing the right technology and the right design flow with subsequent risk assessment 

• Starting a training course that helped the design of the chip 

• Understanding the microelecronics world, its rules and limits 

• Reaching a point in which an autonomous future project assessment is possible 

Despite the previous acquaintance, Amplifon has guaranteed itself by making internal contracts with all its 

sucontractors, therefore all possible risks have been duly weighted. Therefore it was previewed the 

possibility to make 1 or 3 run and also the possibility of failure. All parties responsabilities have been also 

listed as were all IPR issues. 

The following chapter gives information on each subcontractor. 

The design subcontractor 

For performing the design subcontractor task we selected by a small design house for the following reasons: 

♦ No major design house was keen to offer support to an sme like Amplifon at reasonable costs. 

This evaluation also included the semiconductor foundries which did not want to involve their 

design departments because of the low requested volume 

♦ The selected subcontractor is a spin-off of the most reputed Italian University for mixed ASIC 

design. 

♦ The four designers of the company have all Ph D and have designed successfully more than 20 

ASICs in five years (mainly analogue and mixed) for both research and industrial application. 

Their experience covers the design of integrated circuits for telecom application, sensor 

interfaces, and special data conversion systems on silicon. 

♦ They have a proved attitude in working with SMEs and a good acquaintance and interface with 

some of the most important European foundries. They have knowledge of the most advanced 

CMOS and BiCMOS processes. 

It is worth mentioning that the subcontractor demonstrated very co-operative and helpful to the first user 

since the time when the feasibility analysis of the project began well before the proposal submission. 

This means that the selection of the subcontractor preceded the preparation of the proposal and that the help 

of the subcontractor was crucial in obtaining and evaluating the offers from the silicon foundries and in 

defining the different cost voices of the project. 

The Foundry 

The Foundry is specialised on the development and production of full custom and semicustom integrated 

circuits. The company provides high performance CMOS and BiCMOS processes and standard cells. The 

Foundry's "all under one roof" strategy (research and development, design engineering, mask lithography, 

wafer fabrication, assembly and test) has placed the company in a strong position within the market 

segments telecommunication, automotive, audio and industrial electronics. 

The Training Subcontractor 

19


Amplifon SpA 

The Training Subcontractor is a prestigious Italian University very famous for their experience in training 

new designers of analogue and mixed analogue/digital integrated circuits. 

In this University an advanced post graduate course is addressing the design of analogue and mixed ASIC 

circuits. 

The University professors of the Electronic departments are well known for their lectures in international 

courses and summer schools for ASIC design. Favourite research areas include telecommunication circuits 

(audio and video), A/D and D/A converters and, more recently, circuits for smart sensors. 

The knowledge of state of the art technology and design methods is documented by more than 70 papers 

(1989-1994) in international conferences and scientific journals. Moreover in the last five years more than 40 

analogue and mixed analogue/digital integrated circuits have been developed, fabricated and tested. 

In recent years, a new activity branch was started, aiming at the development of CAD tools and behavioural 

models for IC design. 

11. Barriers perceived by the company in the first use of the AE technology 

Prior to the Application Experiment, Amplifon was well aware that the introduction of integrated circuit 

technology was mandatory for the future of the company. On one side, it was true that the electronics of the 

PCB boards had allowed Amplifon to gain the market share that makes it the leader in the sector, but on the 

other side it is also true that shifting to a more competitive technology is the only way to keep the share and 

the only one to expand it anticipating the competitors. 

That is why Amplifon understood that microelectronics could improve products and competitiveness. The 

limited knowledge of microelectronic technologies has manifested itself in technology barriers that have 

enhanced the normal difficulties in introducing a new technology. 

The awareness of important obstacles in developing a new component using the ASIC technology was 

present to the company prior to the beginning of the experiment and, moreover, the use of a new technology 

put in evidence the lack of design expertise that might have affected the spec definition phase. 

At first it was difficult to understand how to search for information about integrated circuit technology. 

Technology experts and European foundries had an own technical slang difficult to understand for the 

company and it has been an hard job to localise a landmark for these first steps. 

Also to be mentioned are the financial barriers. In fact it was a general feeling for our management that any 

investment in research, development and training might affect the production and sales of the current 

products and that, combined to the perception of the high risk involved in the prevented the company to start 

the development on its own resources. 

We would have been in any case sooner or later forced to go through this innovation step, but, without 

FUSE, time to market would have been greatly longer and the development much more difficult for the 

company. 

12. Steps taken to overcome the barriers and arrive at an improved product 

What helped Amplifon was its problem solving attitude and the total absence of prejudice. 

In order to overcome the psychological barriers due to high risk in the new technology, Amplifon chose the 

right Design Assistance subcontractor and performed with him a preliminary feasibility study. This helped 

the correct choice of foundry, technology and design style. Note that pre-existing acquaintance with the 

design assistant can be very useful in the project definition phase, since he knows from its experience the 

potential of the technologies and its constraints. 

The main barrier to be overcome has been the research of a foundry willing to accept a commitment suitable 

to Amplifon production. The research has been carried out by Amplifon at its own cost. Interfacing the 

foundries might be a big problem especially concerning obtaining the technological information. That is why 

it is useful to have a subcontractor with a long acquaintance with the selected foundry. 

20


Amplifon SpA 

Even if the relationship with the subcontractors had always been of complete collaboration, the particular 

application in the biomedical field of the circuit and the particular exigencies have turned out to be difficult 

to be explained to the chosen subcontractors. Therefore many meetings have been held in order to clarify 

those items both to the Foundry and the Design Subcontractor. 

13. Knowledge and experience acquired 

Thanks to the training received during the AE, we understood the paramount importance of the economical, 

technological and managerial information in addition to the strictly technical one. 

The quoted information can allow the company to decide, accordingly to the complexity of the project and to 

the forecast of the production volumes which is the right technology to be used and the right approach for the 

specific problem. 

The complexity of microelectronics problems is sensitively higher than the one generally faced in PCB 

design and that is why it is important to be able to figure out all the necessary steps before the beginning of a 

project. 

For example the work plan should be planned taking into account the schedules of the needed silicon runs 

made available by the selected silicon foundry. This should include the assessment of possible in the sample 

delivery date from the foundry and possibly in the shifting of testing and redesign work packages leading to 

important discrepancies with the scheduled time to market. 

The AE has been really formative under this point of view and improved the general knowledge of the 

company. 

Before starting, the company was sceptical about the training on the job and the need for the training offered 

by the Training Subcontractor because of the different language and the different background knowledge. 

Amplifon also feared the difficulty in transferring the information on its own needs to the subcontractors. 

As a conclusion we can say that the collaboration between the parts was very fruitful because the initial 

doubts and fears let the stage to a constant knowledge transfer which enriched both parts. This means that the 

Application Experiment was also of great advantage for subcontractor and not only for First User and 

possible Replicator. All the partners understood that the knowledge transfer is not only one-way, but it takes 

all the possible directions. The training touched theoretical and technical aspects of: 

• the technology and its limits and possibilities 

• analogue and digital blocks design methodologies and tools 

• testing and debug strategies. 

As far to the weight given to the different parts: 

• on design and testing 60% 

• on technology 30% 

• on project management 10% 

Most training effort was spent on design and testing since it mainly was given with an on the job training 

approach. 30% regarded an explanation of the selected technology and the rationale behind it and 10% 

concerned the management of an ASIC development (development phases and timing) 

We can really say that we realised our main objectives with this AE: 

‣ Learn how to specify a new ASIC component (including the technology choice) 

‣ Set up a reasonable and controllable development plan 

‣ Identify the most suitable development tools 

‣ Define the more appropriate ASIC technology 

At this point ASIC has become a fully manageable technology for our company 

14. Lessons learned 

21


Amplifon SpA 

During the progress of the A.E., the Company has accumulated a wide range of experience covering, 

managerial, business and technical issues: 

♦ the gained experience demonstrates that there were no significant real barriers in introducing the 

new technology. The good co-operation established within FU and subcontractors has increased 

the trust in introducing new technologies into The FU product line. 

♦ The skill in managing the CAD tools for the design is an important selection criteria for 

choosing the right design subcontractor for an ASIC development 

♦ The Company has gained a great deal of confidence in dealing with the new technology and now 

believes that it is able to easily find the sources of information for any future development. 

♦ The Company will certainly have a different attitude in the future in front of innovation of its 

products. 

♦ The advanced technology chosen was the right one. It has allowed the Company to implement 

all the necessary improvements, and to plan for exploiting it in many of its products. The 

expertise gained during the A.E. will allow the Company to rely totally on its internal resources 

for future development projects assessment. 

♦ The Company believes that microelectronics and the usage of suitable design tools might 

provide useful solutions to a wide range of companies, especially those without specific 

experience in microelectronics or those just starting. 

♦ 

Learning to work following a structured work plan has been of great help. The gained expertise 

will help in the future the right prevision of resources allocation in terms of time, man/months 

and budget allocation for each phase. 

♦ The results of this AE have demonstrated that financial barriers often hide cultural barriers. In 

fact the adoption of the ASIC technology is a big achievement for the company that will allow to 

become more flexible with respect to its customers requests and be become more and more 

competitive through the introduction of microelectronics into most of its products . 

15. Resulting product, its industrialisation and internal replication 

Amplifon has stipulated a contract with the foundry for the supply of production prototypes scheduled within 

4 months from the last MPW run and the component test procedure delivery. 

Tests have been repeated after product delivery also on the PC board which had to host the chip, in order to 

verify the correct manufacturing and testing made by the foundry. At the end an order has been placed for 

the first 100 components that have been already delivered and assembled on the target board at the end of 

last August. These ones have been tested and afterwards the final order was made for the delivery of the 

final production components. 

The first 100 pre series audiometers are distributed to Amplifon marketing forces to be presented in 

exhibitions and given to selected customers. 

As far as timing is concerned: 

About 6 months and a further cost of 50 KEUR were requested to get the first audiometer after the 

conclusion of the prototyping phase. 

♦ In July 1998 the first prototype board was validated successfully and the order placed for the first 100 

components 

♦ At the end of August 1998 an order was placed for 100 components to be assembled onto as many new 

audiometer boards 

♦ Delivery of first audiometers to selected customers began at the end of November 1998 

In the second half of 1998 we placed orders for 450 new audiometers. 

In the future Amplifon will exploit the acquired competence to evaluate the possibility to remake, in 

microelectronics technology those product that demonstrated a particular interest inside the market and 

22


Amplifon SpA 

already belong to its range of products. During this phase the First User will still use the present 

subcontractor competence. 

Thanks to the expertise and know-how acquired through the A.E. there is on-going the development of a 

second ASIC component self-financed by Amplifon. 

From a technical point of view the choice made was the integration on the same die of the analogue circuitry 

for the attenuation of audio signals together with the output power amplifier. All these circuits can be 

directly interfaced with the IASY control signals. The development of this new chip is now at the test phase 

for the first prototype. 

The cost of the new equipment and men/hours for the assembly and testing can be evaluated in about 250 

kEUR. 

Further 100 kEUR were spent for advertising the new product line (marketing, brochures, participation in 

sector exhibitions) training to sales forces and distributora 

16. Economic impact and improvement in competitive position 

The forecast for a gradual descent of the prices in the future years imposed a reduction of costs to guarantee 

Company’s budget. Consequently the R & D had to choose innovative technologies. The design cost 

reduction allowed to maintain a lower selling average measure and to acquire market share and therefore 

better prices compared to traditional components. 

The gain of new markets is obtained throughout the implementation of the newly-designed IC, in all 

Amplifon's products making them less expensive, more modern and commercially valuable. 

The following table shows a cost comparison between the old product without IASY inside and the new 

families of products with IASY inside. 

23


Amplifon SpA 

TABLE IV (Unit used KEUR) 

IASY INSIDE COST COST WITHOUT IASY 

Highly innovative Audiometer A311 0,8 1,6 Audiometer 

A308 

Clinical Diagnosis Audiometer A315 1,3 2 Clinical Diagnosis Audiometer 

A309 

Clinical Diagnosis Audiometer A319 1,7 3,1 Clinical Diagnosis Audiometer 

A460 

Cost reduction is due to the following reasons: 

1. A311, A315 and A319 benefits of the same audiometric mother-board, therefore there is an amortisation 

on 1.200 units. Instead the A308, A309 and A 460 have a dedicated mother-board and therefore the cost 

increases; 

2. A315 and A319 use the same case (and also the new impedance meters A724 and A728 which will be on 

the market next July), with an amortisation on almost 1.500 units. 

One of the main goals of the AE is an increment in internal and external sales. On the whole a bigger market 

share increase is foreseen. The first table illustrates the current market situation (real figures as collected at 

the end of the AE) while the second shows the expected future economic situation (real sales in 1997 will be 

only consolidated at the end of 1999) 

TABLE V (Unit used kEUR for the World-Wide Market and percentage for the Market share) 

1994 

KEUR 

1995 

KEUR 

1996 

KEUR 

AMPLAID 3.800 3.450 3.900 

WORLD-WIDE 

MARKET 86.500 88.000 94.500 

MARKET SHARE % 4.3 3.9 4.13 

TABLE VI (Unit used kEUR) 

1997 

kEUR 

1998 

kEUR 

1999 

kEUR 

2000 

kEUR 

AMPLAID 

4.650 4.550 3.650 2.950 

WORLD- 

WIDE 96.500 100.500 103.000 102.000 

MARKET 

MARKET 

SHARE % 4.82 4.52 3.54 2.89 

PROFIT 2.500 2.400 2.000 1500 

24


Amplifon SpA 

The following table shows the projections for the sales figures with the improved product for three years 

after the introduction of the ASIC 

The following table shows for a reasonable lifetime the production volumes, the costs and the turnover 

expected for the improved and for the not improved product. 

25


Amplifon SpA 

TABLE VIII (Product sold per year are indicated unit per year; and the second group of columns the 

unit used is KEUR) 

Products sold per year 

(unit/year) 

Costs 

(kEUR 

Turnover 

(kEUR) 

Profit 

(kEUR) 

NOT IMPR. IMPR. TOT. 

1997 1.970 0 2.150 4.650 2.500 

1998 1.600 600 2..200 2.950 5.600 2.650 

1999 1500 1400 2.900 3.450 7.650 4.200 

2000 0 3500 3.500 4.100 10.550 6.450 

We can represent it in graphical form: 

GRAPH II (Unit used kEUR) 

kEUR 

12000 

10000 

8000 

6000 

Turnover Old Prduct 

Turnover New Product 

4000 

2000 

0 

1998 1999 2000 

26


Amplifon SpA 

Economic surveys have been carefully carried on and the results show that the market responds roughly in 

agreement with the estimation made at the time of the preparation of the proposal. The product has been put 

on the market as expected and there are no significant difference between the foreseen costs of the product 

and the actual one. 

The advantages in fact are quite clear to our customers 

‣ Increased portability (the most requested model can be driven by a portable PC) 

‣ Much increased performance and features (more measurements can be carried out with higher precision) 

‣ Very reasonable cost (compared to the old PCB products) 

17. Investment and Return on investment (ROI) 

The estimated cumulated profit increase, in the 4 years expected life, results 6.400 kEUR. This corresponds 

to an estimate of ROI of 43 times the FUSE funding. The payback period, with the same amount, is expected 

less than 1 year. 

Considering that a total investment was sustained for the industrialisation of about 550 kECU 

Which reduces the ROI to 12 times and increases the payback period to 15 months. 

18. Target audience for dissemination throughout Europe. 

The target audience for the present AE is wide and can be identified in the following points: 

• all the company competitors that are still working with PCB solutions; 

• all the company which are working with PCB technology and are willing to shit to an higher level of 

integration but believe that the step might be too difficult; 

• all the companies that need an integration solution not to loose market shares and need to be reassured 

about the success rate of an ASIC solution; 

• all the company that may save money by integrating the devices. 

The most interesting industrial sectors are certainly the one of the biomedical instruments(3310), the one of 

the precision measurement instruments (3320), the process control system manufacturers (3330). Another 

sector to target might be the one of the musical instruments where the Direct Digital Synthesis Technique 

(DDS) can prove to be very effective especially when applied with ASIC technology. 

Moreover a possible target for replication is constituted by all the European Companies that are facing the 

problem of implementing an existing product with a new technology in other to keep the market share. From 

this dissemination document it can be seen that with a careful and realistic planning, with the help of a 

competent subcontractor, and a good training on the job, a microelectronics project can be took to end with 

very good results and with good perspective for the future. 

It is also important to underline that there is an on-going communication plan to present all the products that 

have the IASY inside. 

This product has been selected from the TTN network to represent the FUSE project in the IST (Information 

Society Technology) exhibition to be held in Vienna on 2-3 December 1998. 

An audiometer embedding the IASY component and interfaced to a notebook was exhibited in the FUSE 

both. 

The same audiometer was exhibited in the FUSE both. In the BIAS fair held in Milan on 24-28 November 

1998. 

Several communications were submitted on the IASY subject of which the most important is the paper at the 

1998 IEEE -ISSCC (International Solid State Circuit Conference) in San Francisco in last February. 

27

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