Par4all: Auto-Parallelizing C and Fortran for the CUDA Architecture

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•CUDA generation ◮ (II) • After: 1 p4a_kernel_launcher_0(space, save); [...] 3 void p4a_kernel_launcher_0(float_t space[SIZE][SIZE], float_t save[SIZE][SIZE]) { 5 f o r(i = 1; i
•CUDA generation ◮ (I) • Memory accesses are summed up for each statement as regions for array accesses: integer polytope lattice • There are regions for write access and regions for read access • The regions can be exact if PIPS can prove that only these points are accessed, or they can be inexact, if PIPS can only find an over-approximation of what is really accessed �Par4All in CUDA — GPU conference 10/1/2009 HPC Project, Mines ParisTech, TÉLÉCOM Bretagne, RPI Ronan KERYELL et al. 16 / 46
Page 1 and 2: • ◮ Par4All: Auto-Parallelizing
Page 3 and 4: •Introduction ◮ • Parallelize
Page 5 and 6: •Par4All ◮ 1 Par4All 2 CUDA gen
Page 7 and 8: •Par4All ◮ (I) • PIPS (Interp
Page 9 and 10: •Par4All ◮ • Automatic parall
Page 11 and 12: •CUDA generation ◮ 1 Par4All 2
Page 13 and 14: •CUDA generation ◮ • Find par
Page 15: •CUDA generation ◮ (I) Parallel
Page 19 and 20: •CUDA generation ◮ (I) Conserva
Page 21 and 22: •CUDA generation ◮ • Hardware
Page 23 and 24: •CUDA generation ◮ (II) • So
Page 25 and 26: •CUDA generation ◮ • Reductio
Page 27 and 28: •CUDA generation ◮ (II) • For
Page 29 and 30: •CUDA generation ◮ (I) • CUDA
Page 31 and 32: •CUDA generation ◮ (III) 21 [..
Page 33 and 34: •Results ◮ 1 Par4All 2 CUDA gen
Page 35 and 36: •Results ◮ (I) Average time in
Page 37 and 38: •Results ◮ (I) Average time in
Page 39 and 40: •Conclusion ◮ 1 Par4All 2 CUDA
Page 41 and 42: •Conclusion ◮ Why open source?
Page 43 and 44: •Conclusion ◮ (II) • We have
Page 45 and 46: •Conclusion ◮ (II) • Capitali
Page 47 and 48: •Conclusion ◮ • HPC Project

Par4all: Auto-Parallelizing C and Fortran for the CUDA Architecture

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