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PAPI Utilities: papi_avail• $ utils/papi_avail -h• Usage: utils/papi_avail [options]• Options:• General command options:• -a, --avail Display only available preset events• -d, --detail Display detailed information about all preset events• -e EVENTNAME Display detail information about specified preset or native event• -h, --help Print this help message• Event filtering options:• --br Display branch related PAPI preset events• --cache Display cache related PAPI preset events• --cnd Display conditional PAPI preset events• --fp Display Floating Point related PAPI preset events• --ins Display instruction related PAPI preset events• --idl Display Stalled or Idle PAPI preset events• --l1 Display level 1 cache related PAPI preset events• --l2 Display level 2 cache related PAPI preset events• --l3 Display level 3 cache related PAPI preset events• --mem Display memory related PAPI preset events• --msc Display miscellaneous PAPI preset events• --tlb Display Translation Lookaside Buffer PAPI preset events• This program provides information about PAPI preset and native events.• PAPI preset event filters can be combined in a logical OR.13 th DOE ACTS Workshop: Scalable and Robust Libraruesabd Tiiks fior High-End ComputingTAUhttp://tau.uoregon.edu
PAPI Utilities: papi_avail• $ utils/papi_avail• Available events and hardware information.• --------------------------------------------------------------------------------• PAPI Version : 4.0.0.0• Vendor string and code : GenuineIntel (1)• Model string and code : Intel Core i7 (21)• CPU Revision : 5.000000• CPUID Info : Family: 6 Model: 26 Stepping: 5• CPU Megahertz : 2926.000000• CPU Clock Megahertz : 2926• Hdw Threads per core : 1• Cores per Socket : 4• NUMA Nodes : 2• CPU's per Node : 4• Total CPU's : 8• Number Hardware Counters : 7• Max Multiplex Counters : 32• --------------------------------------------------------------------------------• The following correspond to fields in the PAPI_event_info_t structure.• [MORE…]13 th DOE ACTS Workshop: Scalable and Robust Libraruesabd Tiiks fior High-End ComputingTAUhttp://tau.uoregon.edu41
Page 1: TAU13 th DOE ACTS Workshop: Scalabl
Page 4 and 5: TAU Performance System ®• Integr
Page 6 and 7: TAU Performance System Architecture
Page 8 and 9: Program Database Toolkit (PDT)Appli
Page 10 and 11: Using TAU: A brief Introduction•
Page 12 and 13: ParaProf Profile Analysis Framework
Page 14 and 15: Parallel Profile Visualization: Par
Page 16 and 17: ParaProf: Scatter Plot13 th DOE ACT
Page 18 and 19: Jumpshot [ANL]: Trace Visualization
Page 20 and 21: Inclusive and Exclusive Profiles•
Page 22 and 23: Atomic Events, Context EventsAtomic
Page 24 and 25: Runtime Environment Variables in TA
Page 26 and 27: Memory Leaks in MPI13 th DOE ACTS W
Page 28 and 29: Generating a flat profile with MPI%
Page 30 and 31: Compile-Time Environment Variables
Page 32 and 33: Usage Scenarios: Loop Level Instrum
Page 34 and 35: Usage Scenarios: Compiler-based Ins
Page 36 and 37: Usage Scenarios: Calculate mflops i
Page 38 and 39: Hardware CountersHardware performan
Page 42 and 43: PAPI Utilities: papi_avail• [CONT
Page 44 and 45: PAPI Utilities: papi_native_availUN
Page 46 and 47: PAPI Utilities: papi_event_chooser$
Page 48 and 49: PAPI Utilities: papi_event_chooser$
Page 50 and 51: Derived Metrics in ParaProf13 th DO
Page 52 and 53: Mflops Sorted by Exclusive Timelowm
Page 54 and 55: • Generates program callgraphCall
Page 56 and 57: Tracing MeasurementProcess A:void m
Page 58 and 59: Generate a Trace File% module load
Page 60 and 61: Three Instrumentation Techniques fo
Page 62 and 63: Issues: Linker based substitution
Page 64 and 65: 13 th DOE ACTS Workshop: Scalable a
Page 66 and 67: HDF5 Library Wrapping[sameer@zorak]
Page 68 and 69: Preloading a wrapper library•Prel
Page 70 and 71: 13 th DOE ACTS Workshop: Scalable a
Page 72 and 73: Usage Scenarios: Evaluate Scalabili
Page 74 and 75: Usage Scenarios: Evaluate Scalabili
Page 76 and 77: Performance Regression Testing13 th
Page 78 and 79: Communication Matrix Display• Goa
Page 80 and 81: Communication Matrix13 th DOE ACTS
Page 82 and 83: Measuring Performance of PGI GPGPU
Page 84 and 85: Scalable Visualization: ParaProf (1
Page 86 and 87: ParaProf (1m cores * )13 th DOE ACT
Page 88 and 89: TAU Integration with IDEs• High p
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Choosing PAPI Counters with TAU in
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• U.S. Department of Energy- Offi
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