proposed syllabus for second year degree course in computer

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Unit 5:[6 Hours]Vector Calculus (Integral calculus): The line integral, Surface integral,volume integral, Gauss Divergence theorem, Stoke’s theorem, Green’stheoremUnit 6:[8 Hours]Numerical Methods: Solution of transdental equations by Newton Raphsonmethod, Gauss Seidel method to solve simultaneous linear equations,Lagranges Interpolation formula for unequal intervals, NumericalDifferentiation: - Newton’s forward and Newton’s Backward differenceformulae, Solution of ordinary differential equation by Euler’s modifiedmethod, and Runge-Kutta IV th order method.Note: All Theorems are without proofsSection A: Unit 1, 2, 3Section B: Unit 4, 5, 6Reference Books:1. P. N. Wartikar and J. N. Wartikar, “A Text Book of EngineeringMathematics (Volume-I, II,III),” Pune Vidyarthi Griha Prakashan,Pune.2. B. S. Grewal, “Higher Engineering Mathematics,” KhannaPublications, New Delhi.3. H.K. Das, “Advanced Engineering Mathematics ,” S. Chand &Company.4. B.V. Ramana, “Higher Engineering Mathematics,” (Tata McGraw-Hill).5. Erwin Kreyszig , “Advanced Engineering Mathematics,” WileyEastern Ltd.6. Ravish R Singh, Mukul Bhat, “Engineering Mathematics,” A TutorialApproach, Mc Graw HillPattern of Question Paper:The units in the syllabus shall be divided in two equal sections. Questionpaper shall be set having two sections A and B. Section A questions shall beset on first three units (1,2,3) and Section B questions on remaining threeunits (4,5,6) . Question paper should cover the entire syllabus.For 80 marks Paper:1. Minimum ten questions2. Five questions in each section3. Question no 1 and 6 be made compulsory and should have at least ten bitsof two marks out of which FIVE to be solved.4. Two questions from remaining questions from each section be asked tosolve having weightage of 15 marks
DR. BABASAHEB AMBEDKAR MARATHWADA UNIVERSITY,AURANGABADFACULTY OF ENGINEERING AND TECHNOLOGYTeaching SchemeSecond Year EngineeringSemester-ICSE-202: DIGITAL ELECTRONICSExamination SchemeLectures 4 Hrs/week Theory 80 MarksClass TestDuration of Theory paper20 Marks3HrsObjectives: To understand different methods used for the simplification ofBoolean functions To design and implement combinational circuits To design and implement synchronous sequential circuits To design and implement asynchronous sequential circuitsUNIT – 15 HoursDigital Principles, Digital Logic: Definitions for Digital Signals, DigitalWaveforms, Digital Logic, 7400 TTL Series, TTL Parameters The BasicGates: NOT, OR, AND, Universal Logic Gates: NOR, NAND, Positive andNegative Logic, Introduction to HDL.UNIT – 25 HoursCombinational Logic Circuits Sum-of-Products Method, Truth Table toKarnaugh Map, Pairs Quads, andOctets, Karnaugh Simplifications, Don’t-care Conditions, Product-of-sumsMethod, Product-of-sums simplifications, Simplification by Quine-McClusky Method, Hazards and Hazard Covers, HDL ImplementationModels.UNIT – 310 HoursData-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder,Encoders, Exclusive-or Gates, Parity Generators and Checkers, MagnitudeComparator, Programmable Array Logic, Programmable Logic Arrays, HDLImplementation of Data Processing CircuitsClocks, Flip-Flops: Clock Waveforms, TTL Clock, Schmitt Trigger,Clocked D FLIP-FLOP, Edge-triggered D FLIP-FLOP, Edge-triggered JKFLIP-FLOP, FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, SwitchContact Bounce Circuits, Various Representation of FLIP-FLOPs, Analysisof Sequential Circuits, HDL Implementation of FLIP-FLOP
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