- Page 1 and 2: The SPARC Architecture ManualVersio
- Page 3 and 4: SIMON & SCHUSTER ASIA PTE. LTD., Si
- Page 5 and 6: 3.2.2 Arithmetic/Logical/Shift Inst
- Page 7 and 8: 7.4.1 PIL Control .................
- Page 9 and 10: A.55 Store Integer into Alternate S
- Page 11 and 12: G.1.5 Other Operand Syntax ........
- Page 13 and 14: IntroductionWelcome to SPARC-V9, th
- Page 15 and 16: upward compatibility straightforwar
- Page 17 and 18: the results of this comparison stor
- Page 19 and 20: We’ve also found a way to reduce
- Page 21 and 22: Well, it’s three o’clock in the
- Page 23 and 24: — Chapter 6, “Instructions,”
- Page 25 and 26: tation dependencies are indicated b
- Page 27: designs, allows for straightforward
- Page 31 and 32: 2.14 f register: A floating-point r
- Page 33 and 34: 2.44 normative appendix: An appendi
- Page 35 and 36: 2.68 undefined: An aspect of the ar
- Page 37 and 38: — Enable the FPU and reexecute th
- Page 39 and 40: IMPL. DEP. #6: Whether the I/O regi
- Page 41 and 42: 3.2.7 Register Window ManagementThe
- Page 43 and 44: 4.4 Signed Integer DoubleSD-0Ssigne
- Page 45 and 46: 4.14 Floating-Point Quad PrecisionF
- Page 47 and 48: Table 4—Floating-Point Double-Pre
- Page 49 and 50: 5.1 Nonprivileged RegistersThe regi
- Page 51 and 52: with the 8 in registers of an adjac
- Page 53 and 54: Subsection 6.4, “Register Window
- Page 55 and 56: 5.1.3.2 32-Bit Multiply/Divide Regi
- Page 57 and 58: Figure 6—Double-Precision Floatin
- Page 59 and 60: 5.1.4.1 Floating-Point Register Num
- Page 61 and 62: 5.1.5.1.2 CCR_integer_cond_codes (i
- Page 63 and 64: Table 8—Floating-Point Condition
- Page 65 and 66: The sequence_error and hardware_err
- Page 67 and 68: The qne bit can be read by the STFS
- Page 69 and 70: 5.1.7.11 FSR ConformanceIMPL. DEP.
- Page 71 and 72: Writing PSTATE is nondelayed; that
- Page 73 and 74: 5.2.1.9 PSTATE_interrupt_enable (IE
- Page 75 and 76: 5.2.6 Trap State (TSTATE)TSTATE 1 C
- Page 77 and 78: VER.maxwin contains the maximum ind
- Page 79 and 80:
5.2.10.5 Window State (WSTATE) Regi
- Page 81:
6 InstructionsInstructions are acce
- Page 84:
Figure 33—Summary of Instruction
- Page 87 and 88:
Figure 34—Summary of Instruction
- Page 89 and 90:
s1:This 5-bit field is the address
- Page 91 and 92:
— An STDF or STDFA instruction ac
- Page 93 and 94:
halfword:For a load/store halfword
- Page 95 and 96:
tion. ASIs 80 16 through FF 16 are
- Page 97 and 98:
6.3.2 Memory Synchronization Instru
- Page 99 and 100:
test a condition, represented in th
- Page 101 and 102:
When PSTATE.AM = 1, the value of th
- Page 103 and 104:
6.3.6.1 SAVE InstructionThe SAVE in
- Page 105 and 106:
6.3.7 State Register AccessThe read
- Page 107 and 108:
In addition,spill (fill) trap to a
- Page 109 and 110:
6.4.2.5 Window Trap HandlersThe tra
- Page 111 and 112:
7.2.1 RED_stateRED_state is an acro
- Page 113 and 114:
(4) Cache coherence in RED_state is
- Page 115 and 116:
After a reset that brings the proce
- Page 117 and 118:
upts are disabled (PSTATE.IE = 0) o
- Page 119 and 120:
For the purposes of this subsection
- Page 121 and 122:
SPARC-V9 assumes that lower-priorit
- Page 124 and 125:
Table 14—Exception and Interrupt
- Page 127 and 128:
Table 15—Exception and Interrupt
- Page 129 and 130:
However, the TT values for the exce
- Page 131 and 132:
— Existing state is preservedTSTA
- Page 133 and 134:
— For a register-window trap only
- Page 135 and 136:
If a watchdog reset occurs when the
- Page 137 and 138:
For any reset when TL = MAXTL, for
- Page 139 and 140:
❍ data_access_protection [tt = 03
- Page 141 and 142:
● privileged_opcode [tt = 011 16
- Page 143 and 144:
Figure 41 shows the relationship of
- Page 145 and 146:
8.3 Addressing and Alternate Addres
- Page 147 and 148:
“SPARC-V9 MMU Requirements,” su
- Page 149 and 150:
a memory management unit (MMU), whi
- Page 151 and 152:
An ordering MEMBAR instruction does
- Page 153 and 154:
8.4.5 Mode ControlThe memory model
- Page 155 and 156:
FLUSH has no latency on the issuing
- Page 157 and 158:
Table 22—Instruction Set (Continu
- Page 159 and 160:
Table 22—Instruction Set (Continu
- Page 161 and 162:
A.3 Branch on Integer Register with
- Page 163 and 164:
A.4 Branch on Floating-Point Condit
- Page 165 and 166:
Annulment, delay instructions, and
- Page 167 and 168:
Programming Note:To set the annul b
- Page 169 and 170:
A.6 Branch on Integer Condition Cod
- Page 171 and 172:
(none)
- Page 173 and 174:
Suggested Assembly Language Syntaxb
- Page 175 and 176:
A.8 Call and LinkOpcode op Operatio
- Page 177 and 178:
A compare-and-swap operation behave
- Page 179 and 180:
Programming Note:The rational quoti
- Page 181 and 182:
A.11 DONE and RETRYOpcode op3 fcn O
- Page 183 and 184:
A.13 Floating-Point CompareOpcode o
- Page 185 and 186:
A.14 Convert Floating-Point to Inte
- Page 187 and 188:
A.16 Convert Integer to Floating-Po
- Page 189 and 190:
A.18 Floating-Point Multiply and Di
- Page 191 and 192:
A.20 Flush Instruction MemoryFormat
- Page 193 and 194:
A.21 Flush Register WindowsFormat (
- Page 195 and 196:
A.23 Implementation-Dependent Instr
- Page 197 and 198:
A.25 Load Floating-PointThe LDFSR i
- Page 199 and 200:
A.26 Load Floating-Point from Alter
- Page 201 and 202:
A.27 Load IntegerThe LDD instructio
- Page 203 and 204:
A.28 Load Integer from Alternate Sp
- Page 205 and 206:
data_access_MMU_missdata_access_err
- Page 207 and 208:
A.30 Load-Store Unsigned Byte to Al
- Page 209 and 210:
of the result, icc.z to 1 if bits 3
- Page 211 and 212:
Table 25—MEMBAR mmask EncodingsMa
- Page 213 and 214:
A.33 Move Floating-Point Register o
- Page 215 and 216:
For Integer Condition Codes:Suggest
- Page 217 and 218:
A.34 Move F-P Register on Integer R
- Page 219 and 220:
A.35 Move Integer Register on Condi
- Page 221 and 222:
For Floating-Point Condition Codes:
- Page 223 and 224:
A.36 Move Integer Register on Regis
- Page 225 and 226:
A.37 Multiply and Divide (64-bit)Op
- Page 227 and 228:
Programming Note:32-bit overflow af
- Page 229 and 230:
(4) The sum from step (3) is writte
- Page 231 and 232:
A.41 Population CountOpcode op3 Ope
- Page 233 and 234:
IMPL. DEP. #103(2): Whether the exe
- Page 235 and 236:
Implementation Note:On a multiproce
- Page 237 and 238:
data_access_MMU_miss (implementatio
- Page 239 and 240:
Suggested Assembly Language Syntaxr
- Page 241 and 242:
A.44 Read State RegisterThe RDY ins
- Page 243 and 244:
A.45 RETURNOpcode op3 OperationRETU
- Page 245 and 246:
A.46 SAVE and RESTOREOpcode op3 Ope
- Page 247 and 248:
A.47 SAVED and RESTOREDOpcode op3 f
- Page 249 and 250:
A.49 ShiftOpcode op3 x OperationSLL
- Page 251 and 252:
A.50 Software-Initiated ResetFormat
- Page 253 and 254:
A.52 Store Floating-PointThe STFSR
- Page 255 and 256:
A.53 Store Floating-Point into Alte
- Page 257 and 258:
A.54 Store IntegerThe STD instructi
- Page 259 and 260:
A.55 Store Integer into Alternate S
- Page 261 and 262:
A.56 SubtractOpcode op3 OperationSU
- Page 263 and 264:
async_data_error
- Page 265 and 266:
Exceptions:mem_address_not_alignedp
- Page 267 and 268:
Exceptions:tag_overflow (TADDccTV o
- Page 269 and 270:
Compatibility Note:TSUBccTV traps a
- Page 271 and 272:
Description:The Tcc instruction eva
- Page 273 and 274:
A.62 Write Privileged RegisterForma
- Page 275 and 276:
A.63 Write State RegisterThe WRY in
- Page 277 and 278:
B.1 Traps Inhibit ResultsAs describ
- Page 279 and 280:
In table 27 NaNn means that the NaN
- Page 281 and 282:
SPARC International maintains a doc
- Page 283 and 284:
Number Category2 v 15, 30, 32, 58 N
- Page 285 and 286:
Number Category33 f 98, 114, 114,11
- Page 287 and 288:
Number Category105 f 51 TICK regist
- Page 289 and 290:
DNumber CategoryDef / Refpage #126
- Page 291 and 292:
A memory model is a set of rules th
- Page 293 and 294:
This definition of program order is
- Page 295 and 296:
Rule (1) states that the RMO model
- Page 297 and 298:
Processor 1 Processor 2 Processor 3
- Page 299 and 300:
TProcessor 1 Processor 2 Processor
- Page 301 and 302:
For example, these tools can be use
- Page 303 and 304:
Table 32—op3[5:0] (op =2)op3[3:0]
- Page 305 and 306:
This appendix is informative only.I
- Page 307 and 308:
The above requirements apply only t
- Page 309 and 310:
F.3.3 Information the MMU Sends to
- Page 311 and 312:
More specifically, the MMU performs
- Page 313 and 314:
This appendix is informative only.I
- Page 315 and 316:
i_or_x_cc:An i_or_x_cc specifies a
- Page 317 and 318:
#ASI_PRIMARY 80 16#ASI_SECONDARY 81
- Page 319 and 320:
eg rs1 + reg rs2The resulting opera
- Page 321 and 322:
Table 37—Mapping Synthetic to SPA
- Page 323 and 324:
A procedure may store temporary val
- Page 325 and 326:
Use of a global base register for f
- Page 327 and 328:
(3) If the RESTORE’s implicit add
- Page 329 and 330:
H.1.5 Other Register-Window-Usage M
- Page 331 and 332:
can be compiled as follows, allowin
- Page 333 and 334:
memory. Some of the latency may be
- Page 335 and 336:
— On pipelined machines, there ma
- Page 337 and 338:
is resident. If the memory is not r
- Page 339 and 340:
cross_domain_call:save ! create a n
- Page 341 and 342:
I.1.1 Read/Write Ancillary State Re
- Page 343 and 344:
compare-and-swap stores the supplie
- Page 345 and 346:
Store instructions, and if reading
- Page 347 and 348:
LockWithCAS(lock, ID)retry:mov [ID]
- Page 349 and 350:
J.8 Process Switch SequenceThis sub
- Page 351 and 352:
Code patching involves a modifying
- Page 353 and 354:
FetchAndAddCAS(address, increment)
- Page 355 and 356:
ListInsert(Head, Element) !%i0 = He
- Page 357 and 358:
J.14.2 The Control and Status Regis
- Page 359 and 360:
misaligned stack pointer. Also, mul
- Page 361 and 362:
only software it should affect is a
- Page 363 and 364:
— FLUSHW: Flush windows— FMOVcc
- Page 365 and 366:
Hennessy, J. and D. Patterson. Comp
- Page 367 and 368:
Mowry, T., M. Lam, and A. Gupta.
- Page 369 and 370:
BE instruction, 146, 278Berkeley RI
- Page 371 and 372:
memory, 121, 224unit, memory, 122co
- Page 373 and 374:
BVS, 146FBE, 140FBfcc, 140FBG, 140F
- Page 375 and 376:
watchdog_reset (WDR), 108window_fil
- Page 377 and 378:
IEEE_754_exception, 10, 46, 46, 48,
- Page 379 and 380:
generating constants, 220global reg
- Page 381 and 382:
s2, 13, 68, 137, 152, 154, 158, 159
- Page 383 and 384:
LD instruction (SPARC-V8), 179LDA i
- Page 385 and 386:
Prefetchable attribute, 284Primary
- Page 387 and 388:
N condition code bit, see negative
- Page 389 and 390:
prefetch_fcn, 295PREFETCHA instruct
- Page 391 and 392:
egistersaddress space identifier (A
- Page 393 and 394:
SDIV instruction, 36, 154SDIVcc ins
- Page 395 and 396:
synthetic instructions, 2BCLR, 299B
- Page 397 and 398:
eset, 56, 95, 96, 97, 105, 255softw
- Page 399:
xcc field of CCR register, 41, 137,