Simulation-based Verification with APRICOT Framework using High ...

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Stimuli(Testbench)Design(VHDL)RTL toBeh.Test vectors in plain textVHDL to HLDDInterfaceConverters viaIntermediate Formatsof APRICOT PartnersVariety of HLDDrepresentation typesHLDDModelCoverage mappingHLDD-basedSimulationCoverageAnalysisDebuggerAssertionCheckingAssertions(PSL)PSL FLSubsetPSL to THLDDInterfaceTHLDDModelApplication-optimized THLDDATPG and FormalProperty Checking(DECIDER engine)Non-terminal nodes represent the design’s conditionalstatements and control signals. Edges determine theactivation conditions for the transaction to the nextnode and are marked by scalar variable values.Terminal nodes in the HLDD model normallydetermine assignment statements, operations or inputs.For example, for the HLDD given in Figure 1, inputvector {x 1 ,x 2 ,x 3 ,x 3 }={4,2,-,-} will activate a path from ythrough m 0 to m 4 and evaluate output y to 4.More detailed and formal definition of HLDD canbe found in [2]. More examples of designrepresentation by HLDDs are provided in Section 3.Figure 2 shows verification flow within theAPRICOT framework. The format of the design underverification (DUV) that is natively supported byAPRICOT is VHDL. The framework has a proprietaryautomatic interface from this design’s description toHLDD representation model. There are also availableadditional interfaces to the APRICOT partners’internal and intermediate formats (and thereforeindirect support for several standard formats such asSystemC).Once the DUV is converted to HLDD it can besimulated with HLDD-based simulator under theprecomputed set of stimuli. The simulator has asupport for structural coverage analysis and assertionchecking. The latter requires assertions to berepresented by Temporally extended HLDD (THLDD)graphs. The framework has automatic interface forTHLDD graphs creation from the IEEE-1850 standardProperty Specification Language (PSL) assertions.Both VHDL to HLDD and PSL to THLDDinterfaces are capable create graphs variable by theirtarget application specific parameters, e.g.compactness. The benefits of this will be discussed inthe next sections.Figure 2. Hardware verification framework APRICOTThe framework also considers hierarchical testpattern generation and formal property checking, aswell as a HLDD-based debugger that exploits themodel’s easy cause-effect relationship diagnosability.These tasks are emphasized by dashed lines in thefigure and not discussed further in this paper.The approaches of the APRICOT frameworkaddressing the simulation-based verification tasks arediscussed in more detail in the next two sections. Theyare also implemented as a tool called ApricotCAD [6](Figure 3).Figure 3. GUI of ApricotCAD3. Code coverage analysisThe most widely used in industry structuralcoverage (aka code coverage) metrics are statement,branch and condition coverage ones [7].
In [8] and [9] we have proposed to map HDL (e.g.VHDL) statement and branch coverage metrics toHLDD-based coverage. The statement coverage mapsdirectly to the ratio of traversed HLDD nodes m duringthe HLDD simulation to the total number of the HLDDnodes in the DUV’s representation. Similar to thestatement coverage, branch coverage is the ratio ofevery activated in the simulation process HLDD edge eto the total number of edges in the correspondingHLDD representation of the DUV.As an example, please consider the VHDLdescription of a DUV provided in Figure 4. Thenumbers from the first column (Stm) correspond to thelines with 10 conditional and assignment statements.The 14 HLDD nodes of the two graphs V1 and V2 inthe same figure correspond to these statements. Theunderlined numbers from the second column (Brn)correspond to the lines with 7 branches. The 12 HLDDedges of the two graphs V1 and V2 correspond to thesedecisions. The APRICOT framework tools distinguishbetween several compactness levels of HLDDrepresentations that provide different tradeoffsbetween the analysis stringency and simulation speedwith memory requirements.Stm Brn VHDL code:...1 if (cS1_C1 andcS1_C2)1 then2 V1
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