Nexys4 DDR FPGA Board Reference Manual 1 Overview

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Nexys4 DDR FPGA Board Reference Manual Buttons Slide Switches 3.3V 1.8V BTNL BTNR BTNU BTND BTNC 3.3V SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 P17 M17 M18 P18 N17 J15 L16 M13 R15 R17 T18 U18 R13 T8 H17 K15 J13 N14 R18 V17 U17 U16 V16 T15 U14 T16 V15 V14 V12 V11 U13 K2 T14 P14 J14 T9 J18 J17 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 AN7 LEDs 3.3V AN6 AN5 AN4 AN3 7-seg Display AN2 AN1 AN0 SW9 U8 SW10 SW11 SW12 SW13 SW14 SW15 R16 T13 H6 U12 U11 V10 T10 R10 K16 K13 P15 T11 L18 H15 CA CB CC CD CE CF CG DP 5.0V CPU Reset 3.3V BTNRES C12 Artix-7 N16 R11 G14 N15 M16 R12 Tri-Color LEDs R17 LD17 G17 B17 R16 LD16 G16 B16 Figure 16. General Purpose I/O devices on the Nexys4 DDR. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 18 of 29
Nexys4 DDR FPGA Board Reference Manual The sixteen individual high-efficiency LEDs are anode-connected to the FPGA via 330-ohm resistors, so they will turn on when a logic high voltage is applied to their respective I/O pin. Additional LEDs that are not user-accessible indicate power-on, FPGA programming status, and USB and Ethernet port status. 10.1 Seven-Segment Display The Nexys4 DDR board contains two four-digit common anode seven-segment LED displays, configured to behave like a single eight-digit display. Each of the eight digits is composed of seven segments arranged in a “figure 8” pattern, with an LED embedded in each segment. Segment LEDs can be individually illuminated, so any one of 128 patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark, as shown in Figure 17. Of these 128 possible patterns, the ten corresponding to the decimal digits are the most useful. Figure 17. An un-illuminated seven-segment display and nine illumination patterns corresponding to decimal digits. The anodes of the seven LEDs forming each digit are tied together into one “common anode” circuit node, but the LED cathodes remain separate, as shown in Fig 18. The common anode signals are available as eight “digit enable” input signals to the 8-digit display. The cathodes of similar segments on all four displays are connected into seven circuit nodes labeled CA through CG. For example, the eight “D” cathodes from the eight digits are grouped together into a single circuit node called “CD.” These seven cathode signals are available as inputs to the 8-digit display. This signal connection scheme creates a multiplexed display, where the cathode signals are common to all digits but they can only illuminate the segments of the digit whose corresponding anode signal is asserted. To illuminate a segment, the anode should be driven high while the cathode is driven low. However, since the Nexys4 DDR uses transistors to drive enough current into the common anode point, the anode enables are inverted. Therefore, both the AN0..7 and the CA..G/DP signals are driven low when active. Common anode AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 F A B CA CB CC CD CE CF CG DP Eight-digit Seven Segment Display CA CB CC CD CE CF CG DP E G C D Individual cathodes DP Figure 18. Common anode circuit node. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 19 of 29
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Nexys4 DDR FPGA Board Reference Manual 1 Overview

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