Technion Presentation - OCP-IP

More documents

Recommendations

Info

■ General techniques • Stop/start subsystem clocks • Dynamic clock frequency • On/off voltage domains • Dynamic voltage/frequency domains (DVFS) ■ IP-specific techniques • ARM big.LITTLE (use optimum IP for loading) ■ Power managers implement the techniques • Software: flexible, but slow • Hardware: very responsive, but less flexible difficulty Managing Dark Silicon… 6/24/2012 Technion Presentation 14
Example Tablet Application Processor 533MHz Cortex A15 Quad core CPU Sonics MemMax Memory Scheduler DRAM Cont. CPU CPU CPU 533MHz 1333MHz 1066MHz 533MHz L2 Cache 133MHz ROM Secure ROM Cortex A7 Quad core 133MHz CPU Security SRAM Sonics MemMax Memory Scheduler DRAM Cont. CPU CPU CPU 533MHz 267MHz 1066MHz 1066MHz L2 Cache DMA 267MHz 533MHz Mali-T658 Quad core GPU GPU GPU GPU Coherency Fabric HDMI SonicsGN On-chip Network 133MHz Ethernet 133MHz PCIe 267MHz 6/24/2012 Technion Presentation 267MHz LCD Controller 400MHz Audio Video Codec 267MHz 200MHz Power Domains 15 Sonics3220 Peripheral Network 133MHz USB 200MHz Cam 1 133MHz SATA APB Peripherals 133MHz Cam 2 1066MHz
Page 1 and 2: Technion Presentation Drew Wingard
Page 3 and 4: Enabling Billons of Connected Devic
Page 5 and 6: Our Communications Architecture ■
Page 7 and 8: Sonics View on NoC ■NoC adapts ke
Page 9 and 10: Why So Fast? ■ We’re fully conv
Page 11 and 12: Integration: Giga-SoC Performance N
Page 13: But What About Power? ■ Convergen
Page 17 and 18: Summary ■ GHz, GFLOPs and GB/sec
Page 19 and 20: SonicsGN (SGN) Benefits ■ Only Ne
Page 21 and 22: On-Chip Network - Under the Hood
Page 23 and 24: Design Capture Master core Socket I
Page 25 and 26: Power Partitioning 6/24/2012 Techni
Page 27 and 28: High Performance Consumer SoC Memor
Page 29 and 30: Consumer SoC Examples ■ What are
Page 31 and 32: Concurrency in Consumer SoCs H.264
Page 33 and 34: Outline ■ Multicore consumer SoC
Page 35 and 36: 6/24/2012 Technion Presentation 35
Page 37 and 38: Utilization Rate ■ Utilization Ra
Page 39 and 40: How Traffic Impacts DRAM Utilizatio
Page 41 and 42: Locality Challenges: DRAM Access St
Page 43 and 44: Access Granularity: DRAM Burst Size
Page 45 and 46: Outline ■ Multicore consumer SoC
Page 47 and 48: Single-ported Memory Subsystems Sha
Page 49 and 50: In-order Protocol ■ Interface pro
Page 51 and 52: Out-of-order Protocol with Non-bloc
Page 53 and 54: Optimizing for High Utilization Goa
Page 55 and 56: Multichannel Solves Access Granular
Page 57 and 58: Interleaved Multichannel Technology
Page 59 and 60: 2D Bursts, Address Tiling & Multich
Page 61 and 62: DRAM-limited Consumer SoCs: Solutio
Page 63 and 64: Futures
Page 65 and 66:
Wide I/O: TSV-enabled Mobile DRAM
Page 67:
THANK YOU!
show all

Technion Presentation - OCP-IP

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?