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<strong>HCD</strong>-<strong>GZR7D</strong>/<strong>GZR8D</strong>/GZR9D<br />
88<br />
Pin No. Pin Name I/O Description<br />
56 to 62 HA2 to HA8 O Host address output bit 2 to 8<br />
63, 64 HA18, HA19 O Host address output bit 18, 19<br />
65 DVDD3 — Power supply pin (+3.3 V) for internal digital circuitry<br />
66 XWR O Write enable output (active Low)<br />
67 to 74 HA16 to HA9 O Host address output bit 16 to 9<br />
75 HA20 O Host address output bit 20<br />
76 XROMCS O Chip select output (active Low)<br />
77 HA1 O Host address output bit 1<br />
78 XRD O Read enable output (active Low)<br />
79, 80 HD0, HD1 O Host data output bit 0, 1<br />
81 DVSS — Ground pin for internal digital circuitry<br />
82 to 86 HD2 to HD6 O Host data output bit 2 to 6<br />
87 HA21 O Host address output bit 21<br />
88 RESERVED O Not used. (Open)<br />
89 HD7 O Host data output bit 7<br />
90 DVSS — Ground pin for internal digital circuitry<br />
91 HA17 O Host address output bit 17<br />
92 HA0 O Host address output bit 0<br />
93 DVDD18 — Power supply pin (+1.8 V) for internal digital circuitry<br />
94 FWD O Forward signal output for loading motor driver (Not used in this set)<br />
95 REV O Reserve signal output for loading motor driver (Not used in this set)<br />
96 DVDD3 — Power supply pin (+3.3 V) for internal digital circuitry<br />
97 IFSDO O External CPU serial data output (H/W method)<br />
98 IFCK O External CPU serial clock output (H/W method)<br />
99 xIFCS O External CPU serial chip select output (active Low, H/W method)<br />
100 IFSDI I External CPU serial data input (H/W method)<br />
101 SCL O I2C clock output for EEPROM<br />
102 SDA O I2C data output for EEPROM<br />
103 CKSW I Chucking switch detection input (Not used in this set)<br />
104 OCSW I Open/close switch detection input (Not used in this set)<br />
105 RXD I Hardwired RS232C RXD input<br />
106 TXD O Hardwired RS232C TXD output<br />
107 ICE I ICE mode enable input (Not used in this set)<br />
108 xSYSRST I MT1389 reset input (active Low)<br />
109 RESERVED I Not used. (Open)<br />
110 xIFBSY I External CPU ready/busy interrupt signal input (L: ready, H: busy)<br />
111 DQM0 O Mask for DRAM output byte 0<br />
112 EEWP O EEPROM write protect control output (L: write allowed)<br />
113 to 117 RD7 to RD3 O DRAM data output bit 7 to 3<br />
118 DVDD3 — Power supply pin (+3.3 V) for internal digital circuitry<br />
119 to 121 RD2 to RD0 O DRAM data output bit 2 to 0<br />
122 to 129 RD15 to RD8 O DRAM data output bit 15 to 8<br />
130 TSD_M I Thermal shutdown monitor input<br />
131 DVDD3 — Power supply pin (+3.3 V) for internal digital circuitry<br />
132 DQM1 O Mask for DRAM output byte 1<br />
133 _RWE O DRAM write enable output<br />
134 _CAS O DRAM column address strobe output<br />
135 _RAS O DRAM row address strobe output<br />
136 _RCS O DRAM chip select output<br />
137, 138 BA0, BA1 O DRAM bank address output 0, 1<br />
139 RA10 O DRAM address output bit 10<br />
140, 141 RA0, RA1 O DRAM address output bit 0, 1<br />
142 DVDD18 — Power supply pin (+1.8 V) for internal digital circuitry<br />
143, 144 RA2, RA3 O DRAM address output bit 2, 3<br />
145 DVDD3 — Power supply pin (+3.3 V) for internal digital circuitry<br />
146 DRCLK O DRAM clock output
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