Problem Determination Guide - Systems Group

JTAG
Each processor has an interface onto a control system. The protocol used is
called the Joint Technical Advisory Group (JTAG) interface, which is an Institute
of Electrical and Electronic Engineers (IEEE) 1149.1 standard. The IDo chip
converts the 100 Mbps ethernet bus into 40 JTAG buses, two for each Compute
Node (32 in all, one for control of each processor), two for each of the I/O nodes
(4 in all, one for control of each processor), and four for the gigabit ethernet
transceivers that are associated with the I/O nodes. On Blue Gene/L, JTAG
provides:
► Hardware control to turn on the CPU and start its clock.
► Hardware diagnostic and debugging.
► Delivery of the microloader to each CPU to start the boot process.
► A mailbox function for recording messages from the MCP or CNK, which are
used for recording RAS events.
Figure 1-22 illustrates node cards links to the JTAG network.
Figure 1-22 Node cards links to the JTAG network
Chapter 1. Introduction 23