PNX85500 – Single Chip LCD TV System with ... - Hot Chips
PNX85500 – Single Chip LCD TV System with ... - Hot Chips
PNX85500 – Single Chip LCD TV System with ... - Hot Chips
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
<strong>PNX85500</strong> <strong>Single</strong> <strong>Chip</strong> <strong>LCD</strong> <strong>TV</strong> <strong>System</strong><br />
<strong>with</strong> integrated 120Hz HD Frame Rate Converter<br />
Colin Osborne / Ralf Karge<br />
<strong>PNX85500</strong> <strong>Single</strong> <strong>Chip</strong> <strong>LCD</strong> <strong>TV</strong> <strong>System</strong><br />
<strong>Hot</strong> <strong>Chip</strong>s 2009<br />
August, 25, 2009
Presentation Outline<br />
Introduction<br />
<strong>System</strong> Integration<br />
<strong>–</strong> More <strong>TV</strong> <strong>System</strong> on a <strong>Chip</strong><br />
<strong>–</strong> <strong>PNX85500</strong> <strong>TV</strong> Solution<br />
Design Challenges<br />
<strong>–</strong> Architecture<br />
<strong>–</strong> Memory Bandwidth and Latency<br />
<strong>–</strong> Verification and Emulation<br />
High-lighted Features<br />
Conclusions<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
2<br />
25-Aug-2009
Introducing the <strong>TV</strong>550 <strong>System</strong><br />
<strong>TV</strong>550 <strong>System</strong> comprises the world’s first Digital <strong>TV</strong> SoC in C045: <strong>PNX85500</strong><br />
Extremely high level of functional integration<br />
• Channel demodulators, networking (USB, HDMI, Ethernet, SD card reader),<br />
120 Hz, H.264 HD decoding, advanced Picture Quality Algorithms, etc.<br />
Smallest memory requirement for the total system<br />
• Full application (networking, H.264 HD decoding, advanced gfx, FRC, …) all<br />
on 2x16-bit DDR2 footprint!<br />
Drives industry’s lowest cost-of-ownership/bill-of-material<br />
• Avoid expensive EMI protection <strong>with</strong> built-in spread-spectrum on both LVDS<br />
as well as DDR interfaces<br />
Enables development for global chassis roll out thanks to<br />
low system costs<br />
• Minimize upfront development costs and time-to-market for global rollout<br />
• One development, one PCB line, one test set up<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
3<br />
25-Aug-2009
Introduction<br />
<strong>System</strong> Integration<br />
<strong>–</strong> More <strong>TV</strong> <strong>System</strong> on a <strong>Chip</strong><br />
<strong>–</strong> <strong>PNX85500</strong> <strong>TV</strong> Solution<br />
Design Challenges<br />
<strong>–</strong> Architecture<br />
<strong>–</strong> Memory Bandwidth and Latency<br />
<strong>–</strong> Verification and Emulation<br />
High-lighted Features<br />
Conclusions<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
4<br />
25-Aug-2009
<strong>TV</strong>550 <strong>System</strong> Integration<br />
Tuner<br />
TDA18272<br />
Silicon Tuner<br />
CVBS,Y/C,<br />
RGB L/R<br />
YCbCr<br />
SPDIF<br />
RGB, HV<br />
L/R<br />
Switch<br />
TDA9996<br />
<strong>PNX85500</strong><br />
Analog IF IP<br />
TDA8296<br />
HDMI<br />
Switch<br />
DVB-C Channel<br />
Decoder<br />
TDA10024<br />
DVB-T Channel<br />
Decoder<br />
TDA10048<br />
Low-IF<br />
CVBS/SIF<br />
TS<br />
PCMCIA<br />
CI+<br />
Ethernet<br />
MAC<br />
DDR2<br />
256MB<br />
NXP<br />
PNX8543<br />
MIPS32@300 MHz<br />
Pixel OSD, <strong>TV</strong> Control,<br />
HDMI,USB,PC-AVI<br />
PNX8543<br />
32 bit<br />
DDR2-666<br />
FLASH<br />
128 MB<br />
L/R<br />
LVDS-2<br />
CVBS<br />
SPDIF<br />
L,R<br />
L,R<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
32 bit<br />
DDR2-666<br />
DDR2<br />
128MB<br />
NXP<br />
PNX5120<br />
Frame Rate<br />
Conversion<br />
NXP<br />
TFA9810<br />
Audio Amplifier<br />
HD 1080p<br />
100/120Hz<br />
50/60Hz<br />
5<br />
25-Aug-2009
<strong>TV</strong>550 <strong>System</strong> Integration<br />
Tuner<br />
TDA18272<br />
Silicon Tuner<br />
CVBS,Y/C,<br />
RGB L/R<br />
YCbCr<br />
SPDIF<br />
RGB, HV<br />
L/R<br />
Switch<br />
TDA9996<br />
<strong>PNX85500</strong><br />
Analog IF IP<br />
TDA8296<br />
HDMI<br />
Switch<br />
DVB-C Channel<br />
Decoder<br />
TDA10024<br />
DVB-T Channel<br />
Decoder<br />
TDA10048<br />
Low-IF<br />
CVBS/SIF<br />
TS<br />
PCMCIA<br />
CI+<br />
Ethernet<br />
MAC<br />
DDR2<br />
256MB<br />
NXP<br />
NXP<br />
PNX8543<br />
<strong>PNX85500</strong><br />
MIPS32@300 MHz<br />
Pixel OSD, <strong>TV</strong> Control,<br />
HDMI,USB,PC-AVI<br />
PNX8543<br />
32 bit<br />
DDR2-666<br />
FLASH<br />
128 MB<br />
L/R<br />
LVDS-2<br />
CVBS<br />
SPDIF<br />
L,R<br />
L,R<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
32 bit<br />
DDR2-666<br />
DDR2<br />
128MB<br />
NXP<br />
PNX5120<br />
Frame Rate<br />
Conversion<br />
NXP<br />
TFA9810<br />
Audio Amplifier<br />
HD 1080p<br />
100/120Hz<br />
50/60Hz<br />
6<br />
25-Aug-2009
<strong>TV</strong>550 <strong>–</strong> FRC 120Hz FULL HD<br />
DVB-T, CI+, PAL/SECAM, IP<br />
<strong>TV</strong>550<br />
CI+<br />
TDA18272<br />
Si Tuner<br />
HDMI<br />
DDR2<br />
128 DDR2 MB<br />
128 MB<br />
TDA9996<br />
switch<br />
HDMI<br />
PNX8550x<br />
FLASH<br />
64 MB<br />
DIGITAL<br />
AUDIO IN<br />
HDMI HDMI<br />
DIGITAL<br />
AUDIO OUT<br />
USB<br />
PHY<br />
Ethernet<br />
TFA9810<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
7<br />
25-Aug-2009
<strong>TV</strong>550 <strong>–</strong> FRC 120Hz FULL HD<br />
DMB-T/ATSC/ISDB-T, PAL/SECAM/NTSC, IP<br />
<strong>TV</strong>550<br />
TDA18272<br />
Si Tuner<br />
Optional China CI+<br />
Channel<br />
Demod<br />
HDMI<br />
DDR2<br />
128 DDR2 MB<br />
128 MB<br />
TDA9996<br />
switch<br />
HDMI<br />
PNX8550x<br />
FLASH<br />
64 MB<br />
DIGITAL<br />
AUDIO IN<br />
HDMI HDMI<br />
DIGITAL<br />
AUDIO OUT<br />
USB<br />
PHY<br />
Ethernet<br />
TFA9810<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
8<br />
25-Aug-2009
<strong>PNX85500</strong> Block Diagram<br />
SYS_CTRL<br />
Interrupts<br />
CLOCKS<br />
RESET<br />
JTAG<br />
UART<br />
PC_AVI<br />
Channel<br />
Decode<br />
HDMI_RX<br />
Audio Decoding<br />
Audio Processor<br />
RTC<br />
MIPS24K <strong>–</strong> Control Network<br />
FLASH_CTRL<br />
MIPS24K<br />
I2C<br />
PC_AVI<br />
Transport<br />
Stream Input<br />
CAI<br />
USB<br />
R<br />
W<br />
R<br />
R<br />
W<br />
2D Drawing<br />
R<br />
W<br />
GFX_SCALER<br />
ETHERNET<br />
R<br />
R<br />
W<br />
SPI<br />
SD Card<br />
R<br />
W<br />
R<br />
W<br />
R<br />
W<br />
R<br />
W<br />
W<br />
R<br />
W<br />
R<br />
W<br />
A<br />
MCU_DDR<br />
(32bit)<br />
MEM_ARB<br />
A<br />
DMA Network<br />
BRIDGE<br />
R<br />
W<br />
R<br />
W<br />
R<br />
W<br />
R<br />
W<br />
W<br />
R/W<br />
R<br />
W<br />
R<br />
W<br />
R<br />
W<br />
R<br />
W<br />
R<br />
W<br />
R<br />
W<br />
R<br />
W<br />
W<br />
R<br />
W<br />
R<br />
Digital Video<br />
Decoder<br />
AV-DSP<br />
Frame<br />
Rate<br />
Converter<br />
MPEG Demux<br />
Scatter/Gather<br />
DMA<br />
Video Scaler (1)<br />
Video<br />
Composition<br />
Pipe (1)<br />
Video<br />
Input Processor<br />
Video Scaler (2)<br />
Video<br />
Composition<br />
Pipe (2)<br />
PC_AVI<br />
SPDIF<br />
Digital Video Generic Processing Broadcast Audio Control Processing and / and Transport Interconnect<br />
Graphics<br />
Stream<br />
I2S<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
AVDSP <strong>–</strong> Control Network<br />
Interrupts<br />
GPIO<br />
LVDS_TX<br />
DENC<br />
Key<br />
Control Network<br />
DMA Network<br />
R DMA Read<br />
W DMA Write<br />
9<br />
25-Aug-2009
Introduction<br />
<strong>System</strong> Integration<br />
<strong>–</strong> More <strong>TV</strong> <strong>System</strong> on a <strong>Chip</strong><br />
<strong>–</strong> <strong>PNX85500</strong> <strong>TV</strong> Solution<br />
Design Challenges<br />
<strong>–</strong> Architecture<br />
<strong>–</strong> Memory Bandwidth and Latency<br />
<strong>–</strong> Verification and Emulation<br />
High-lighted Features<br />
Conclusions<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
10<br />
25-Aug-2009
Organizational Complexity<br />
World-wide multi-site<br />
project<br />
<strong>–</strong> UK, Netherlands,<br />
Germany, France,<br />
India, Israel, USA<br />
Number of IPs<br />
<strong>–</strong> Approx 100 IP blocks<br />
(85% NXP-internal)<br />
Compute infra metrics<br />
<strong>–</strong> 15 TBytes of disk<br />
space<br />
<strong>–</strong> 3 TBytes of RAM for<br />
SoC Integration<br />
Chicago<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
Southampton Caen Hamburg<br />
San Jose Eindhoven Haifa Bangalore<br />
11<br />
25-Aug-2009
Integrating many different functions<br />
MIPS24K<br />
Audio and<br />
Video<br />
Capture<br />
Connectivity<br />
Interfaces<br />
Function Examples<br />
Established HW functions Analogue audio/video decoding<br />
High performance HW functions Video scaling & composition<br />
Control processing Generic operating system<br />
Flexible DSP Audio & video feature processing<br />
High performance DSP Motion Accurate Picture Processing<br />
Analogue<br />
Standards<br />
Decoder<br />
Digital Audio<br />
Decoder<br />
Audio<br />
Post-Processing<br />
Audio<br />
Presentation<br />
MPEG<br />
Demux &<br />
Descrambler<br />
MPEG/H.264<br />
Video Decoder<br />
Flexible<br />
Video Decoder<br />
Graphics<br />
Rendering<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
Picture Quality<br />
Processing<br />
Frame Rate<br />
Conversion<br />
Auto Picture<br />
Control<br />
Video<br />
Presentation<br />
12<br />
25-Aug-2009
Challenging Bandwidth and Latency Needs<br />
Cost pressure only allows 2 x 16 DDR2-1066<br />
Critical<br />
MIPS24K<br />
• Limiting gross bandwidth to 4.2 Gbytes/sec<br />
• Originally the <strong>TV</strong>550 system was expected to need 64-bit DDR interface<br />
Requiring high-bandwidth and low-latency<br />
• Processors for flexible processing: requiring low-latency to minimise cache miss penalty<br />
• Hardware traffic mostly predictable: requiring high-bandwidth<br />
Innovative solutions<br />
• Processors supported by specific arbitration settings in infrastructure<br />
• Hardware units and VLIW pre-fetch memory accesses<br />
• Local caches/buffers<br />
• Video streaming between IP functions<br />
Critical Tolerant<br />
Embedded<br />
Control CPU<br />
Digital Video<br />
Decoder<br />
Memory Subsystem <strong>with</strong> Arbitration and Buffering<br />
Critical Tolerant Critical Tolerant<br />
FRC<br />
Processor<br />
FRC Coprocessor<br />
AVDSP<br />
Processor<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
Audio<br />
Processor<br />
Tolerant<br />
Video Comp.<br />
Pipe(s)<br />
Tolorant<br />
Video<br />
Scaler(s)<br />
13<br />
25-Aug-2009
Assuring fast Silicon Bring-Up<br />
Extensive suite of verification methods<br />
Various abstraction levels in simulation of<br />
<strong>–</strong> IP functionality and connectivity<br />
<strong>–</strong> SoC infrastructure performance<br />
Emulation of representative Software and<br />
Hardware<br />
<strong>–</strong> 300 million gates of IC emulation capacity<br />
<strong>–</strong> <strong>System</strong> tuning and performance sign-off<br />
<strong>–</strong> 300 - 400 k frames of HD video before<br />
tape out<br />
Advance system software development<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
Emulation<br />
All main use-cases had been brought up on the emulator before silicon<br />
<strong>–</strong> Software was ready when silicon arrived<br />
<strong>–</strong> Arbitration and tuning settings had been verified<br />
=> Very rapid silicon bring-up<br />
14<br />
25-Aug-2009
<strong>PNX85500</strong> Silicon<br />
• TSMC's 45nm Low Power (LP)<br />
process technology<br />
• 27 mm Flip <strong>Chip</strong> BGA Package<br />
• Power Consumption < 7 Watt<br />
• No active cooling required<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
15<br />
25-Aug-2009
Introduction<br />
<strong>System</strong> Integration<br />
<strong>–</strong> More <strong>TV</strong> <strong>System</strong> on a <strong>Chip</strong><br />
<strong>–</strong> <strong>PNX85500</strong> <strong>TV</strong> Solution<br />
Design Challenges<br />
<strong>–</strong> Architecture<br />
<strong>–</strong> Memory Bandwidth and Latency<br />
<strong>–</strong> Verification and Emulation<br />
High-lighted Features<br />
Conclusions<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
16<br />
25-Aug-2009
Complex SoC made up by Complex IPs<br />
Example: Video Scaler<br />
VCAR<br />
MPEG Artefact<br />
Reduction<br />
STDI<br />
De-interlacer<br />
TNR<br />
Temporal Noise<br />
Reduction<br />
AHSC<br />
Horizontal scaler<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
PCOR<br />
Projection data<br />
for film detector<br />
17<br />
25-Aug-2009
Complex SoC made up by Complex IPs<br />
Example: Video Composition Pipe<br />
PCTI<br />
Peaking-based<br />
Color Transient<br />
Improvement<br />
VSHR<br />
Video Sharpening<br />
SKCR<br />
Skin-tone Control<br />
DI2D<br />
2-Dimensional<br />
Backlight Dimming<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
BSKY<br />
Blue-Sky<br />
Enhancement<br />
18<br />
25-Aug-2009
Motion Accurate Picture Processing<br />
Film Judder Cancellation + Motion Blur Reduction<br />
A<br />
B<br />
Original Movie<br />
24 frames per second<br />
Typical <strong>TV</strong><br />
at 50 or 60 frames<br />
per second<br />
(<strong>with</strong> ‘movie judder’)<br />
<strong>PNX85500</strong> output<br />
at 120 frames<br />
per second; after<br />
movie judder removal<br />
A<br />
24 Hz film<br />
A A A B B<br />
2 3 4 5 B 7 8 9 10<br />
High quality smooth, natural-looking motion<br />
- analysed and created<br />
- in real-time, for HD video content<br />
- at 120 frames per second<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
19<br />
25-Aug-2009
Improved Picture Quality at Reduced Power<br />
2D Local Dimming Processing<br />
Histogram<br />
Video<br />
input<br />
<strong>PNX85500</strong><br />
FRC Processor<br />
Image Analysis<br />
Backlight<br />
calculation<br />
+<br />
Video<br />
Gain<br />
Backlight output Video output<br />
Perceived output<br />
Video on backlight<br />
=<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
Reduce <strong>LCD</strong> <strong>TV</strong>’s<br />
backlight power by<br />
about 50%<br />
Significant increase<br />
of contrast and black<br />
level<br />
Histogram<br />
measurement and<br />
pixel processing<br />
done in HW-IP<br />
Flexible processing<br />
of VLIW processor<br />
for image analysis<br />
and backlight<br />
calculation<br />
20<br />
25-Aug-2009
Introduction<br />
<strong>System</strong> Integration<br />
<strong>–</strong> More <strong>TV</strong> <strong>System</strong> on a <strong>Chip</strong><br />
<strong>–</strong> <strong>PNX85500</strong> <strong>TV</strong> Solution<br />
Design Challenges<br />
<strong>–</strong> Architecture<br />
<strong>–</strong> Memory Bandwidth and Latency<br />
<strong>–</strong> Verification and Emulation<br />
High-lighted Features<br />
Conclusions<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
21<br />
25-Aug-2009
Conclusions<br />
<strong>PNX85500</strong>: the world’s first D<strong>TV</strong> SoC in 45nm<br />
•Very high level of integration<br />
•Award-winning 120 Hz processing in front-end <strong>TV</strong> SoC<br />
•Enabling global chassis, single platform<br />
Performance critical<br />
•Iterative analysis and optimisation through design cycle<br />
•Solving challenging demands on memory latency<br />
Verification challenge<br />
•Very high level of integration creates challenges in interdependency and complexity<br />
•Extensive use of prototyping using emulation and FPGA<br />
First silicon arrived in Q1 2009<br />
•Successful customer demonstrations <strong>with</strong>in 2 weeks of first silicon!<br />
What’s next?<br />
•Higher integration levels, lower system cost<br />
•Improved picture quality, increased frame rates and resolution<br />
•New video features<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
22<br />
25-Aug-2009
Questions<br />
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
23<br />
25-Aug-2009
<strong>PNX85500</strong> / <strong>Hot</strong><strong>Chip</strong>s / C.Osborne, R. Karge<br />
24<br />
25-Aug-2009
Change language