UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3) - Silvaco

HiSIM HV
SPICE Model Extraction and TCAD Validation

Overview
Device structures and characteristics for standard MOS, LDMOS and
XDMOS simulated using Silvaco’s ATHENA process and ATLAS device
TCAD simulators
Simulation of DC, capacitance and self-heating for
HiSIM HV
HiSIM HV SPICE model parameter optimization to TCAD simulated
results using UTMOST IV
HiSIM HV LDMOS – UTMOST IV
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MOS, LDMOS, XDMOS Device Structures
HiSIM HV LDMOS – UTMOST IV
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MOS, LDMOS, XDMOS ATLAS DC Curves
HiSIM HV LDMOS – UTMOST IV
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MOS, LDMOS, XDMOS ATLAS Cgg Curves
HiSIM HV LDMOS – UTMOST IV
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MOS, LDMOS, XDMOS ATLAS Cgd Curves
HiSIM HV LDMOS – UTMOST IV
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LDMOS ATLAS Cgg and Cgd Curves
HiSIM HV LDMOS – UTMOST IV
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HiSIM HV SPICE Cgg and Cgd Curves
HiSIM HV LDMOS – UTMOST IV
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HiSIM HV Optimized DC Results
HiSIM HV LDMOS – UTMOST IV
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HiSIM HV SPICE Self-Heating Curves
HiSIM HV LDMOS – UTMOST IV
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LDMOS Device Structure Used to Obtain Simulation Data
for Parameter Extraction
HiSIM HV LDMOS – UTMOST IV
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Ids/Vgs TCAD-Simulated Data as Target
Ids/Vgs under several drain voltages such as the linear, quasi-saturation and
saturation regions enable easier parameter extraction
HiSIM HV LDMOS – UTMOST IV
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Ids/Vds TCAD-Simulated Data as Target
HiSIM HV LDMOS – UTMOST IV
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LDMOS Specific HiSIM HV Model Parameters
Schematic diagram of HiSIM HV
potential distribution
HiSIM HV LDMOS – UTMOST IV
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LDMOS Specific HiSIM HV Model Parameters
HiSIM HV LDMOS – UTMOST IV
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LDMOS Specific HiSIM HV Model Parameters
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
Left: initial right: optimized
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
Left: initial right: optimized
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
Left: initial right: optimized
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
HiSIM HV LDMOS – UTMOST IV
Left: initial right: optimized
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
HiSIM HV LDMOS – UTMOST IV
Left: initial right: optimized
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
Left: initial right: optimized
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
Left: initial right: optimized
HiSIM HV LDMOS – UTMOST IV
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UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
HiSIM HV LDMOS – UTMOST IV
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HiSIM LDMOS needs several
parameters for capacitance. Cgg is
required for tuning. Set parameter
XLDLD equal to LOVERLD if no Cgg
is available.
LOVERLD = 3 um for a left figure
while the upper left shows the
default.

UTMOST IV HiSIM HV Parameter Extraction (CORSRD=3)
HiSIM HV LDMOS – UTMOST IV
64 bit Intel Core2 Duo(Centrino) took about
35 minutes to optimize this example
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Summary
HiSIM HV accurately models HV and LDMOS in quasi-saturation,
thermal behavior, and capacitance
UTMOST IV genetic optimizer can quickly and accurately extract all
HiSIM HV parameters to create a single scalable model set
HiSIM HV Model performance reports from various companies, posted
on the Compact Modeling Council (CMC ) website, can be accessed via
http://www.silvaco.com/cmc
HiSIM HV LDMOS – UTMOST IV
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