CMSC 611: Advanced Computer Architecture

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Block # 0 1 2 3 4 5 6 7 Data Tag Search Direct mapped 1 2 Block Placement Set # 0 1 2 3 Data Tag Search Set associative 1 2 Data Tag Search Hardware Complexity Cache utilization Fully associative • Set number = (Block number) modulo (Number of sets in the cache) • Increased flexibility of block placement reduces probability of cache misses 1 2
31 X X X Fully Associative Cache • Forget about the Cache Index • Compare the Cache Tags of all cache entries in parallel • Example: Block Size = 32 Byte blocks, we need N 27-bit comparators • By definition: Conflict Miss = 0 for a fully associative cache X X Cache Tag Cache Tag (27 bits long) : Valid Bit : 4 Cache Data Byte 31 : Byte 63 : Byte Select Ex: 0x01 Byte 1 Byte 33 : 0 Byte 0 Byte 32 Slide: Dave Patterson
Page 1 and 2: CMSC 611: Advanced Computer Archite
Page 3 and 4: Performance 1000 100 10 1 Processor
Page 5 and 6: To Processor From Processor Memory
Page 7 and 8: Requesting X n generates a miss and
Page 9 and 10: # cache blocks Tag Accessing Cache
Page 11: Miss Penalty Determining Block Size
Page 15 and 16: Index Tag size increases with highe
Page 17 and 18: Write Through via Buffering Process
Page 19 and 20: Measuring Cache Performance • To
Page 21: Multi-level Cache Performance Suppo

CMSC 611: Advanced Computer Architecture

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