Using a Micrel Ethernet PHY and a Lattice ECP3 FPGA to Create an ...

Using a Micrel Ethernet PHY and a Lattice ECP3 FPGA to Create an Ethernet 

Subsystem: A Step by Step Guide 

APPLICATION NOTE 

Introduction 

Many modern applications use FPGAs to implement complex system level 

building blocks. These building blocks can contain processors, DSPs, bus 

interface and even video and audio functions. Getting high-speed data 

on and off the FPGA can be accomplished by using a standard Ethernet 

interface and this leverages a wide range of established protocols, software 

platforms and IP. FPGA’s usually requires an Ethernet Interface IP Core inside 

the FPGA and some external devices, typically an Ethernet Physical (PHY) 

layer device and a connector. 

Creating an Ethernet subsystem involves a variety of design considerations. 

This application note provides a step-by-step guide for a designer who 

needs to quickly and efficiently create an Ethernet subsystem using a Lattice 

ECP3 FPGA, and a Micrel Ethernet PHY. 

Topics in this application note are organized by design task (Device 

Selection, FPGA Design, and Board Design) and each topic is a stand-alone 

section, with a short introduction or overview, followed by the step-by-step 

design guidelines. The reader may skip over sections and go directly to the 

topic of interest, or start at the beginning and follow each topic in order 

to quickly go through the entire design process, step-by-step. The topics 

covered in this application note include the following: 

1) Device Selection 

a. Micrel Ethernet PHY 

i. Ethernet PHY Functional Overview 

ii. Pin Descriptions 

iii. MII Connectivity 

b. Midcom PMD and Connector 

i. Functional Overview 

ii. Connectivity to Ethernet PHY 

iii. Available Devices 

c. Lattice ECP3 FPGAs 

i. ECP3 Functional Overview 

ii. Family Overview 

iii. Device Selection 

2) FPGA Design 

a. Using the Lattice Ethernet IP Core 

i. IP Core Overview 

ii. Functional Description 

iii. Pin Descriptions 

iv. Example Design- Step-by-Step 

b. Integration of the IP Core 

i. Integration Overview 

ii. Functional Description 

iii. Pin Descriptions 

AN094 October 7, 2010 (Version 1.0) 


3) Board Design Considerations 

a. Pin Assignment Considerations 

b. Simultaneous Switching Output Considerations 

c. Power Supply and Decoupling Considerations 

d. Board Layout and Signal Routing Considerations 

A significant amount of supporting documentation is referenced in this 

application note and the reference section at the end of this application note 

provides links to on-line versions of each reference, making it easy to locate 

additional information. 

Device Selection 

The first phase of the design project is device selection, where the designer 

decides on the key components to be used in the design. As a target 

application example we will use a video inspection system used in an 

assembly line application. This type of embedded video processor needs to 

fit into a very small form factor and will monitor and control inspection of 

product produced by an assembly. Ethernet is being used to communicate to 

the controller so that commands and data received by the controller can be 

relayed to the central processing location. A large number of controllers will 

be distributed throughout the factory at various stages of the manufacturing 

process. Because of the data transmission speed required high-speed 

Ethernet is needed, but backwards compatibility to standard Ethernet is an 

advantage. Significant DSP functionality is desired so that video images 

may be processed quickly and any product quality issues spotted quickly. 

Let’s assume that an initial review of possible suppliers has been conducted 

and that Micrel has been selected as the supplier for the Ethernet PHY and 

Lattice has been selected as the FPGA supplier. 

An FPGA was selected for the flexibility, small form factor and the ability to 

provide a variety of I/O options required by the equipment. The Lattice ECP3 

Family was selected because of its low cost, low power, high speed SERDES, 

DSP functionality and the availability of a robust Tri-Mode Ethernet MAC. 

The Micrel Ethernet PHY was selected because of its small footprint, flexible 

interface, power management capability and advanced features. 

In this section of the application note we will review the Micrel Ethernet PHY, 

and the Lattice ECP3 Family. This combination of devices is excellent for a 

wide range of applications in the consumer, industrial, communications and 

networking industries- and in particular for our target application where low 

power, a small form factor, DSP processing power and future extendibility are 

important. The following sections provide a quick overview of each device 

family, identifies key features that make them good selections for our target 

application and determines the best device within the family for our specific 

application.

Using a Micrel Ethernet PHY and a Lattice ECP3 FPGA to Create an Ethernet Subsystem: A Step-By-Step Guide 

Micrel Ethernet Devices 

Micrel offers a wide range of Ethernet physical layer devices. All Micrel devices come with options for various voltages, Lead Free, Industrial or with HP Auto- 

MDIX crossover features. A summary list of the main Micrel PHY devices is given in Table 1 below. Depending on the feature options selected the part number 

is modified. For example, an “I” designator on the end of the part number indicates an Industrial temperature rating. A selector guide with all the specific part 

numbers is available at http://www.micrel.com/_PDF/Ethernet/ethernet.pdf. 


Product Voltages Lead Free Industrial LinkMD 

KSZ8021 3.3V Yes Yes Yes 


KSZ8041 3.3V Yes Yes Yes or No 


KSZ8721 2.5V/3.3V Yes Yes Yes or No 

Table 1: Micrel Ethernet Controller Products Summary 

Micrel KSZ8051NL Overview 

With the core at 1.2 volts to meet low voltage and low-power requirements, the KSZ8051MLL is a 10BASE-T/100BASE-TX Physical Layer Transceiver with 

Media Independent Interface (MII) to transmit and receive data. A unique mixed signal design extends signaling distance while reducing power consumption. The 

KSZ8051MLL is a highly-integrated, compact solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential 

pairs and by integrating a low-noise regulator to supply the 1.2V core. 

The KSZ8051MLL provides diagnostic features to facilitate system bring-up and debugging in production testing and in product development. Parametric NAND 

tree support enables fault detection between KSZ8051MLL I/Os and the board. Micrel LINKMD TDR-based cable diagnostics permit identification of faulty copper 

cabling. Remote and local loopback functions provide verification of analog and digital data paths. 

The signal list for the KSZ8051MLL is shown in Table 2 below. The interface to the MAC can use the MII standard. 

Name Type Description 

TXD0 I Transmit Data 0: Bit 0 of the 4 data bits that are accepted by the PHY for transmission. 




TXEN I Transmit Enable Input: Indicates that valid data is presented on the TXD[3:0] signals, for transmission. 

TXC O Transmit Clock Output: 25MHz in 100Base-TX mode, 2.5MHz in 10Base-T mode. 

RXD3/ PHYAD0 I/O Receive Data 3: Bit 3 of the 4 data bits that are sent by the PHY in the receiver path. 

PHY ADDR[0]: sets PHYADDR[0] during initialization. 





RXD0/ DUPLEX I/O Receive Data 0: Bit 0 of the 4 data bits that are sent by the PHY in the receiver path. 

DUPLEX: sets DUPLEX during initialization. 

RXER/ ISO O Receive Error: Asserted to indicate that an error was detected somewhere in the frame presently being transferred from the PHY. 

ISO: Sets ISO during initialization. 

RX_DV/ CONFIG2 O Receive Data Valid Output: Indicates that recovered and decoded data nibbles are being presented on RXD[3:0]. 

CONFIG2: sets CONFIG2 during initialization. 

RXC/B-CAST_OFF O Receive Clock Output: 25MHz in 100Base-TX mode. 2.5MHz in 10Base-T mode. 

CONFIG Mode: B-CAST_OFF set during initialization. 

COL/CONFIG0 O Collision Detect: Asserted to indicate detection of collision condition. 

CONFIG MODE: CONFIG0 set during initialization. 

MDIO I/O Management Data Input/Output: Serial management data input/output. External 1K Ohm pull-up. 

MDC I Management Clock: Serial management clock.


Name Type Description 

CRS/CONFIG1 O Carrier Sense Output. Indicates presence of Carrier on the media. 

CONFIG MODE: CONFIG1 set during initialization 

INTRP/ NAND_Tree# I/O Interrupt Output: Programmable interrupt indication. 

CONFIG MODE: NAND_Tree# set during initialization. 

RST# I External Reset- input of the system reset. 

XI I/O Clock Input- 25MHz external clock or crystal input. 

XO O Crystal Feedback. 

LED0/NWAYEN O Programmable LED Output 

CONFIG MODE: NWAYEN set during initialization 

LED1/SPEED O Programmable LED Output 

CONFIG MODE: SPEED set during initialization 

TXP AO Transmit Data Positive: 100Base-TX or 10Base-T differential transmit outputs to magnetic. 

TXM AO Transmit Data Negative: 100Base-TX or 10Base-T differential transmit outputs to magnetic. 

RXP AI Receive Data Positive: 100Base-TX or 10Base-T differential transmit inputs from magnetic. 

RXM AI Receive Data Negative: 100Base-TX or 10Base-T differential transmit inputs from magnetic. 

REXT IO Connects to reference resistor of value 6.49K-Ohm to ground 

VDD_1.2 POWER 1.2V Core Voltage supplied by on-chip regulator 

VDDIO POWER +3.3V, 2.5V or 1.8V Digital IO Voltage 

VDDA3.3 POWER +3.3V Analog Power 

GND POWER Ground 

Table 2: Micrel KSZ8051MLL Pin Descriptions 

KSZ8051MLL Functional Description 

The KSZ8051MLL is an integrated single 3.3V supply Fast Ethernet 

transceiver. It is fully compliant with the IEEE 802.3 Specification, and 

reduces board cost and simplifies board layout by using on-chip termination 

resistors for the two differential pairs and by integrating the regulator to 

supply the 1.2V core. On the copper media side, the KSZ8051MLL supports 

10Base-T and 100Base-TX for transmission and reception of data over a 

standard CAT-5 unshielded twisted pair (UTP) cable, and HP auto MDI/MDI-X 

for reliable detection of and correction for straight-through and crossover 

cables. On the MAC processor side, the KSZ8051MLL offers the Media 

Independent Interface (MII) for direct connection with MII compliant Ethernet 

MAC processors and switches. The MII management bus option gives the 

MAC processor complete access to the KSZ8051MLL control and status 

registers. Additionally, an interrupt pin eliminates the need for the processor 

to poll for PHY status change. 

100Base-TX Transmit 

The 100Base-TX transmit function performs parallel-to-serial conversion, 

4B/5B encoding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding 

and transmission. The circuitry starts with a parallel-to-serial conversion, 


which converts the MII data from the MAC into a 125MHz serial bit stream. 

The data and control stream is then converted into 4B/5B coding and 

followed by a scrambler. The serialized data is further converted from NRZto-NRZI 

format, and then transmitted in MLT3 current output. The output 

current is set by an external 6.49K Ohm 1% resistor for the 1:1 transformer 

ratio. The output signal has a typical rise/fall time of 4ns and complies with 

the ANSI TP-PMD standard regarding amplitude balance, overshoot, and 

timing jitter. The wave-shaped 10Base-T output is also incorporated into the 

100Base-TX transmitter. 

100Base-TX Receive 

The 100Base-TX receiver function performs adaptive equalization, DC 

restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to- 

NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel 

conversion. The receiving side starts with the equalization filter to 

compensate for inter-symbol interference (ISI) over the twisted pair cable. 

Since the amplitude loss and phase distortion is a function of the cable 

length, the equalizer must adjust its characteristics to optimize performance. 

In this design, the variable equalizer makes an initial estimation based 

on comparisons of incoming signal strength against some known


cable characteristics, and then tunes itself for optimization. This is an 

ongoing process and self-adjusts against environmental changes such 

as temperature variations. Next, the equalized signal goes through a DC 

restoration and data conversion block. The DC restoration circuit is used to 

compensate for the effect of baseline wander and to improve the dynamic 

range. The differential data conversion circuit converts the MLT3 format back 

to NRZI. The slicing threshold is also adaptive. The clock recovery circuit 

extracts the 125MHz clock from the edges of the NRZI signal. This recovered 

clock is then used to convert the NRZI signal into the NRZ format. This signal 

is sent through the de-scrambler followed by the 4B/5B decoder. Finally, the 

NRZ serial data is converted to the MII format and provided as the input data 

to the MAC. 

10Base-T Transmit 

The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow 

for transmission using the same magnetic. The drivers perform internal 

wave-shaping and pre-emphasis, and output 10Base-T signals with typical 

amplitude of 2.5V peak. The 10Base-T signals have harmonic contents that 

are at least 27dB below the fundamental frequency when driven by an allones 

Manchester-encoded signal. 

10Base-T Receive 

On the receive side, input buffer and level detecting squelch circuits are 

employed. A differential input receiver circuit and a PLL performs the 

decoding function. The Manchester-encoded data stream is separated into 

clock signal and NRZ data. A squelch circuit rejects signals with levels less 

than 400 mV or with short pulse widths to prevent noise at the RXP and RXM 

inputs from falsely trigger the decoder. When the input exceeds the squelch 

limit, the PLL locks onto the incoming signal and the KSZ8051MLL decodes 

a data frame. The receive clock is kept active during idle periods in between 

data reception. 

Scrambler/De-Scrambler (100Base-TX Only) 

The scrambler is used to spread the power spectrum of the transmitted 

signal to reduce EMI and baseline wander, and the de-scrambler is needed 

to recover the scrambled signal. SQE and Jabber Function (10Base-T Only) 

In 10Base-T operation, a short pulse is put out on the COL pin after each 

frame is transmitted. This SQE Test is required as a test of the 10Base-T 

transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms 

(jabbering), the 10Base-T transmitter is disabled and COL is asserted high. If 

TXEN is then driven low for more than 250 ms, the 10Base-T transmitter is 

re-enabled and COL is de-asserted (returns to low). 

PLL Clock Synthesizer 

The KSZ8051MLL generates all internal clocks and all external clocks for 

system timing from an external 25MHz crystal, oscillator, or reference clock. 

Auto-Negotiation 

The KSZ8051MLL conforms to the auto-negotiation protocol, defined in 

Clause 28 of the IEEE 802.3 Specification. Auto-negotiation allows UTP 

(Unshielded Twisted Pair) link partners to select the highest common mode 

of operation. During auto-negotiation, link partners advertise capabilities 

across the UTP link to each other, and then compare their own capabilities 


with those they received from their link partners. The highest speed and 

duplex setting that is common to the two link partners is selected as the 

mode of operation. 

MII Data Interface 

The Media Independent Interface (MII) is compliant with the IEEE 802.3 

Specification. It provides a common interface between MII PHYs and MACs, 

and has the following key characteristics: 

• Pin count is 15 pins (6 pins for data transmission, 7 pins for data 

reception, and 2 pins for carrier and collision indication). 

• 10Mbps and 100Mbps data rates are supported at both half and full 

duplex. 

• Data transmission and reception are independent and belong to separate 

signal groups. 

• Transmit data and receive data are each 4-bit wide, a nibble. 

By default, the KSZ8051MLL is configured to MII mode after it is powered up 

or hardware reset with the following: 

• A 25MHz crystal connected to XI, XO (pins 15, 14), or an external 25MHz 

clock source (oscillator) connected to XI. 

• The CONFIG[2:0] strapping pins (pins 27, 41, 40) set to ‘000’ (default 

setting). 

MII Signal Definition 

Transmit Clock (TXC) 

TXC is sourced by the PHY. It is a continuous clock that provides the timing 

reference for TXEN and TXD[3:0]. TXC is 2.5MHz for 10Mbps operation and 

25MHz for 100Mbps operation. 

Transmit Enable (TXEN) 

TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It 

is asserted synchronously with the first nibble of the preamble and remains 

asserted while all nibbles to be transmitted are presented on the MII, and 

is negated prior to the first TXC following the final nibble of a frame. TXEN 

transitions synchronously with respect to TXC. 

Transmit Data [3:0] (TXD[3:0]) 

TXD[3:0] transitions synchronously with respect to TXC. When TXEN is 

asserted, TXD[3:0] are accepted for transmission by the PHY. TXD[3:0] is 

”00” to indicate idle when TXEN is de-asserted. Values other than “00” on 

TXD[3:0] while TXEN is de-asserted are ignored by the PHY. 

Receive Clock (RXC) 

RXC provides the timing reference for RXDV, RXD[3:0], and RXER. In 10Mbps 

mode, RXC is recovered from the line while carrier is active. RXC is derived 

from the PHY’s reference clock when the line is idle, or link is down. In 

100Mbps mode, RXC is continuously recovered from the line. If link is down, 

RXC is derived from the PHY’s reference clock. RXC is 2.5MHz for 10Mbps 

operation and 25MHz for 100Mbps operation. 

Receive Data Valid (RXDV) RXDV is driven by the PHY to indicate that the 

PHY is presenting recovered and decoded nibbles on RXD[3:0]. In 10Mbps


mode, RXDV is asserted with the first nibble of the SFD (Start of Frame 

Delimiter), “5D”, and remains asserted until the end of the frame. In 

100Mbps mode, RXDV is asserted from the first nibble of the preamble to the 

last nibble of the frame. RXDV transitions synchronously with respect to RXC. 

Receive Data[3:0] (RXD[3:0]) 

RXD[3:0] transitions synchronously with respect to RXC. For each clock 

period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered 

data from the PHY. 

Receive Error (RXER) 

RXER is asserted for one or more RXC periods to indicate that a Symbol 

Error (e.g. a coding error that a PHY is capable of detecting, and that may 

otherwise be undetectable by the MAC sub-layer) was detected somewhere 

in the frame presently being transferred from the PHY. RXER transitions 

synchronously with respect to RXC. While RXDV is de-asserted, RXER has no 

effect on the MAC. 

Carrier Sense (CRS) 

CRS is asserted and de-asserted as follows: In 10Mbps mode, CRS assertion 

is based on the reception of valid preambles. CRS de-assertion is based on 

the reception of an end-of-frame (EOF) marker. In 100Mbps mode, CRS is 

asserted when a start-of-stream delimiter, or /J/K symbol pair is detected. 

CRS is de-asserted when an end-of-stream delimiter, or /T/R symbol pair 

is detected. Additionally, the PMA layer de-asserts CRS if IDLE symbols are 

received without /T/R. 

Collision (COL) 

COL is asserted in half-duplex mode whenever the transmitter and receiver 

are simultaneously active on the line. This is used to inform the MAC that 

a collision has occurred during its transmission to the PHY. COL transitions 

asynchronously with respect to TXC and RXC. 

Power Management 

The KSZ8051MLL offers the following power management modes: 

Power Saving Mode: Power-Saving Mode is used to reduce the transceiver 

power consumption when the cable is unplugged. It is enabled by writing a 

one to register 1Fh, bit 10, and is in effect when auto-negotiation mode is 

enabled and cable is disconnected (no link). In this mode, the KSZ8051MLL 


Figure 1: Interconnection between Lattice FPGA and Micrel Ethernet PHY 

shuts down all transceiver blocks, except for transmitter, energy detect and 

PLL circuits. By default, Power-Saving Mode is disabled after power-up. 

Energy Detect Power-Down Mode: Energy Detect Power-Down Mode is used 

to further reduce the transceiver power consumption when the cable is unplugged. 

It is enabled by writing a zero to register 18h, bit 11, and is in effect 

when auto-negotiation mode is enabled and cable is disconnected (no link). 

In this mode, the KSZ8051MLL shuts down all transceiver blocks, except 

for transmitter and energy detect circuits. Further power consumption is 

achieved by extending the time interval in between transmissions of link 

pulses to check for the presence of a link partner. The periodic transmission 

of link pulses is needed to ensure two link partners in the same low power 

state and with auto MDI/MDI-X disabled can wake up when the cable is 

connected between them. By default, Energy Detect Power-Down Mode is 

disabled after power-up. 

Power-Down Mode: Power-Down Mode is used to power down the 

KSZ8051MLL device when it is not in use after power-up. It is enabled 

by writing a one to register 0h, bit 11. In this mode, the KSZ8051MLL 

disables all internal functions, except for the MII management interface. The 

KSZ8051MLL exits (disables) Power-Down Mode after register 0h, bit 11 is 

set back to zero. 

Slow Oscillator Mode: Slow Oscillator Mode is used to disconnect the input 

reference crystal/clock on XI (pin 15) and select the on-chip slow oscillator 

when the KSZ8051MLL device is not in use after power-up. It is enabled 

by writing a one to register 11h, bit 5. Slow Oscillator Mode works in 

conjunction with Power-Down Mode to put the KSZ8051MLL device in the 

lowest power state with all internal functions disabled, except for the MII 

management interface. 

KSZ8051MLL to FPGA Connectivity 

The Media Independent Interface (MII) is used to connect between the 

FPGA and the PHY. The MII standard requires 16 pins for each MAC to PHY 

interface. A block diagram of the MII connectivity between the KSZ8051MLL 

and the Lattice ECP3 FPGA is shown in Figure 1 below. The signal 

assignments and constraints required for the FPGA will be discussed in more 

detail in the FPGA Design section of this document. Important board level 

considerations like grounding, layout and routing constraints will be covered 

in the Board Design section of this document.


Midcom MIC24 Series of RJ-45 Connectors with Integrated Magnetics 

Midcom offers a family of devices with the Ethernet line isolation magnetics 

combined in the required RJ45 cable jack. This combined single device helps 

to reduce board space, improves signal integrity, increases reliability and 

also simplifies board layout. The wide range of available devices provides a 

perfect match for just about any application: routers and switches benefit 

from the high density provided by stackable configurations with integrated 

status LEDs, consumer applications can use an option without an LED when 

status isn’t required, different pin-out options, optional EMI tabs help in noise 

sensitive applications, and support for both tab up and tab down orientation 

simplifies the mechanical aspects of the cable interface. 

These devices come compliant to Ethernet 10, 10/100 or gigabit standards 

and are available in single port and multi-port form factors as well as in thru 

hole or surface mount formats. Power Over Ethernet (PoE) is also available 

for the 10/100 standard. For our application we will focus on the single port, 

Ethernet 10/100 standard in the thru hole format. This still provides us with 

a very wide range of options to select from. A subset of all the available 

devices is shown in Table 3 below to illustrate the wide range of options 

available to us. (Additional differences between some devices are pin-out 

related and are not illustrated in this table for simplicity. You can refer to the 

Midcom product selector guide listed in the reference section of this app 

note for additional details.) 

Part Number LED Tabs 


EMI 

Fingers 

Auto 

MDIX 

Temp RoHS 

MIC24010-0107T NONE DOWN YES YES ETR NO 

MIC24010-0107T-LF3 NONE DOWN YES YES ETR YES 

MIC24010-5101T-LF3 NONE DOWN YES YES STR YES 

MIC24010-5104T-LF3 NONE DOWN YES YES STR YES 

MIC24011-0101T L-Y R-G DOWN YES STR STR NO 

MIC24011-0101T-LF3 L-Y R-G DOWN YES YES STR YES 

MIC24011-0101W-LF3 L-Y R-G DOWN YES YES STR YES 

MIC24011-0104T L-Y R-G DOWN YES STR STR NO 

MIC24011-0104T-LF3 L-Y R-G DOWN YES YES STR YES 

MIC24011-5108T-LF3 L-Y R-G DOWN YES YES ETR YES 

MIC24012-5101T-LF3 L-G R-G DOWN YES YES STR YES 

MIC24012-5117T-LF3 L-G R-G DOWN YES YES ETR YES 

MIC24012-5204T-LF3 L-G R-G DOWN YES YES STR YES 

MIC24013-0102T L-G R-Y DOWN YES STR STR NO 

MIC24013-5104T-LF3 L-G R-Y DOWN YES YES STR YES 

MIC24013-5204T-LF3 L-G R-Y DOWN YES YES STR YES 

MIC24018-5101T-LF3 L-R R-G DOWN YES YES STR YES 

MIC24019-0101T L-G R-R DOWN YES STR NO NO 

MIC2401D-5217T-LF3 L-GY R-GY DOWN YES YES ETR YES 

Table 3: Selected Midcom RJ45 Ethernet MIC24 Series Devices 

Device Selection 

In our application status indication is important as is keeping board space 

small. Noise is also a consideration and should be reduced where possible. 

To simplify installation auto MDIX (the ability to sense and correct for cable 

‘twists’) is also desirable. 

For our application we will also want a device with an LED configuration 

of a yellow LED on the left and a green LED on the right (L-Y R-G). We also 

want RoHS compliance and the ability to use either an extended or standard 

temperature range. 

The Midcom MIC24011-0101T-LF3 is through hole mounted, has Yellow and 

Red LEDs, a tab down orientation, EMI flanges, Auto MDIX support, and is 

RoHS compliant. It is also compatible with both 10Base-T and 100Base-T 

Ethernet standards. 

MIC24011-0101T-LF3 Connectivity 

The connections between the Micrel PHY and the MIC24011-0101T-LF3 are 

the transmit and receive signals and the LED control signals. A summary of 

the detailed connections are given below with PHY being the Micrel PHY pin 

and PMD being the MIC24011-0101T-LF3 pin: 

1) PHY TXP to PMD T+ and thru a 50Ohm resistor to VCCO 

2) PHY TXN to PMD T- and thru a 50Ohm resistor to VCCO 

3) PMD T center tap thru a 10Ohm resistor to VCCO (Shared with PMD R) 

4) PHY RXP to PMD R+ and thru a 50Ohm resistor to VCCO 

5) PHY RXN to PMD R- and thru a 50Ohm resistor to VCCO 

6) PMD R center tap thru a 10Ohm resistor to VCCO (Shared with PMD T) 

7) PMD T and R center taps thru a 22NF capacitor to GND 

8) FPGA LED 1 thru a 330Ohm resistor to LED1+ on the PHD 

9) FPGA LED 2 thru a 330Ohm resistor to LED1+ on the PHD 

10) LED 1- and LED 2- on the PMD to GND 

Lattice ECP3 FPGAs 

The LatticeECP3 (EConomy Plus Third generation) family of FPGA devices 

is optimized to deliver high performance features such as an enhanced 

DSP architecture, high speed SERDES and high speed source synchronous 

interfaces in an economical FPGA fabric. This combination is achieved 

through advances in device architecture and the use of 65nm technology 

making the devices suitable for high-volume, high-speed, low-cost 

applications. The LatticeECP3 device family expands look-up-table (LUT) 

capacity to 149K logic elements and supports up to 486 user I/Os. The 

LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide 

range of parallel I/O standards. 

The LatticeECP3 FPGA fabric is optimized with high performance and low 

cost in mind. The LatticeECP3 devices utilize reconfigurable SRAM logic 

technology and provide popular building blocks such as LUT-based logic, 

distributed and embedded memory, Phase Locked Loops (PLLs), Delay 

Locked Loops (DLLs), pre-engineered source synchronous I/O support, 

enhanced sysDSP slices and advanced configuration support, including 

encryption and dual-boot capabilities. 

The pre-engineered source synchronous logic implemented in the 

LatticeECP3 device family supports a broad range of interface standards, 

including DDR3, XGMII and 7:1 LVDS. The LatticeECP3 device family also 

features high speed SERDES with dedicated PCS functions. High jitter 

tolerance and low transmit jitter allow the SERDES plus PCS blocks to 

be configured to support an array of popular data protocols including PCI 

Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-


emphasis and Receive Equalization settings make the SERDES suitable for 

transmission and reception over various forms of media. 

The LatticeECP3 devices also provide flexible, reliable and secure 

configuration options, such as dual-boot capability, bit-stream encryption, 

and TransFR field upgrade features. 

The Lattice Diamond Design Software allows large complex designs to be 

efficiently implemented using the LatticeECP3 FPGA family. Synthesis library 

support for LatticeECP3 is available for popular logic synthesis tools. The 

Lattice Diamond Design Software uses the synthesis tool output along with 

the constraints from its floor planning tools to place and route the design 

in the LatticeECP3 device. The Diamond Software tool extracts the timing 

from the routing and back-annotates it into the design for timing verification. 

Lattice provides many pre-engineered IP (Intellectual Property) modules for 

the LatticeECP3 family. By using these configurable IP cores as standardized 

Table 4: Lattice ECP3 Family Logic Function and IO Capabilities 

Device Selection Summary 

We have decided on the key components from which to construct our 

Ethernet subsystem. We chose the Micrel KSZ8051MLLL Ethernet PHY for 

its low cost, flexibility, advanced features, power saving capabilities and 

small footprint. We selected the Lattice ECP3-70 for low power, high speed 

SERDES, advanced DSP capabilities, abundant IO resources and low cost. We 

chose the Midcom RJ45 Ethernet connector for its high level of integration 

and excellent performance characteristics. 


blocks, designers are free to concentrate on the unique aspects of their 

design, increasing their productivity. 

Selecting the Lattice ECP3 Device 

The selection of the target ECP3 device depends on both the IO requirements 

and the logic requirements. For our target application let’s assume we 

need over 350 IOs and over 40K LUTs. Let’s also assume that our 18x18 

multiplier requirements are around 64, based on a quick review of the DSP 

oriented functions we need to implement. Table 4 below shows the range of 

capabilities of the Lattice ECP3 devices. The ECP3-70 device is the smallest 

that meets all of our key requirements. (During the design process we will 

have the option to design the interface in such a way that we can migrate to 

another device with the same package footprint, with a different amount of 

logic capacity. This can be useful if the design requirements might change 

late in the design process.) 

Now that we have selected our target devices we can begin the design of 

the FPGA portion of the subsystem. This involves configuring the Ethernet 

Controller that resides in the Lattice ECP3 FPGA. This process is described in 

detail in the next section of this document.


FPGA Design 

Once the key devices have been selected the FPGA stage of the design can 

be started. During this phase the designer will need to create an Ethernet 

interface subsystem, inside the FPGA, to control the external PHY. There 

are a few choices available from Lattice to implement this function in an 

ECP3 Family device. There is a 10Gb+ Ethernet MAC, 2.5Gb Ethernet MAC, 

HiGig Ethernet MAC, and Tri-Speed Ethernet MAC. The Tri-Speed Ethernet 

Controller IP Core supports Gigabit mode (1000Mbits/sec data rate) or the 

Fast Ethernet mode (10/100 Mbits/sec data rate). For our application, where 

backwards compatibility to the older protocols is important, the Tri-Speed IP 

Core is a good choice. A block diagram of which is shown in Figure 2, below. 

The Tri-Speed Ethernet MAC transmits and receives data between a host 

processor and an Ethernet network. The main function of the Ethernet MAC 

is to ensure that the Media Access rules specified in the 802.3 IEEE standard 

are met while transmitting a frame of data over Ethernet. On the receiving 

side, the Ethernet MAC extracts the different components of a frame and 

transfers them to higher applications through the FIFO interface. 

Figure2: Ethernet MAC IP Core Block Diagram 


The data received from the G/MII interface is first buffered until sufficient 

data is available to be processed by the Receive MAC (Rx MAC). The 

Preamble and the Start of Frame Delimiter (SFD) information are then 

extracted from the incoming frame to determine the start of a valid frame. 

The Receive MAC checks the address of the received packet and validates 

whether the frame can be received before transferring it into the FIFO. Only 

valid frames are transferred into the FIFO. This feature has the following two 

benefits: the systems need not re-calculate the Frame Check Sequence (FCS) 

again when the frame is being transmitted, and it also keeps the receive 

MAC relatively simple. The Tri-Speed MAC, however, always calculates CRC 

to check whether the frame was received error-free. 

On the transmit side, the Tx MAC is responsible for controlling access to the 

physical medium. The Tx MAC reads data from an external client Tx FIFO, 

formats this data into an Ethernet packet and passes it to the G/MII module. 

The Tx MAC reads data from the Tx Client FIFO when the client indicates a 

packet is available, and the Tx MAC is in its appropriate state. The Tx MAC 

pre-fixes the Preamble and the Start-of-Frame Delimiter information to 

the data and appends the Frame Check Sequence at the end of the data. 

In half-duplex operation, the Tx MAC stores the first 64 bytes of data from


the external FIFO in an internal buffer, to be used in re-transmitting data on 

collisions. The SGMII Easy Connect configuration option adds pins and logic 

for seamless connection to the Lattice’s Gigabit Ethernet PCS IP core. 

Using the Lattice Ethernet Controller IP Core 

The TSMAC IP core is available for download from the Lattice IP Server using 

the IPexpress tool. The IP files are automatically installed using ispUPDATE 

technology in any customer-specified directory. After the IP core has been 

installed, the IP core will be available in the IPexpress GUI dialog box shown 

in Figure 3. 

Figure 3: IPexpress GUI Dialog Box 

Once the IP Core is opened the user can configure the various core 

parameters. The user specifies the following: 

• Project Path – Path to the directory where the generated IP files will be 

located. 

• File Name – “username” designation given to the generated IP core and 

corresponding folders and files. 

• (Diamond) Module Output – Verilog or VHDL. 

• (ispLEVER) Design Entry Type – Verilog HDL or VHDL. 

• Device Family – Device family to which IP is to be targeted (e.g. 

LatticeSCM, Lattice ECP2M, LatticeECP3, etc.). Only families that support the 

particular IP core are listed. 

• Part Name – Specific targeted part within the selected device family. 

Note that if the IPexpress tool is called from within an existing project, 

Project Path, Module Output (Design Entry in ispLEVER), Device Family and 

Part Name default to the specified project parameters. Refer to the IPexpress 

tool online help for further information. 


The resources required for selected configurations of the core are shown in 

Figure 4, below. 

Figure 4: Resources Required for IP Core 

Once the Ethernet MAC has been successfully configured and integrated in 

to the users design it is time to move on to the Board Design portion of the 

project. The key Board Design considerations are given in the next section of 

this application note. 

Board Design 

During the board design portion of the Ethernet subsystem design process 

there are several key design considerations that need to be addressed. 

These considerations can be grouped as follows: Pin Assignment 

considerations, Power Supply/Decoupling Considerations and Board Layout/ 

Component Placement Considerations. 

FPGA Pin Assignment Considerations 

The during the configuration portion of the IP core design the Lattice 

software can use pin assignments supplied by the user, making it easy to 

simplify the board layout process. If board layout isn’t a concern the pin 

assignment can be left up to the Lattice software and the assignment will 

be made based on the design requirements of the logic and interconnect 

inside the FPGA. It is a fairly simple process to make pin assignments for 

the important MII signals between the FPGA and the Micrel PHY. Simply 

select pins of the side of the FPGA that is closest to the Micrel PHY device as 

determined by your board layout. 

Power Supply/Decoupling Capacitor Considerations 

Power supply design and the selection of decoupling components can be 

of critical importance to any subsystem with a combination of analog and 

digital functions like Ethernet. The key considerations can be grouped into 

these categories: Power Supply, PCB Decoupling Capacitors, PCB Bypass 

Capacitors and PCB Bulk Capacitors. 

Power Supply 

• Ensure adequate power supply ratings. Verify that all power supplies and 

voltage regulators can supply the amount of current required. 

• Power supply output ripple should be limited to less than 50 mV. 

• Noise levels on all power planes and ground planes should be limited to 

less than 50 mV. 

• Ferrite beads should be rated for 4 – 6 times the amount of current they 

are expected to supply. Any de-rating over temperature should also be 

accounted for.


PCB Decoupling Capacitors 

• Every high-speed semiconductor device on the PCB assembly requires 

decoupling capacitors. One decoupling cap for every power pin is 

necessary. 

• Decoupling capacitor value is application dependent. Typical decoupling 

capacitor values may range from 0.1 μF to 0.001 μF. 

• The total decoupling capacitance should be greater than the load 

capacitance presented to the digital output buffers. 

• Typically, Class II dielectric capacitors are chosen for decoupling 

purposes. The first choice would be an X7R dielectric ceramic 

capacitor for its excellent stability and good package size vs. capacitance 

characteristics. Low inductance is of the utmost importance when 

considering decoupling capacitor characteristics. 

• Each decoupling capacitor should be located as close as possible to the 

power pin that it is decoupling. 

• All decoupling capacitor leads should be as short as possible. The best 

solutions are plane connection vias inside the surface mount pads. When 

using vias outside the surface mount pads, pad-to-via connections should 

be less than 5 – 10 mils in length. 

• Trace connections should be as wide as possible to lower inductance. 

PCB Bypass Capacitors 

• Bypass capacitors should be placed near all power entry points on the 

PCB. These caps will allow unwanted high-frequency noise from entering 

the design; the noise will simply be shunted to ground. 

• Bypass capacitors should be utilized on all power supply connections and 

all voltage regulators in the design. 

• Bypass capacitor values are application dependent and will be dictated by 

the frequencies present in the power supplies. 


• All bypass capacitor leads should be as short as possible. The best 

solutions are plane connection vias inside the surface mount pads. When 

using vias outside the surface mount pads, pad-to-via connections should 

be less than 5 – 10 mils in length. Trace connections should be as wide as 

possible to lower inductance. 

PCB Bilk Capacitors 

• Bulk capacitors must be properly utilized in order to minimize switching 

noise. Bulk capacitance helps maintain constant DC voltage and current 

levels. 

• Bulk capacitors should be utilized on all power planes and all voltage 

regulators in the design. 

• All bulk capacitor leads should be as short as possible. The best solutions 

are plane connection vias inside the surface mount pads. When using vias 

outside the surface mount pads, pad-to-via connections should be less 

than 5 – 10 mils in length. Trace connections should be as wide as 

possible to lower inductance. 

• Whenever a ferrite bead is implemented, bulk capacitance must be used 

on each side of the ferrite bead. 

Board Layout and Component Placement Considerations 

Proper board layout and component placement considerations are important 

to any high-speed mixed analog/digital design. The requirements for the 

layout of the signals connecting the Lattice FPGA and the Micrel PHY are 

shown in Figure 5 below. These requirements are used to drive the layout 

of specific signals and must be checked against actual board signal routing 

results. 

Notes: 

1. Provide solid ground reference 

2. Match transmit data with respect to transmit clock and receive data with respect to receive clock with in 100 mils 

3. A single ground plane is recommended. Do not split ground plane into separate planes for analog, digital and power pins. 

4. Route high speed signals above a continuous unbroken ground plane. 

5. Route differential pair on the same PCB layer 

Figure 5: Layout Recommendations for Ethernet PHY to Lattice ECP3 Connections


Micrel has published an excellent application note on General PCB Design 

and Layout Guidelines, listed in the reference section of this document. 

These guidelines can be used to drive the PCB layout strategy. 

PCB Layer Strategy 

The following PCB layer guidelines when used as part of a comprehensive 

PCB layout strategy will help insure that high-speed signal integrity is 

preserved. These are not the only guidelines that should be used, since 

other considerations (cost, time to market, fabrication capabilities, etc) could 

dominate in any specific application. These are good examples however 

of general guidelines which could be a starting point for a comprehensive 

strategy. 

General Rules 

• Place components so as to avoid long loop traces. 

• Choose a metal box to shield the printed circuit board. 

• Use a ferrite core on the DC power cord to reduce EMI. 

• Follow the guidelines to layout differential pairs, the ground plane, and 

high-speed signals. 

• Provide controlled impedance on all clock lines and high-speed digital 

signals traces with right termination schemes to prevent reflection and 

ringing. 

• Ensure that the power supply is rated for the application and optimized 

with decoupling capacitors. 

• Keep power and ground noise under 50mV peakto-peak. 

• Ensure that the switching DC-DC converter is filtered and properly 

shielded as the DC-DC power converter can produce a great deal of EMI 

noise. 

• Avoid via and pad in the path on any critical signal as via and pad will 

induce unwanted capacitance and inductance which can cause reflection 

and distortion. 

Power Ground Rules 

• Do not split the ground plane into separate planes for analog, digital, 

power pins. A single and contiguous ground plane is recommended. 

• Route high-speed signals above a solid and unbroken ground plane. 

• Fill copper in the unused area of signal planes and connect these coppers 

to the ground plane through vias. 

• Stagger the placement of vias to avoid creating long gap in the plane due 

to via voids. 

Figure 6: MDI Signal Layout Requirements 


Analog VCC Plane 

• Place and route analog components within the Analog VCC plane. 

Digital VCC plane 

• Place and route digital components within the Digital VCC plane. 

Signal Ground 

• The signal ground region should be one continuous and unbroken plane. 

• Both analog (AGND) and digital (DGND) grounds should be directly 

connected to the signal ground plane. 

Chassis Ground 

The chassis ground and magnetics serve two purposes: they help to reduce 

EMI noise emissions from the signal ground plane to the PCB’s external 

environment and also act as a shield to protect the PCB components from 

ESD. 

• Place the chassis ground on all PCB layers and use connection mounting 

holes to join the chassis ground on different PCB layers. 

• If the chassis ground on the PCB is directly connected to the metal shield 

of equipment through the connection mounting holes, use a trench/moat 

to isolate the chassis ground plane from the signal ground plane. 

• The chassis ground region should extend from the front edge of the PCB 

board (RJ45 connectors) to the magnetics and around the edge of the 

board. 

Magnetic Noise Zone 

• Void both power and ground planes on all PCB layers directly under the 

magnetics. 

• Chassis ground should extend from the magnetics to the RJ45 connector. 

• Do not route any digital signals between the PHY and RJ45 connector. 

Differential Signal Layout 

• Differential pair (TX+/- or RX+/-) should be routed away from all other 

signals and close together to use 5-mil trace width and 5-mil trace space 

in same length as possible with 100 ohms controlled trace. 

• Keep both traces of each differential pair as identical to each other as 

possible. 

• Route each differential pair on the same PCB layer. 

• Route both TX+/- and RX+/- pairs as far as away from each other at least 

four times of 5-mil trace space as shown in Figure 6.


Additional PCB and layout guidelines are given in the Micrel application note. Refer to that note for additional suggestions that include PCB stacking, clock layout 

and ESD protection. 

Micrel has published a detailed Design Kit for the KSZ8051MLL that includes a board design with schematic and IBIS models. The location for this kit is given in 

the Reference section of this application note. 

Conclusion 

This application note has provided a step-by-step guide to designing an Ethernet subsystem using Lattice ECP3 FPGAs, and a Micrel Ethernet PHY. The reader 

should be able to more easily implement these types of interfaces and better understand the major design considerations and concerns present in these types of 

designs. It is hoped that the reader can also extending the concepts presented in this app note to other Lattice FPGAs and Micrel PHY devices and simplify those 

designs as well. 

For the reader who wants additional levels of detail on the Lattice, and Micrel products used in this app note a list of valuable documents is given in the Reference 

section at the end of this document. 

References 

1) Lattice ECP3 Data sheet 

http://www.latticesemi.com/products/fpga/ecp3/index.cfm 

2) Lattice Tri-Speed Ethernet MAC Data Sheet 

http://www.latticesemi.com/products/intellectualproperty/ipcores/trispeedethernetmediaacce/index.cfm 

3) Micrel Ethernet PHY Data Sheet (April 2007, Rev 1.1) 

http://www.micrel.com/page.do?page=product-info/fastether_trans.jsp 

4) Micrel General PCB Design and Layout Guidelines (AN-111, Feb 2007) 

http://www.micrel.com/_PDF/Ethernet/app-notes/an-111.pdf 

5) Micrel Design Kit for KSZ8051MLL 

http://www.micrel.com/page.do?page=product-info/fastether_trans.jsp 

6) Midcom RJ 45 Selector guide 

http://www.midcom-inc.com/Products/Lan/R_1X1_100_MIC24_TH.asp 

Notice Of Disclaimer 

Nu Horizons is disclosing this Application Note to you “AS-IS” with no warranty of any kind. This Application Note is one possible implementation of this feature, 

application, or standard, and is subject to change without further notice from Nu Horizons. You are responsible for obtaining any rights you may require in 

connection with your use or implementation of this Application Note. NU HORIZONS MAKES NO REPRESENTATIONS OR WARRANTIES, WHETHER EXPRESS 

OR IMPLIED, STATUTORY OR OTHERWISE, INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, OR FITNESS 

FOR A PARTICULAR PURPOSE. IN NO EVENT WILL NU HORIZONS BE LIABLE FOR ANY LOSS OF DATA, LOST PROFITS, OR FOR ANY SPECIAL, INCIDENTAL, 

CONSEQUENTIAL, OR INDIRECT DAMAGES ARISING FROM YOUR USE OF THIS APPLICATION NOTE. 

AN094 October 7, 2010 (Version 1.0)

Using a Micrel Ethernet PHY and a Lattice ECP3 FPGA to Create an ...

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