Operation and Design of Multilevel Inverters Dr ... - MotorLab.com

a two-level inverter. The line-to-neutral voltage v an and line-to-line voltage v ab
result from the line-to-ground voltage as described above yielding three levels in
v ab and five levels in v an . The filter is sized so that the load voltage has a total
harmonic distortion (THD) of 2.5%. As a result, the phase voltage v as contains
little harmonic content and the current waveform is nearly sinusoidal. Figure 3.1-7
shows the performance for a nine-level inverter under the same operating conditions.
Due to the higher number of voltage levels, a smaller output filter can be used to
obtain the same voltage THD at the load terminals.
The above studies were performed with three- and five-level inverters for further
comparison. The results are shown in Figure 3.1-8. Therein, the line-to-neutral
voltage THD, output filter size, and inverter power losses are shown versus number
of voltage levels. Considering the THD, it can be seen that there is a significant
difference between the two- and three-level inverters. However, as the number of
levels becomes large, the change in THD is not as great. As expected, the output
filter size has a similar characteristic versus levels as the THD. In this case, a 50 µF
capacitor was used for all studies and the inductor was sized to set the phase voltage
THD. The resistor was used to limit the gain at the resonant frequency. Although
more advanced filter techniques can be used the resistor could be sized in these
examples so that the power losses were less than 2% and the effect on filter
performance was negligible. The conduction losses are fairly constant, but the
switching losses decrease by a factor of three from the two-level to the nine-level
case. One might expect that the switching losses would decrease by a factor of n −1
or eight. In this example, a flying capacitor inverter [5] was used for the
implementation of the various levels and some of the savings in switching losses
were sacrificed in order to balance the flying capacitors. In this way, the inverter can
be operated from a single dc source as shown in Figure 3.1-1.
It should be pointed out that the decrease in filter inductance size is offset by the
need for flying capacitors. In the case of the nine-level inverter, seven 1000 µF
capacitors were needed having an average voltage of 3000 V and an average rms
current of 50 A. The exact sizing of these capacitors depends on the tolerable
voltage ripple. In this example, the voltage ripple for each capacitor was around 5%.
Although these tradeoffs exist, the multilevel inverter has some distinct advantages.
Besides lower switching losses, the output voltage dv/dt is lowered which improves
EMC and also reduces stresses on the filter circuitry. Additionally, the multilevel
inverter avoids series connection of devices for higher-voltage systems. In the above
examples, 1200 V, 300 A IGBTs were used for the switching devices. The twolevel
inverter had eight IGBTs in series to make up each switch. As a practical
matter, switching the series IGBTs so that they dynamically share the bus voltage is
a major challenge. Although it may be possible to use fewer higher-voltage IGBTs
instead, the switching characteristics of those IGBTs would make a 5 kHz switching
frequency unreasonable. However, lowering the switching frequency would lead to
a larger filter size. The nine-level inverter also used eight IGBTs, but they are not
Copyright 2005. K.A. Corzine 8