Presentation - Power Integrity Analysis in a split plane PCB

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Power integrity is becoming a critical issue in chip(IR), package(Ldi/dt) and PCB design. Power fluctuation affects delay budget in chip and produces noise on board. Power integrity is also important for mixed signal boards( e.g.. w. A/D, D/A) and EMI.
Lower voltage, split planes, poor stack up design, miss used decouple caps, and SSN/SSO all lead to power integrity problems.
Page 1 and 2: Power Integrity Analysis in a split
Page 3: New trend in high speed design: Pow
Page 7 and 8: Engineers used to depend on experie
Page 9 and 10: SIwave for Power Integrity SIwave c
Page 11 and 12: A ten-layer PCB with split power pl
Page 13 and 14: Bare 2.5v split plane resonance
Page 15 and 16: Mesh is dense in sensitive areas
Page 17 and 18: No resonance observed up to 350Mhz
Page 19 and 20: Small voltage fluctuation in 10MHZ
Page 21 and 22: Some local voltage fluctuation in 3
Page 23 and 24: Three 100uf caps added to reduce fl
Page 25 and 26: Resonance induced
Page 27 and 28: Z parameter vs. frequency at probe
Page 29 and 30: Add probe and port for plane crosst
Page 31 and 32: S parameter for split plane crossta
Page 33: Thanks a lot!

Presentation - Power Integrity Analysis in a split plane PCB

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