Presentation - Power Integrity Analysis in a split plane PCB

More documents

Recommendations

Info

Cell delay increased by 40% with 10% Power drop.
Engineers used to depend on experience and over-design to deal with power problems. This method can not cope with increasing frequency and complexity.
Page 1 and 2: Power Integrity Analysis in a split
Page 3 and 4: New trend in high speed design: Pow
Page 5: Lower voltage, split planes, poor s
Page 9 and 10: SIwave for Power Integrity SIwave c
Page 11 and 12: A ten-layer PCB with split power pl
Page 13 and 14: Bare 2.5v split plane resonance
Page 15 and 16: Mesh is dense in sensitive areas
Page 17 and 18: No resonance observed up to 350Mhz
Page 19 and 20: Small voltage fluctuation in 10MHZ
Page 21 and 22: Some local voltage fluctuation in 3
Page 23 and 24: Three 100uf caps added to reduce fl
Page 25 and 26: Resonance induced
Page 27 and 28: Z parameter vs. frequency at probe
Page 29 and 30: Add probe and port for plane crosst
Page 31 and 32: S parameter for split plane crossta
Page 33: Thanks a lot!

Presentation - Power Integrity Analysis in a split plane PCB

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?