Memory - Vodafone Chair Mobile Communications Systems

Vodafone Chair Mobile Communications Systems, Prof. Dr.-Ing. G. Fettweis 

Jan Dohl 

Benedikt Nöthen 

Digital Signal Transmission Lab 

SS 2012 

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Vodafone Chair 

Tomahawk (Jan. 2008) Tomahawk2 (2012) 

Möglichkeiten für Studenten: 

Studienarbeit 

Diplomarbeit 

SHK (8,28 Euro) 

Ansprechpartner 

- Hardware 

- Software 

Oliver Arnold (oliver.arnold@ifn.et.tu-dresden.de) 

- Simulation 

- Verifikation 

Steffen Kunze (steffen.kunze@ifn.et.tu-dresden.de) 

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TU Dresden, 6/4/2012 Slide 2

Termine 

05. Juni: Einführungsveranstaltung (BAR II/63a) 

07. Juni: kurzer Test (BAR IV/1) 

Versuche: Jeweils Dienstag,14:50 Uhr, Bar IV/1 

12. Juni: Versuch 1: Realisierung eines Echos in Audiodaten 

19. Juni: Versuch 2: Abtastratenerhöhung 

26. Juni: Versuch 3: Synchronisation und Decodierung 

03. Juli: Versuch 4: Realisierung einer 16-QAM Übertragungsstrecke 

E-Mail-Verteiler 

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Introduction 

Hardware 

Why to use digital signal processing? 

General introduction to DSPs 

The TMS320C6455 DSP 

Architecture Overview 

Peripherals 

DSK6455 evaluation board - Software 

Code Composer Studio 

DSP/BIOS 

Multi-channel Buffered Serial Port (McBSP) 

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Hardware 

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Digital Signal Processing (DSP) 

Wireless / Cellular 

Voice-band audio 

RF codecs 

Voltage regulation 

Consumer Audio 

Stereo A/D, D/A 

PLL 

Mixers 

Multimedia 

Stereo audio 

Imaging 

Graphics palette 


DSP: 

Technology 

Enabler 

HDD 

PRML read channel 

MR pre-amp 

Servo control 

SCSI tranceivers 

DTAD 

Speech synthesizer 

Mixed-signal 

processor 

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Automotive 

Digital radio A/D/A 

Active suspension 



System Considerations 

Size 

Interfacing 

Ease-of Use 

• Programming 

• Interfacing 

• Debugging 

Performance 

Cost 

• Device cost 

• System cost 

• Development cost 

• Time to market 

Power 

Integration 

• Memory 

• Peripherals 

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Why Go Digital? 

Easier 

Digital signal processing techniques are now so 

powerful that sometimes it is extremely difficult, if 

not impossible, for analogue signal processing to 

achieve similar performance. 

Examples: 

FIR filter with linear phase 

Adaptive filters 

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Analogue signal processing is achieved by 

using analogue components such as: 

Resistors 

Capacitors 

Inductors 

Inherent tolerances: 

Temperature 

Voltage changes 

Mechanical vibrations 

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With DSP? - It is easy to: 

Change applications 

Correct applications 

Update applications 

Additionally DSPs reduce: 

Noise susceptibility 

Chip count 

Development time 

Cost 

Power consumption 

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General Introduction to DSPs 

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What Problem Are We Trying To Solve? 

Digital sampling of 

an analog signal: 

A 

ADC 

t 

x Y 

DSP 

Most DSP algorithms can be 

expressed as: 

count 

DAC 

Y = Σ ai * xi i = 1 

for (i = 1; i < count; i++){ 

sum += m[i] * n[i]; } 

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What are the typical DSP algorithms? 

The Sum of Products (SOP) is the key element in 

most DSP algorithms: 

Algorithm Equation 

Finite Impulse Response Filter 

Infinite Impulse Response Filter 

Convolution 

Discrete Fourier Transform 

Discrete Cosine Transform 

yn ( ) = a xn ( − k) 

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TU Dresden, 6/4/2012 Slide 13 

y( 

n) 

= 

F 

M 

∑ 

k= 

0 

a 

k 

y( 

n) 

= 

∑ − N 1 

n= 

0 

M 

∑ 

k = 0 

k 

x( 

n − k) 

+ 

N 

∑ 

k= 

0 

N 

∑ 

k= 

1 

b 

k 

x( 

k) 

h( 

n − k) 

y( 

n − k) 

X ( k) 

= x( 

n) 

exp[ − j( 

2π 

/ N) 

nk] 

∑ − N 1 

x= 

0 

⎡ π 

⎢ 

⎣2N 

( u) 

= c( 

u). 

f ( x). 

cos u( 

2x 

+ 1) 

⎤ 

⎥ 

⎦

Why do we need DSP processors? 

Use a DSP processor when the following 

are required: 

Cost saving 

Smaller size 

Low power consumption 

Processing of many “high” frequency signals in 

real-time 

Use a GPP processor when the following 

are required: 

Large memory 

Advanced operating systems 

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Hardware vs. Microcode multiplication 

DSP processors are optimized to perform 

multiplication and addition operations. 

Multiplication and addition are done in 

hardware and in one cycle. 

Example: 4-bit multiply (unsigned). 

Hardware Microcode 

1011 

x 1110 

1011 

x 1110 

10011010 0000 

1011. 

1011.. 

1011... 

10011010 

Cycle 1 

Cycle 2 

Cycle 3 

Cycle 4 

Cycle 5 

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General Purpose DSP vs. DSP in ASIC 

Application Specific Integrated Circuits 

(ASICs) are semiconductors designed for 

dedicated functions. 

The advantages and disadvantages of using 

ASICs are listed below: 

Advantages 

• High throughput 

• Lower silicon area 

• Lower power consumption 

• Improved reliability 

• Reduction in system noise 

• Low overall system cost 

Disadvantages 

• High investment cost 

• Less flexibility 

• Long time from design to 

market 

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Floating vs. Fixed point processors 

Applications which require: 

High precision 

Wide dynamic range 

High signal-to-noise ratio 

Ease of use 

Need a floating point processor 

Drawback of floating point processors: 

Higher power consumption 

Usually higher cost 

Usually slower than fixed-point counterparts and 

larger in size 

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TMS320C6455 Architectural Overview 

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General DSP System Block Diagram 

External 

Memory 

Internal Memory 

Internal Buses 

Central 

Processing 

Unit 

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P 

E 

R 

I 

P 

H 

E 

R 

A 

L 

S

‘6455 CPU Overview 

Specification 

Clock Rate: 1/1.2 GHz 9600 MIPS 

0.09-μm/7-Level Metal Process – CMOS Technology 

CPU has got two Datapaths, altogether: 

2* .M, 

2* .L, 

2*.S, 

2*.D 

2* 32 32-Bit General-Purpose Registers 

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‘6455 CPU Overview 

VelociTI advanced very-long instruction words (VLIW) 

Program Memory Width is 256 Bit 

Up to 8 32-Bit instructions can be executed in parallel/Cycle 

16, 32 and 40 bit fixed point operands 

Instruction parallelism is detected at compile-time 

no data dependency checking is done in Hardware. 

Instruction Packing Reduces Code Size 

All operations work on registers 

Memory Architecture 

32K-Byte L1P Program Cache (Direct Mapped) 

32K-Byte L1D Data Cache (2-Way Set-Associative) 

2048K-Byte L2 Unified Mapped RAM/L2 Cache (Flexible 

Data/Program Allocation) 

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Functional Block and CPU Diagram 

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A ‘6455 Datapath 

.S & .L 

.M 

.D 

Arithmetic, Logical 

& Branch functions 

Multiply, Rotation, 

Bit expansion 

Data-addressing 

Only way to access 

memory 

Cross path 

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Functional Units and Operations Performed 

Functional Unit Fixed-Point Operations 

.L unit (.L1, .L2) 32/40-bit arithmetic and compare operations, 

32-bit logical operations, 

Leftmost 1 or 0 counting for 32 bits, 

Byte shifts, 5-bit constant generation 

.S unit (.S1, .S2) 32-bit arithmetic operations, 

32/40-bit shifts and 32-bit bit field operations, 

32-bit logical operations, Branches, Byte shifts, 

Register transfer to/from control register file (.S2 only) 

.M unit (.M1, .M2) 32x32-bit multiply, 16x16-bit multiply, 16x32-bit multiply, 

rotation, variable shift operations 

.D unit (.D1, .D2) 32-bit add, substract, linear and circular address calculation 

32-bit logical operations, 5-bit constant generation, 

Loads and stores 5-bit/15-bit constant offset 

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C6400: Instruction Set 

.S 

.L 

.D 

.M 

ADD 

ADDK 

ADD2 

AND 

B 

CLR 

EXT 

MV 

MVC 

MVK 

MVKH 

.S Unit 

NEG 

NOT 

OR 

SET 

SHL 

SHR 

SSHL 

SUB 

SUB2 

XOR 

ZERO 

ADD 

ADDAB (B/H/W) 

LDB (B/H/W) 

LDDW 

MV 

.D Unit 

ABSSP 

ABSDP 

CMPGTSP 

CMPEQSP 

CMPLTSP 

CMPGTDP 

CMPEQDP 

CMPLTDP 

RCPSP 

RCPDP 

RSQRSP 

RSQRDP 

SPDP 

NEG 

STB (B/H/W) 

SUB 

SUBAB (B/H/W) 

ZERO 

ABS 

ADD 

AND 

CMPEQ 

CMPGT 

CMPLT 

LMBD 

MV 

NEG 

NORM 

MPY 

MPYH 

MPYLH 

MPYHL 

No Unit Used 

IDLE 

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NOP 

.L Unit 

NOT 

OR 

SADD 

SAT 

SSUB 

SUB 

SUBC 

XOR 

ZERO 

.M Unit 

SMPY 

SMPYH 

ADDSP 

ADDDP 

SUBSP 

SUBDP 

INTSP 

INTDP 

SPINT 

DPINT 

SPRTUNC 

DPTRUNC 

DPSP 

MPYSP 

MPYDP 

MPYI 

MPYID

'C6x System Block Diagram 

Ext’l 


- Sync 

- Async 

Addr 

D (32) 

EMIF 

Program 

RAM 

Regs (A0-A31) 


.D1 

.M1 

.L1 

.S1 

.D2 

.M2 

CPU 

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.L2 

.S2 

Control Regs 

Regs (B0-B31) 

Data Ram 

DMA 

Serial Port 

Host Port 

Boot Load 

Timers 

Pwr Down

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‘C6455 Memory Map 

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How are Peripherals Controlled? 

Control and configuration of internal peripherals is done 

by memory mapped control registers 

Example of Timer mode control register: 

31 

7 

HLD 

6 

GO 

Rsvd 

5 

Rsvd 

4 

PWID 

12 

TSAT 

DATIN 

INVIMP 

DATOUT 

CLKSRC 

INVOUT 

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11 

3 

10 

2 

9 

1 

8 

C/P 

0 

Func

Operands 

Operands can be 

5-bit constants (or 16-bit in some special instruct.) 

32-bit Registers 



A 40-bit or a 64-bit register can be obtained by 

concatenating two registers 

The registers must be from the same side 

The first register must be even and the second odd (e.g. 

A1:A0, B9:B8 or A15:A14) 

The registers must be consecutive 

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Conditional execution 

All instructions in each Functional Unit of both Data 

paths can be executed conditionally 

Only the Registers A1, A2, B0, B1, B2 can hold the 

condition 

Conditional Execution uses the Syntax 

e.g 

[!condition] Instruction 

[!B0] ADD.L1 A1,A2,A3 ; add if B0 ==0 

[B0] ADD.L1 A1,A2,A3 ; add if B0 != 0 

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Branches 

Branches are required to realize loops and change 

the program flow 

Branches are very useful in conjunction with 

conditional execution 

There are two branch types supported: 

Relative Branching 

Absolute Branching 

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More on the Branch Instruction (1) 

With this processor all the instructions are encoded 

in a 32-bit. 

Therefore the label must have a dynamic range of 

less than 32-bit as the instruction B has to be 

coded. 

B 

Case 1: B .S1 label 

Relative branch. 

32-bit 

21-bit relative address 

Label limited to +/- 2 20 offset. 

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More on the Branch Instruction (2) 

By specifying a register as an operand instead of 

a label, it is possible to have an absolute branch. 

This will allow a dynamic range of 2 32 . 

Case 2: B .S2 register 

B 

Absolute branch. 

32-bit 

Operates on .S2 ONLY! 

5-bit register 

code 

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Getting Data from the Memory 

All Instructions work exclusively on Registers 

The .D Units in the Data-Paths are used to load and 

store the required Data from and to the Memory 

Load and Store Instructions use an Address 

operator X: 

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Addressing Modes 

There are two addressing modes supported: 

Linear Addressing 

Circular Addressing (e.g. Convolution) 

Circular Addressing supports block sizes 2 N 

Only the lower N bits of the Address are modified by address 

arithmetic. This equals mod(2 N ) operations. 

The addressing mode is selected by control register 

„AMR‘ 

Operands for CA are limited to A4-A7, B4-B7 

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Floating vs. Fixed point processors 

Fixed point arithmetic 

16-bit (integer or fractional) 

Signed or unsigned 

Floating point arithmetic 

32-bit single precision 

64-bit single precision 

Using signed and unsigned integers: 

Multiplication overflow. 

Addition overflow 

Saturate the result 

Double precision result 

Fractional arithmetic 

( n) 

= a( 

k) 

x( 

n − k) 

e.g. If A and B are fractional then: A x B < min(A, B) 

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y 

∑ − N 1 

k = 0

C6000 C Data Types 

Type Size Representation 

char, signed char 8 bits ASCII 

unsigned char 8 bits ASCII 

short 16 bits 2’s complement 

unsigned short 16 bits binary 

int, signed int 32 bits 2s complement 

unsigned int 32 bits binary 

long, signed long 40 bits 2’s complement 

unsigned long 40 bits binary 

enum 32 bits 2’s complement 

float 32 bits IEEE 32-bit 

double 64 bits IEEE 64-bit 

long double 64 bits IEEE 64-bit 

pointers 32 bits binary 

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Numerical Issues - Useful Tips 

Multiply by 2: Use shift left 

Divide by 2: Use shift right 

Log 2N: Use shift 

Sine, Cosine, Log: Use look up tables 

To convert a fractional number to hex: 

Num x 2 15 

Then convert to hex 

e.g: convert 0.5 to hex 

0.5 x 2 15 = 16384 

(16384) dec = (0x4000) hex 

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Numerical Issues - 32-bit Multiplication 

It is possible to perform 32-bit multiplication 

using 16-bit multipliers. 

Example: c = a x b (with 32-bit values). 

a = 

b = 

a h 

b h 

32-bits 

a * b = (a h

Selected ‘6455 Peripherals 

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C6000 Peripherals 

Host µC 

External 


XB 

Host Port 

PCI 

16/32 EMIF 

McBSPs 

EDMA 

DMA 

Boot Loader 

Timer/Count 

PLL 


.D1 

.M1 

.L1 

.S1 

.D2 

.M2 

.L2 

.S2 

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Regs (A0-A15/31) 

Internal 


CPU 

Regs (B0-B15/31)

The McBSP 

Multichannel Buffered Serial Port 

Up to 100 Mb/sec performance 

full-duplex, synchronous serial-ports 

Enables direct interfacing to industry standard 

Codecs, Analog interface Chips and other serially 

connected devices 

Supports a wide range of data-sizes, including 8, 12, 

16, 20, 24 and 32 bits 

Bit, Word(channel), Frame 

In our lab the McBSP is used to connect to the A/D, 

D/A 

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ADC/DAC 

24-bit resolution 

Multiple Digital Transfer widths (16-,20-, 24-, 32-bits) 

SAMPLING RATE: Up to 96kHz 

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What is the bootloader? 

VCC 

EPROM 

VCC 

EMIF 

DMA 

C6211/C6711 

Boot Config 

When the DSP is NOT powered or under 

reset the internal program memory is in a 

random state. 

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L2 Cache 

L1P Cache 

CPU 

L1D Cache 

Addr 

0000 

0001 

0002 

0003 

...


VCC 

EPROM 

VCC 

EMIF 

DMA 

C6211/C6711 

Boot Config 

When the DSP is powered and the CPU is taken out of 

reset the internal memory is still in a random state and 

the program will start running for address zero. 

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L2 Cache 

L1P Cache 

CPU 

PC=0000 PC=0001 PC=0002 PC=0003 

L1D Cache 

Addr 

0000 

0001 

0002 

0003 

...


VCC 

EPROM 

VCC 

EMIF 

DMA 

C6211/C6711 

Boot Config 

With the boot, a portion of code can be 

automatically copied from external to internal 

memory. 

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L2 Cache 

L1P Cache 

CPU 

L1D Cache

Interrupts 

DSPs must be able to execute tasks on 

asynchronous events 

Interrupts suspend the current processor task 

and save its context 

A interrupt service routine (ISR) is executed 

After completion of the ISR, the context of the 

former task is restored and the execution 

continues 

Interrupts are organized hierarchically 

vs. Polling 

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Interrupt Interrupt- and Thread Types 

HWI priorities set by hardware 

One ISR per interrupt 

14 SWI priority levels Multiple 

SWIs at each level 

15 TSK priority levels Multiple 

TSKs at each level 

Multiple IDL functions 

Continuous loop 

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HWI triggered by hardware interrupt 

IDL runs as the background thread 


The DSK6455 Development Kit 

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Code Composer Studio and the DSK 

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Code Composer Studio 

The Code Composer Studio (CCS) application 

provides an integrated environment with the 

following capabilities: 

Integrated development environment with an editor, 

debugger, project manager, profiler, etc. 

‘C/C++’ compiler, assembly optimiser and linker 

(code generation tools). 

Simulator. 

Real-time operating system (DSP/BIOS). 

Real-Time Data Exchange (RTDX) between the 

Host and Target. 

Real-time analysis and data visualisation. 

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Hardware: (2) DSK Connections 

(A) Parallel port: The PC’s USB port is connected to the DSK. 

USB 

PC DSK 

Power 

Supply 

Line-level Output 

Line-level Input 

(B) JTAG: An XDS JTAG emulator connected to the PC (either 

internal or external) is connected to the JTAG header on the DSK. 

JTAG 

PC DSK 

XDS 

Power 

Supply 

External 

Power 

Supply 

External 

Power 

Supply 

Line-level Output 

Line-level Input 

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Laboratory Exercise: Using CCS 

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Click on Project properties 

Add include search paths: 

"C:\ti\ccsv5\dsk6455_v2\boards\dsk6455_v2\csl_c64xplus_intc\inc" 

"C:\ti\ccsv5\dsk6455_v2\boards\dsk6455_v2\csl_c6455\inc" 

"C:\ti\ccsv5\dsk6455_v2\boards\dsk6455_v2\include" 

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Add Library files to be included: 

"C:\ti\ccsv5\dsk6455_v2\boards\dsk6455_v2\lib\dsk6455bsl\dsk6455bsl.lib" 

"C:\ti\ccsv5\dsk6455_v2\boards\dsk6455_v2\csl_c6455\lib\csl_c6455.lib" 

Add Library search paths: 

"C:\ti\ccsv5\dsk6455_v2\boards\dsk6455_v2\lib\dsk6455bsl" 

"C:\ti\ccsv5\dsk6455_v2\boards\dsk6455_v2\csl_c6455\lib" 

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DSP/BIOS 

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DSP/BIOS Components 

The user writes code (‘C’/assembly) using the DSP/BIOS library. 

The user can use the configuration tools to setup the system. 

All the files generated constitute a project. 

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DSP/BIOS Components 

The project is then compiled, assembled and linked by the code 

generation tools in order to generate an executable file (*.out). 

There are also some DSP/BIOS plug-ins that can be used, for 

instance, as program test while the target is running. 

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Graphical Interface for Static System 

Setup 

The DSP/BIOS main objects are: 

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(1) Hardware interrupts (HWI). 

(2) Software interrupts (SWI). 

(3) Tasks (TSK, IDL). 

(4) Data and I/O streams (RTDX, SIO, PIP, HST). 

(5) Synchronisation and Communication (SEM, MBX, 

LCK). 

(6) Timing (PRD, CLK). 

(7) Logging and statistics (LOG, STS, TRC). 

For a complete list see: \Links\SPRU303.pdf (Page 1-5). 


Project Configurations 

Right Click on Project new target 

Configuration file 

Open Configuration file and select: DSK6455 

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Right click->new->others 

Select DSP/BIOS v5x configuration file 

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DSP/BIOS configuration window opens 

automatically: select DSK6455 

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Open the tcf File: 

» 

• Right click SWI->insert swi-> name it Process Buffer Swi 

• Right click process buffer swi 

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Multi-channel Buffered Serial Port (McBSP) 

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Objectives 

Definition of Terms: 

Bit, word or channel, frame and phase. 

Understand basic serial port operation. 

Understand clock generation. 

Pin polarity. 

Serial port interrupts. 

Describe multi-channel operation. 

Programming the serial port. 

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Basic Definitions: Bits, Words ? 

CLK 

FS 

Data 

Data 

a1 a0 

Serial Port 

SP Ctrl (SPCR) 

Rcv Ctrl (RCR) 

Xmt Ctrl (XCR) 

Rate (SRGR) 

Pin Ctrl (PCR) 

Bit 

b7 b6 b5 b4 b3 b2 b1 b0 

Word 

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“Bit” - one data bit per SP clock period. 

“Word” or “channel” contains #bits specified by 

WDLEN1 (8, 12, 16, 20, 24, 32). 

7 5 

RWDLEN1 

7 5 

XWDLEN1 


Basic Definitions: Frame? 

FS 

ata 

w6 w7 

Serial Port 




Rate (SRGR) 


Word 

w0 w1 w2 w3 w4 w5 w6 w7 

Frame 

“Frame” - contains one or multiple words. 

FRLEN1 specifies #words per frame (1-128). 

RFRLEN1 

RWDLEN1 

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14 

14 

8 

8 

XFRLEN1 

7 

7 

5 

5 

XWDLEN1

Objectives 





Pin polarity. 

Serial port interrupts. 



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Serial Port - Basic Operation 

DR 

DX 

CLKR 

CLKX 

FSR 

FSX 

Multi-Channel Buffered 

Serial Port (McBSP) 

RSR RBR 

DRR 

XSR 

Serial Port 

Control Logic 

SPCR RCR 

Peripheral Bus 

SRGR 

XCR PCR 

DXR 

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P 

e 

r 

i 

p 

h 

B 

u 

s 

“TRANSMIT” 

“RECEIVE” 

CPU 

DMA

McBSP Registers 

Receive 

Transmit 

Control 

RSR Receive Shift Reg 

RBR Receive Buffer Reg 

DRR Data Receive Reg 

XSR Transmit Shift Reg 

DXR Data Transmit Reg 

SPCR Serial Port Control Reg 

RCR Receive Control Reg 

XCR Transmit Control Reg 

SRGR Sample Rate Generator 

PCR Pin Control Reg 

MCR Multi-Channel Ctrl Reg 

RCER Rcv Channel Enable Reg 

XCER Xmit Channel Enable Reg 

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Objectives 





Pin polarity. 

Serial port status and interrupts. 



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RRDY/XRDY Status and Interrupts 

RBR DRR 

XSR DXR 

Serial Port 




Rate (SRGR) 


RRDY=1 

“Ready to Read” 

XRDY=1 

“Ready to Write” 

CPU 

RINT 

XINT 

EDMA 

Sync 

XRDY 

RRDY/XRDY displays the 

“status” of the read and 

transmit ports: 

0: not ready. 

1: ready to read/write. 

There are 3 methods for 

detecting if data is ready: 

RRDY 

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17 

Poll SPCR bits via s/w. 

Config CPU ints 

(RINT/XINT). 

Program DMA sync events. 

1

Next Steps 

Create a new C function: 

processData(Int16 *inBuf, Int16 outBuf, int16 length) 

Function will be called by HWI/SWI routine 

inBuf is pointer to samples of the in-Signal 

outBuf. is pointer to processed samples ready for 

audio out 

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