Multimedia Board Schematics
Multimedia Board Schematics
Multimedia Board Schematics
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5<br />
5<br />
4<br />
4<br />
3<br />
RED PB12<br />
RESET_IN<br />
53<br />
RESET_IN<br />
D RESET_IN<br />
D<br />
CLOCK27MHZ<br />
22<br />
CLOCK27MHZ<br />
XC95144XL_TQ100<br />
STARTUP<br />
25<br />
STARTUP<br />
TV_OUT_RESET_Z<br />
AUDIO_RESET_Z<br />
49<br />
41<br />
TV_OUT_RESET_Z<br />
AUDIO_RESET_Z<br />
XC95144XL_TQ100<br />
U1B<br />
D1<br />
R30<br />
C<br />
R29<br />
3K0 5%<br />
PROG_CPLD_TDI<br />
PROG_CPLD_TMS<br />
PROG_CPLD_TCK<br />
PROG_CPLD_TDO<br />
SERIAL_SELECT0<br />
SERIAL_SELECT1<br />
45<br />
47<br />
48<br />
83<br />
8<br />
7<br />
TDI<br />
TMS<br />
TCK<br />
TD0<br />
SERIAL_SEL0<br />
SERIAL_SEL1<br />
VIDEO_DECODER_CLOCK<br />
TV_OUT_CLOCK<br />
HC3_SYSTEM_CLOCK<br />
MASTER_CLOCK<br />
PS2_PORT1_ENZ<br />
PS2_PORT2_ENZ<br />
RS232_DATA_ENZ<br />
RS232_CTRL_ENZ<br />
24<br />
35<br />
50<br />
40<br />
18<br />
19<br />
36<br />
37<br />
R31<br />
CLOCK_OUT1<br />
VIDEO_DECODER_CLOCK<br />
27.4 1%<br />
CLOCK_OUT2 R33<br />
TV_OUT_CLOCK<br />
27.4 1%<br />
CLOCK_OUT3 R35<br />
HC3_SYSTEM_CLOCK<br />
27.4 1%<br />
CLOCK_OUT4 R37<br />
MASTER_CLOCK<br />
27.4 1%<br />
PS2_PORT1_ENZ<br />
PS2_PORT2_ENZ<br />
RS232_DATA_ENZ<br />
RS232_CTRL_ENZ<br />
PB1<br />
PB2<br />
PB3<br />
PB4<br />
PB5<br />
PB6<br />
PB7<br />
PB8<br />
PB9<br />
PB10<br />
PB11<br />
6<br />
1<br />
2<br />
99<br />
97<br />
93<br />
92<br />
87<br />
74<br />
73<br />
72<br />
PB1<br />
PB2<br />
PB3<br />
PB4<br />
PB5<br />
PB6<br />
PB7<br />
PB8<br />
PB9<br />
PB10<br />
PB11<br />
XC95144XL_TQ100<br />
PB1_LED_Z<br />
PB2_LED_Z<br />
PB3_LED_Z<br />
PB4_LED_Z<br />
PB5_LED_Z<br />
PB6_LED_Z<br />
PB7_LED_Z<br />
78<br />
67<br />
94<br />
89<br />
90<br />
96<br />
85<br />
PB1_LED_Z<br />
PB2_LED_Z<br />
PB3_LED_Z<br />
PB4_LED_Z<br />
PB5_LED_Z<br />
PB6_LED_Z<br />
PB7_LED_Z<br />
AMBER<br />
D3<br />
AMBER<br />
D5<br />
AMBER<br />
D7<br />
D2 130 5%<br />
AMBER<br />
R34<br />
D4 130 5%<br />
AMBER<br />
R38<br />
D6 130 5%<br />
AMBER<br />
R40<br />
R32<br />
130 5%<br />
R36<br />
130 5%<br />
R39<br />
130 5%<br />
VCC3V3<br />
C<br />
AMBER<br />
D8 130 5% R41<br />
XC95144XL_TQ100<br />
PB_CLOCK<br />
65<br />
PB_CLOCK<br />
PB8_LED_Z<br />
81 PB8_LED_Z<br />
AMBER<br />
PB_DATA<br />
R42<br />
63<br />
PB_DATA<br />
PB9_LED_Z<br />
79 PB9_LED_Z<br />
D9<br />
R43 130 5%<br />
VCC3V3<br />
R44<br />
27.4 1%<br />
AMBER<br />
D10 130 5% R45<br />
B<br />
L3<br />
FERRITE BEAD SM<br />
CTCB1210-600-S<br />
EXTEND_DCM_RESET<br />
27.4 1%<br />
70<br />
EXTEND_DCM_RESET PB10_LED_Z<br />
PB11_LED_Z<br />
77<br />
76<br />
PB10_LED_Z<br />
PB11_LED_Z<br />
D11<br />
AMBER<br />
R47<br />
130 5%<br />
B<br />
RED<br />
D12 130 5% R48<br />
FPGA_DONE<br />
27<br />
FPGA_DONE FPGA_DONE_LED_Z<br />
16 FPGA_DONE_LED_Z<br />
1<br />
Y2<br />
ENABLE VCC<br />
6<br />
VCC3V3<br />
HC3_CFGPROGZ<br />
52<br />
PROG_FPGA_Z<br />
FPGA_PROG_LED_Z<br />
11 FPGA_PROG_LED_Z<br />
D13<br />
RED<br />
GREEN<br />
R49<br />
130 5%<br />
C38<br />
0.1uF<br />
2<br />
3<br />
NC<br />
GND<br />
NC<br />
OUT<br />
5<br />
4<br />
27.000MHZ 50PPM<br />
R46<br />
CLOCK27MHZ<br />
R227<br />
3K0 5% R51<br />
R50<br />
3K0 5% R52<br />
VCC_CORE<br />
3V3GOOD<br />
56<br />
59<br />
VCC_CORE<br />
3V3GOOD<br />
2V5_OK_Z<br />
3V5_OK_Z<br />
60<br />
58<br />
2V5_OK_Z<br />
3V3_OK_Z<br />
130 5%<br />
49.9 1%<br />
J10<br />
3K0 5%<br />
3K0 5%<br />
1V5GOOD<br />
61<br />
1V5GOOD<br />
1V5_OK_Z<br />
71<br />
1V5_OK_Z<br />
CPLD<br />
CONFIG<br />
JTAG<br />
PORT<br />
VIDEO_DECODER_RESET_Z<br />
HC3_RESET_Z<br />
ENET_RESET_Z<br />
JTAG_PROG_CON<br />
29<br />
34<br />
20<br />
U1A<br />
VIDEO_DECODER_RESET_Z<br />
HC3_RESET_Z<br />
ENET_RESET_Z<br />
A<br />
1<br />
2<br />
VCC3V3<br />
A<br />
3<br />
4<br />
5<br />
6<br />
PROG_CPLD_TDO<br />
PROG_CPLD_TDI<br />
PROG_CPLD_TCK<br />
PROG_CPLD_TMS<br />
XILINX INC.<br />
Title<br />
2100 Logic Drive San Jose California USA 95124<br />
3<br />
R226<br />
3K0 5%<br />
VCC3V3<br />
2<br />
2<br />
CPLD<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
3 of 35<br />
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