Multimedia Board Schematics
Multimedia Board Schematics
Multimedia Board Schematics
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5<br />
5<br />
AUDIO_5V<br />
4<br />
4<br />
3<br />
U26<br />
D D<br />
AUDIO_LEFT<br />
20K 5%<br />
L_SPKR_NEG<br />
L_SPKR_POS<br />
C<br />
AUDIO_RIGHT<br />
20K 5%<br />
R10<br />
C7<br />
0.33uF @ 35V<br />
R9<br />
20K 5%<br />
22<br />
9<br />
10<br />
BYPASS<br />
BFB<br />
BIN<br />
POWER HP_IN<br />
AMP<br />
+OUTB<br />
-OUTB<br />
21<br />
28<br />
26<br />
R8<br />
100K 5%<br />
R_SPKR_POS<br />
R_SPKR_NEG<br />
J9<br />
RIGHT<br />
SPEAKER<br />
3<br />
11<br />
10<br />
2<br />
1<br />
HEADPHONE<br />
OUTPUT<br />
PHONEJACK STEREO<br />
C<br />
20K 5%<br />
0.33uF @ 35V<br />
R11<br />
R12<br />
AUDIO_AMP_SHUTDOWN<br />
2<br />
SHUTDOWN<br />
BR1<br />
25<br />
B<br />
C10<br />
10K THUMBWHEEL POT<br />
B<br />
AUDIO_GND<br />
VCC5V0<br />
AUDIO_GND<br />
AUDIO_5V<br />
A L2<br />
A<br />
GND<br />
L1<br />
FERRITE BEAD<br />
2961666671<br />
+ C11<br />
10uF @ 16V<br />
FERRITE BEAD<br />
2961666671<br />
C1<br />
0.1uF<br />
R7<br />
+ C12<br />
1uF @ 20V<br />
C2<br />
0.1uF<br />
C6<br />
+<br />
+<br />
AUDIO_GND<br />
C3 + C4<br />
0.1uF 10uF @ 16V<br />
R6<br />
20K 5%<br />
1uF @ 20V<br />
+<br />
11<br />
13<br />
12<br />
5<br />
4<br />
3<br />
LM4835 AUDIO AMP<br />
AUDIO<br />
INTERNAL GAIN SELECT<br />
VOLUME<br />
CONNECT EXPOSED DAP<br />
TO EXPOSED GROUND<br />
PLANE<br />
1<br />
6<br />
BEEP<br />
A_FB<br />
AIN<br />
GND<br />
VDD<br />
MUTE<br />
MODE<br />
GND<br />
8<br />
16<br />
VDD<br />
GND<br />
14<br />
GND<br />
20<br />
27<br />
VDD<br />
AR2<br />
AR1<br />
-OUTA<br />
+OUTA<br />
BR2<br />
GND<br />
23<br />
19<br />
18<br />
17<br />
15<br />
24<br />
7<br />
R3<br />
20K 5%<br />
R13<br />
20K 5%<br />
AUDIO_GND<br />
3<br />
R4<br />
20K 5%<br />
C9<br />
0.1uF<br />
R5<br />
C484<br />
20K 5%<br />
20K 5%<br />
C485<br />
68nF<br />
68nF<br />
R1<br />
AUDIO_GND<br />
AUDIO_5V<br />
VOLUME<br />
C5 220uF @ 10V<br />
+<br />
+<br />
C8 220uF @ 10V<br />
2<br />
J8<br />
2<br />
R15<br />
1K0 5%<br />
LEFT<br />
SPEAKER<br />
Title<br />
R14<br />
1K0 5%<br />
XILINX INC.<br />
R2<br />
100K 5%<br />
2100 Logic Drive San Jose California USA 95124<br />
AUDIO POWER AMPLIFIER<br />
J7<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
1 of 35<br />
1
RIGHT<br />
AUDIO<br />
INPUTS<br />
5<br />
5<br />
4<br />
4<br />
3<br />
D<br />
J1B<br />
R18<br />
AUDIO_GND<br />
D<br />
5CH1_L_IN<br />
C20 CH1_L<br />
GND<br />
LEFT<br />
6<br />
RCA<br />
4<br />
AUDIO_GND<br />
4K7 5%<br />
0.33uF @ 35V<br />
R19<br />
4K7 5%<br />
BEEP_TONE<br />
CH1_R<br />
12<br />
24<br />
PC_BEEP<br />
LINE_IN_R<br />
U2<br />
RESET<br />
SDATA_OUT<br />
11<br />
5<br />
AUDIO_RESET_Z<br />
AC97_SDATA_OUT<br />
AUDIO_GND<br />
CH1_L<br />
23<br />
LINE_IN_L<br />
SDATA_IN<br />
8<br />
AC97_SDATA_IN<br />
MIC1<br />
21<br />
MIC1<br />
SYNCH<br />
10<br />
AC97_SYNCH<br />
6K8 5%<br />
0.33uF @ 35V<br />
18<br />
CD_L<br />
10K 5%<br />
C<br />
R22<br />
4K7 5%<br />
17<br />
16<br />
VIDEO_R<br />
VIDEO_L<br />
AMP_PWR_DWN<br />
LNLVL_OUT_R<br />
47<br />
41 LINE_R<br />
AUDIO_AMP_SHUTDOWN<br />
C<br />
AUDIO_GND<br />
15<br />
AUX_R<br />
LNLVL_OUT_L<br />
39 LINE_L<br />
14<br />
AUX_L<br />
LINE_OUT_R<br />
36<br />
AUDIO_RIGHT<br />
LEFT<br />
RCA<br />
6<br />
4<br />
R24<br />
1uF @ 20V<br />
AUDIO_GND<br />
AUDIO_GND<br />
B<br />
LINE<br />
OUTPUT<br />
AUDIO_GND<br />
47K 5%<br />
AUDIO_GND<br />
C24<br />
270pF<br />
C25<br />
100nF<br />
Y1<br />
B<br />
C26<br />
RIGHT<br />
J1C<br />
RCA<br />
AUDIO_GND<br />
BEEP_TONE_IN<br />
J2B<br />
R16<br />
8CH1_R_IN<br />
9<br />
7<br />
4K7 5%<br />
R21<br />
C13<br />
+<br />
0.33uF @ 35V<br />
R17<br />
4K7 5%<br />
+<br />
+<br />
+<br />
CH1_R<br />
BEEP_TONE<br />
C23<br />
5 LINE_OUT_L LINE_L<br />
J2C<br />
RCA<br />
8<br />
9<br />
7<br />
LINE_OUT_R<br />
R25<br />
C27<br />
LINE_R<br />
1uF @ 20V<br />
270pF<br />
C28<br />
47nF<br />
24.576 MHz<br />
R26<br />
47K 5%<br />
AUDIO_GND<br />
C29 1M0 5%<br />
C31 + + C32<br />
22pF<br />
1uF @ 20V 1uF @ 20V<br />
AUDIO_GND AUDIO_GND<br />
GND<br />
+<br />
C21<br />
PHONEJACK STEREO<br />
AUDIO_GND<br />
+<br />
3<br />
AUDIO_5V<br />
C22<br />
+<br />
MONO<br />
1uF @ 20V<br />
R23<br />
47K 5%<br />
AUDIO_GND<br />
C15<br />
0.1uF<br />
22<br />
20<br />
19<br />
13<br />
37<br />
48<br />
MIC2<br />
CD_R<br />
CD_GND<br />
26<br />
AVSS<br />
PHONE_IN<br />
MONO_OUT<br />
SPDIF<br />
AFILT1<br />
29<br />
42<br />
AVSS<br />
2<br />
2<br />
VCC3V3<br />
AC97 CODEC<br />
AUDIO MIXER AND CODEC<br />
AFLT2<br />
30<br />
25<br />
AVDD<br />
31<br />
38<br />
FILT_L<br />
AVDD<br />
44<br />
NC<br />
FILT_R<br />
32<br />
43<br />
NC<br />
34<br />
AUDIO_GND<br />
40<br />
CX3D<br />
NC<br />
1<br />
DVDD<br />
RX3D<br />
33<br />
9<br />
DVDD<br />
VREF_OUT<br />
28<br />
4<br />
DVSS<br />
27<br />
7<br />
VREF<br />
DVSS<br />
XTAL_IN<br />
2<br />
+ C17<br />
10uF @ 16V<br />
BIT_CLOCK<br />
LINE_OUT_L<br />
XTAL_OUT<br />
3<br />
CS0<br />
CS1<br />
C18<br />
0.1uF<br />
AC97 AUDIO PROCESSOR<br />
6<br />
45<br />
46<br />
35<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
2 of 35<br />
1<br />
C30<br />
22pF<br />
GND<br />
C19<br />
0.1uF<br />
AC97_BIT_CLOCK<br />
R20<br />
R28<br />
MIC_PWR<br />
C33<br />
100nF<br />
+ C34<br />
10uF @ 16V<br />
10K 5%<br />
J17<br />
2K0 5%<br />
A<br />
MIC 1<br />
INPUT<br />
3<br />
11<br />
10<br />
2<br />
1<br />
C36<br />
470pF<br />
C35<br />
MIC1<br />
0.33uF @ 35V<br />
C37<br />
470pF<br />
XILINX INC.<br />
Title<br />
AUDIO_GND<br />
2100 Logic Drive San Jose California USA 95124<br />
A<br />
C14<br />
0.1uF<br />
+ C16<br />
10uF @ 16V<br />
AUDIO_LEFT<br />
R27<br />
VCC3V3<br />
AUDIO_5V
5<br />
5<br />
4<br />
4<br />
3<br />
RED PB12<br />
RESET_IN<br />
53<br />
RESET_IN<br />
D RESET_IN<br />
D<br />
CLOCK27MHZ<br />
22<br />
CLOCK27MHZ<br />
XC95144XL_TQ100<br />
STARTUP<br />
25<br />
STARTUP<br />
TV_OUT_RESET_Z<br />
AUDIO_RESET_Z<br />
49<br />
41<br />
TV_OUT_RESET_Z<br />
AUDIO_RESET_Z<br />
XC95144XL_TQ100<br />
U1B<br />
D1<br />
R30<br />
C<br />
R29<br />
3K0 5%<br />
PROG_CPLD_TDI<br />
PROG_CPLD_TMS<br />
PROG_CPLD_TCK<br />
PROG_CPLD_TDO<br />
SERIAL_SELECT0<br />
SERIAL_SELECT1<br />
45<br />
47<br />
48<br />
83<br />
8<br />
7<br />
TDI<br />
TMS<br />
TCK<br />
TD0<br />
SERIAL_SEL0<br />
SERIAL_SEL1<br />
VIDEO_DECODER_CLOCK<br />
TV_OUT_CLOCK<br />
HC3_SYSTEM_CLOCK<br />
MASTER_CLOCK<br />
PS2_PORT1_ENZ<br />
PS2_PORT2_ENZ<br />
RS232_DATA_ENZ<br />
RS232_CTRL_ENZ<br />
24<br />
35<br />
50<br />
40<br />
18<br />
19<br />
36<br />
37<br />
R31<br />
CLOCK_OUT1<br />
VIDEO_DECODER_CLOCK<br />
27.4 1%<br />
CLOCK_OUT2 R33<br />
TV_OUT_CLOCK<br />
27.4 1%<br />
CLOCK_OUT3 R35<br />
HC3_SYSTEM_CLOCK<br />
27.4 1%<br />
CLOCK_OUT4 R37<br />
MASTER_CLOCK<br />
27.4 1%<br />
PS2_PORT1_ENZ<br />
PS2_PORT2_ENZ<br />
RS232_DATA_ENZ<br />
RS232_CTRL_ENZ<br />
PB1<br />
PB2<br />
PB3<br />
PB4<br />
PB5<br />
PB6<br />
PB7<br />
PB8<br />
PB9<br />
PB10<br />
PB11<br />
6<br />
1<br />
2<br />
99<br />
97<br />
93<br />
92<br />
87<br />
74<br />
73<br />
72<br />
PB1<br />
PB2<br />
PB3<br />
PB4<br />
PB5<br />
PB6<br />
PB7<br />
PB8<br />
PB9<br />
PB10<br />
PB11<br />
XC95144XL_TQ100<br />
PB1_LED_Z<br />
PB2_LED_Z<br />
PB3_LED_Z<br />
PB4_LED_Z<br />
PB5_LED_Z<br />
PB6_LED_Z<br />
PB7_LED_Z<br />
78<br />
67<br />
94<br />
89<br />
90<br />
96<br />
85<br />
PB1_LED_Z<br />
PB2_LED_Z<br />
PB3_LED_Z<br />
PB4_LED_Z<br />
PB5_LED_Z<br />
PB6_LED_Z<br />
PB7_LED_Z<br />
AMBER<br />
D3<br />
AMBER<br />
D5<br />
AMBER<br />
D7<br />
D2 130 5%<br />
AMBER<br />
R34<br />
D4 130 5%<br />
AMBER<br />
R38<br />
D6 130 5%<br />
AMBER<br />
R40<br />
R32<br />
130 5%<br />
R36<br />
130 5%<br />
R39<br />
130 5%<br />
VCC3V3<br />
C<br />
AMBER<br />
D8 130 5% R41<br />
XC95144XL_TQ100<br />
PB_CLOCK<br />
65<br />
PB_CLOCK<br />
PB8_LED_Z<br />
81 PB8_LED_Z<br />
AMBER<br />
PB_DATA<br />
R42<br />
63<br />
PB_DATA<br />
PB9_LED_Z<br />
79 PB9_LED_Z<br />
D9<br />
R43 130 5%<br />
VCC3V3<br />
R44<br />
27.4 1%<br />
AMBER<br />
D10 130 5% R45<br />
B<br />
L3<br />
FERRITE BEAD SM<br />
CTCB1210-600-S<br />
EXTEND_DCM_RESET<br />
27.4 1%<br />
70<br />
EXTEND_DCM_RESET PB10_LED_Z<br />
PB11_LED_Z<br />
77<br />
76<br />
PB10_LED_Z<br />
PB11_LED_Z<br />
D11<br />
AMBER<br />
R47<br />
130 5%<br />
B<br />
RED<br />
D12 130 5% R48<br />
FPGA_DONE<br />
27<br />
FPGA_DONE FPGA_DONE_LED_Z<br />
16 FPGA_DONE_LED_Z<br />
1<br />
Y2<br />
ENABLE VCC<br />
6<br />
VCC3V3<br />
HC3_CFGPROGZ<br />
52<br />
PROG_FPGA_Z<br />
FPGA_PROG_LED_Z<br />
11 FPGA_PROG_LED_Z<br />
D13<br />
RED<br />
GREEN<br />
R49<br />
130 5%<br />
C38<br />
0.1uF<br />
2<br />
3<br />
NC<br />
GND<br />
NC<br />
OUT<br />
5<br />
4<br />
27.000MHZ 50PPM<br />
R46<br />
CLOCK27MHZ<br />
R227<br />
3K0 5% R51<br />
R50<br />
3K0 5% R52<br />
VCC_CORE<br />
3V3GOOD<br />
56<br />
59<br />
VCC_CORE<br />
3V3GOOD<br />
2V5_OK_Z<br />
3V5_OK_Z<br />
60<br />
58<br />
2V5_OK_Z<br />
3V3_OK_Z<br />
130 5%<br />
49.9 1%<br />
J10<br />
3K0 5%<br />
3K0 5%<br />
1V5GOOD<br />
61<br />
1V5GOOD<br />
1V5_OK_Z<br />
71<br />
1V5_OK_Z<br />
CPLD<br />
CONFIG<br />
JTAG<br />
PORT<br />
VIDEO_DECODER_RESET_Z<br />
HC3_RESET_Z<br />
ENET_RESET_Z<br />
JTAG_PROG_CON<br />
29<br />
34<br />
20<br />
U1A<br />
VIDEO_DECODER_RESET_Z<br />
HC3_RESET_Z<br />
ENET_RESET_Z<br />
A<br />
1<br />
2<br />
VCC3V3<br />
A<br />
3<br />
4<br />
5<br />
6<br />
PROG_CPLD_TDO<br />
PROG_CPLD_TDI<br />
PROG_CPLD_TCK<br />
PROG_CPLD_TMS<br />
XILINX INC.<br />
Title<br />
2100 Logic Drive San Jose California USA 95124<br />
3<br />
R226<br />
3K0 5%<br />
VCC3V3<br />
2<br />
2<br />
CPLD<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
3 of 35<br />
1
5<br />
5<br />
4<br />
VCC3V3 VCC3V3<br />
4<br />
3<br />
13<br />
66<br />
R53<br />
TIE<br />
TIE<br />
R54<br />
D D<br />
3K0 5%<br />
14<br />
TIE<br />
TIE<br />
68<br />
3K0 5%<br />
10<br />
TIE<br />
C C<br />
R56<br />
3K0 5%<br />
B B<br />
39<br />
TIE<br />
R58<br />
3K0 5%<br />
R55<br />
3K0 5%<br />
R57<br />
3K0 5%<br />
R59<br />
3K0 5%<br />
12<br />
15<br />
17<br />
3<br />
4<br />
9<br />
23<br />
28<br />
30<br />
32<br />
33<br />
91<br />
95<br />
42<br />
43<br />
46<br />
80<br />
82<br />
86<br />
54<br />
55<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
TIE<br />
5<br />
57<br />
98<br />
26<br />
38<br />
51<br />
88<br />
XC95144XL_TQ100<br />
XC95144XL_TQ100<br />
U1C<br />
VCC3V3<br />
A A<br />
R267<br />
3K0 5%<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
GND<br />
21<br />
VCCint<br />
GND<br />
31<br />
VCCint<br />
GND<br />
44<br />
VCCint<br />
GND<br />
62<br />
GND<br />
69<br />
GND<br />
75<br />
VCCio<br />
GND<br />
84<br />
VCCio<br />
GND<br />
100<br />
VCCio<br />
VCCio<br />
TIE<br />
64<br />
3<br />
CPLD CAPS<br />
C40<br />
0.1uF<br />
C41<br />
0.1uF<br />
C42<br />
0.1uF<br />
C43<br />
0.1uF<br />
2<br />
C44<br />
0.1uF<br />
2<br />
C45<br />
0.1uF<br />
C46<br />
0.1uF<br />
Title<br />
C47<br />
0.1uF<br />
C48<br />
0.1uF<br />
CPLD POWER<br />
C49<br />
0.1uF<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
4 of 35<br />
1<br />
+ C39<br />
47uF @ 16V
5<br />
5<br />
4<br />
4<br />
3<br />
R60<br />
J13<br />
49.9 1%<br />
R61<br />
ENET_GND<br />
D<br />
1<br />
3<br />
5<br />
7<br />
2<br />
4<br />
6<br />
8<br />
TP_TX_P<br />
TP_TX_N<br />
TP_RX_P<br />
TP_RX_N<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
TP_TX_P<br />
TP_TX_N<br />
TP_RX_P<br />
TP_RX_N<br />
1<br />
2<br />
3<br />
L4<br />
16<br />
15<br />
14<br />
C51<br />
270pF -5%<br />
49.9 1%<br />
RX_N<br />
24<br />
C52<br />
RX_P<br />
23<br />
270pF -5%<br />
0.01uF -10%<br />
TPIN<br />
TPIP<br />
U3<br />
TXD0<br />
TXD1<br />
TXD2<br />
TXD3<br />
TX_EN<br />
57<br />
58<br />
59<br />
60<br />
56<br />
TX_DATA0<br />
TX_DATA1<br />
TX_DATA2<br />
TX_DATA3<br />
TX_ENABLE<br />
D<br />
RJ45 ETHERNET NIC<br />
VIEW FROM TOP SIDE<br />
6<br />
7<br />
11<br />
10 ENET_TX_PWR<br />
TX_N<br />
20<br />
TPON<br />
TX_CLK<br />
TX_ER<br />
TXSLEW0<br />
55<br />
54<br />
5<br />
R62<br />
20.0 1% R63<br />
20.0 1%<br />
TX_CLOCK<br />
TX_ERROR<br />
ENET_SLEW0<br />
R70 R71 R72 R73<br />
C54<br />
1000pF @2KV<br />
C53<br />
1000pF @2KV<br />
TG110-S050N2 D14<br />
SPEED<br />
AMBER<br />
R67<br />
110 5%<br />
LED1_CONFIG1<br />
17<br />
38<br />
RBIAS<br />
LED_CFG1<br />
RXD0<br />
RXD1<br />
RXD2<br />
RXD3<br />
RX_DV<br />
48<br />
47<br />
46<br />
45<br />
49<br />
R64<br />
20.0 1%<br />
R66<br />
20.0 1%<br />
R65<br />
20.0 1%<br />
R68<br />
20.0 1%<br />
R69<br />
20.0 1%<br />
RX_DATA0<br />
RX_DATA1<br />
RX_DATA2<br />
RX_DATA3<br />
RX_DATA_VALID<br />
49.9 1% 49.9 1% 49.9 1% 49.9 1%<br />
D15<br />
R75<br />
RX_ER<br />
53<br />
R74<br />
20.0 1%<br />
RX_ERROR<br />
LINK UP<br />
LED2_CONFIG2<br />
37<br />
LED_CFG2 RX_CLK<br />
52 R76<br />
RX_CLOCK<br />
C<br />
ENET_VCC<br />
GREEN<br />
110 5%<br />
COL<br />
62 20.0 1%<br />
R77<br />
20.0 1%<br />
COLLISION_DETECTED<br />
C<br />
R78<br />
49.9 1%<br />
R79<br />
49.9 1%<br />
GND<br />
D16<br />
RX DATA<br />
R81<br />
LED3_CONFIG3<br />
36<br />
LED_CFG3<br />
CRS<br />
PAUSE<br />
63<br />
33<br />
R80<br />
20.0 1%<br />
CARRIER_SENSE<br />
PAUSE<br />
Y4<br />
ENET_XTAL_X1<br />
ENET_XTAL_X0<br />
GND<br />
C55<br />
1000pF @2KV<br />
GREEN<br />
110 5%<br />
DEFAULT TO AUTO<br />
NEGOTIATE 10/100Mbps<br />
FULL/HALF DUPLEX<br />
R82<br />
22K1 1%<br />
ENET_GND<br />
ENET_VCCD<br />
27<br />
28<br />
29<br />
30<br />
31<br />
34<br />
35<br />
TDI<br />
TDO<br />
TMS<br />
TCK<br />
TRST<br />
TEST0<br />
TEST1<br />
PWRDWN<br />
RESET<br />
MDIO<br />
MDC<br />
MDDIS<br />
MDINT<br />
ADDR0<br />
REFCLK_XI<br />
39<br />
4<br />
42<br />
43<br />
3<br />
64<br />
12<br />
1<br />
ENET_XTAL_X1<br />
ENET_RESET_Z<br />
MDIO<br />
MDC<br />
MDINIT_Z<br />
B C495<br />
18pF 25.000MHZ<br />
ENET_GND<br />
C496<br />
18pF<br />
C56 C57<br />
0.1uF 1000pF<br />
C58<br />
0.1uF<br />
ENET_VCCIO<br />
C59<br />
1000pF<br />
ENET_VCCD<br />
C60 C61<br />
0.1uF 1000pF<br />
ENET_GND<br />
L5<br />
ENET_VCCIO<br />
ENET_VCCA<br />
ENET_TX_PWR<br />
51<br />
8<br />
40<br />
21<br />
22<br />
44<br />
10<br />
9<br />
VCCD<br />
VCCIO<br />
VCCIO<br />
VCCA<br />
VCCA<br />
NC<br />
NC<br />
NC<br />
XO<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
2<br />
7<br />
11<br />
13<br />
14<br />
15<br />
16<br />
18<br />
25<br />
26<br />
32<br />
41<br />
50<br />
61<br />
ENET_XTAL_X0<br />
VCC3V3<br />
R85<br />
3K0 5%<br />
B<br />
MAC ADDRESS<br />
U4<br />
R84<br />
3K0 5%<br />
SILICON<br />
SERIAL<br />
NUMBER<br />
1<br />
GND<br />
2<br />
DATA<br />
DS2401<br />
VCC3V3<br />
ENET_VCC<br />
A FERRITE BEAD<br />
2961666671<br />
A<br />
+ C63<br />
10uF @ 16V<br />
+ C64<br />
1uF @ 20V<br />
C65<br />
0.1uF<br />
+ C66<br />
10uF @ 16V<br />
C67<br />
0.1uF<br />
FERRITE BEAD SM<br />
CTCB1210-600-S<br />
C68 C69 C70 C71<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
L8<br />
ENET_GND<br />
0.1uF 1000pF 0.1uF 1000pF<br />
Title<br />
GND<br />
L6<br />
FERRITE BEAD<br />
2961666671<br />
ENET_GND<br />
8<br />
ENET_VCC<br />
L7<br />
9<br />
FERRITE BEAD SM<br />
CTCB1210-600-S<br />
3<br />
C62<br />
0.01uF -10%<br />
ENET_GND<br />
TX_P<br />
ENET_VCCA<br />
ENET_GND<br />
19<br />
C50<br />
2<br />
TPOP<br />
10BASE-T 100BASE-TX<br />
ETHERNET<br />
TRANSCEIVER<br />
2<br />
LXT972<br />
TXSLEW1<br />
6<br />
ENET_GND<br />
ENET_VCC<br />
FAST ETHERNET INTERFACE<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
5 of 35<br />
1<br />
GND<br />
ENET_SLEW1<br />
SSN_DATA
5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
C<br />
VGA_OUT_GREEN0<br />
G21<br />
PAD16<br />
C<br />
VGA_OUT_RED7<br />
D24<br />
PAD17<br />
TX_DATA3<br />
TX_DATA2<br />
TX_DATA1<br />
TX_DATA0<br />
TX_ENABLE<br />
R235<br />
20.0 1%<br />
R237<br />
20.0 1%<br />
R239<br />
VGA_OUT_PIXEL_CLOCK<br />
VGA_OUT_GREEN7_YCrCb1<br />
VGA_OUT_GREEN6_YCrCb0<br />
CARRIER_SENSE<br />
COLLISION_DETECTED<br />
R236<br />
VGA_COMP_SYNCH<br />
VGA_OUT_BLANK_Z<br />
VGA_OUT_GREEN5<br />
VGA_OUT_GREEN4<br />
VGA_OUT_GREEN3<br />
VGA_OUT_GREEN2<br />
VGA_OUT_GREEN1<br />
20.0 1%<br />
R238<br />
VGA_OUT_RED6<br />
VGA_OUT_RED5<br />
VGA_OUT_RED4<br />
VGA_OUT_RED3<br />
VGA_OUT_RED2<br />
VGA_OUT_RED1<br />
VGA_OUT_RED0<br />
20.0 1%<br />
USER_LED0_Z<br />
VGA_HSYNCH<br />
VGA_VSYNCH<br />
PAL_NTSC_Z<br />
S_VIDEO_Z<br />
SSN_DATA<br />
USER_LED1_Z<br />
MDINIT_Z<br />
20.0 1%<br />
B TX_ERROR<br />
D21<br />
PAD35<br />
B<br />
RX_ERROR<br />
RX_DATA_VALID<br />
RX_DATA0<br />
RX_DATA1<br />
RX_DATA2<br />
RX_DATA3<br />
MDC<br />
MDIO<br />
PAUSE<br />
TX_CLOCK<br />
ENET_SLEW0<br />
RX_CLOCK<br />
ENET_SLEW1<br />
B27<br />
A27<br />
F24<br />
E24<br />
C26<br />
C25<br />
A26<br />
A25<br />
F23<br />
F22<br />
C24<br />
D25<br />
A24<br />
B25<br />
G22<br />
D23<br />
B23<br />
B24<br />
H21<br />
H20<br />
E22<br />
E23<br />
A22<br />
B22<br />
F21<br />
F20<br />
C23<br />
C22<br />
B20<br />
B21<br />
G20<br />
G19<br />
D22<br />
B17<br />
B16<br />
F17<br />
F16<br />
D16<br />
D17<br />
A17<br />
A16<br />
H16<br />
G16<br />
C17<br />
C16<br />
PAD01<br />
PAD02<br />
PAD03<br />
PAD04<br />
PAD05 VRP_0<br />
PAD06 VRN_0<br />
PAD07 VREF0<br />
PAD08<br />
PAD09<br />
PAD10<br />
PAD11<br />
PAD12<br />
PAD13<br />
PAD14<br />
PAD15<br />
PAD18 VREF0<br />
PAD19<br />
PAD20<br />
PAD21<br />
PAD22<br />
PAD23<br />
PAD24<br />
PAD25<br />
PAD26<br />
PAD27<br />
PAD28<br />
PAD29<br />
PAD30 VREF0<br />
PAD31<br />
PAD32<br />
PAD33<br />
PAD34<br />
PAD36<br />
PAD37 VREF0<br />
PAD38<br />
PAD39<br />
PAD40<br />
PAD41<br />
PAD42<br />
PAD43<br />
PAD44<br />
A A<br />
3<br />
BANK0<br />
PAD45 GCLK7P<br />
PAD46 GCLK6S<br />
PAD47 GCLK5P<br />
PAD48 GCLK4S<br />
U5A<br />
VCCO_0<br />
VCCO_0<br />
VCCO_0<br />
VCCO_0<br />
VCCO_0<br />
VCCO_0<br />
VCCO_0<br />
VCCO_0<br />
VCCO_0<br />
VCCO_0<br />
VCCO_0<br />
Title<br />
K20<br />
K19<br />
K18<br />
K17<br />
K16<br />
J21<br />
J20<br />
J19<br />
J18<br />
C18<br />
B26<br />
XILINX INC.<br />
2<br />
VCC3V3<br />
2100 Logic Drive San Jose California USA 95124<br />
FPGA BANK0 CONNECTIONS<br />
Size Document Number Rev<br />
0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 6 of 35<br />
2<br />
1<br />
1
5<br />
5<br />
RS232_TX_DATA<br />
RS232_RX_DATA<br />
4<br />
4<br />
3<br />
CHAN1_LINE_LOCK_CLOCK1<br />
C15<br />
PAD49 GCLK3P VCCO_1<br />
K15<br />
VCC3V3<br />
D CHAN1_LINE_LOCK_CLOCK2<br />
C14<br />
PAD50 GCLK2S VCCO_1<br />
K14<br />
D<br />
AC97_BIT_CLOCK<br />
F15<br />
PAD51 GCLK1P VCCO_1<br />
K13<br />
USER_INPUT1<br />
F14<br />
PAD52 GCLK0S VCCO_1<br />
K12<br />
CHAN1_VIDEO_DATA0<br />
B15<br />
PAD53<br />
VCCO_1<br />
K11<br />
CHAN1_VIDEO_DATA1<br />
B14<br />
PAD54 VREF1 VCCO_1<br />
J13<br />
CHAN1_VIDEO_DATA2<br />
D14<br />
PAD55<br />
VCCO_1<br />
J12<br />
CHAN1_VIDEO_DATA3<br />
D15<br />
PAD56<br />
VCCO_1<br />
J11<br />
CHAN1_VIDEO_DATA4<br />
G15<br />
PAD57<br />
VCCO_1<br />
J10<br />
CHAN1_VIDEO_DATA5<br />
H15<br />
PAD58<br />
VCCO_1<br />
C13<br />
C C<br />
RS232_CTS_OUT KBD_CLOCK<br />
F11<br />
PAD69<br />
RS232_DSR_OUT<br />
CHAN1_VIDEO_DATA6<br />
CHAN1_VIDEO_DATA7<br />
CHAN1_VIDEO_DATA8<br />
CHAN1_VIDEO_DATA9<br />
CHAN1_I2C_CLOCK<br />
CHAN1_I2C_DATA<br />
CHAN1_ISO<br />
USER_INPUT0<br />
MOUSE_CLOCK<br />
MOUSE_DATA<br />
KBD_DATA<br />
RS232_RTS_IN<br />
AC97_SDATA_IN<br />
AC97_SDATA_OUT<br />
AC97_SYNCH<br />
BEEP_TONE_IN<br />
MEMORY_BANK4_ADDR6<br />
MEMORY_BANK4_ADDR7<br />
MEMORY_BANK4_CEN_Z<br />
MEMORY_BANK4_WEND_Z<br />
MEMORY_BANK4_WENC_Z<br />
MEMORY_BANK4_WENB_Z<br />
MEMORY_BANK4_WENA_Z<br />
MEMORY_BANK4_CLK<br />
MEMORY_BANK4_WEN_Z<br />
MEMORY_BANK4_CLKEN_Z<br />
MEMORY_BANK4_OEN_Z<br />
MEMORY_BANK4_ADV_LDZ<br />
F9<br />
PAD87<br />
B<br />
MEMORY_BANK4_ADDR18<br />
G8<br />
PAD88<br />
B<br />
MEMORY_BANK4_ADDR17<br />
MEMORY_BANK4_ADDR8<br />
MEMORY_BANK4_ADDR9<br />
MEMORY_BANK4_DATA_B7<br />
MEMORY_BANK4_DATA_C0<br />
MEMORY_BANK4_DATA_B6<br />
MEMORY_BANK4_DATA_C1<br />
MEMORY_BANK4_DATA_B5<br />
A14<br />
A13<br />
E10<br />
E11<br />
H12<br />
H11<br />
D9<br />
D10<br />
C9<br />
C8<br />
F10<br />
B8<br />
B9<br />
E8<br />
E9<br />
G11<br />
H10<br />
B7<br />
A7<br />
D8<br />
E7<br />
G10<br />
G9<br />
A5<br />
A6<br />
C6<br />
C7<br />
B6<br />
C5<br />
D7<br />
D6<br />
F8<br />
F7<br />
B4<br />
A4<br />
PAD59<br />
A A<br />
3<br />
BANK1<br />
PAD60 VREF1<br />
PAD61<br />
PAD62<br />
PAD63<br />
PAD64<br />
PAD65<br />
PAD66<br />
PAD67 VREF1<br />
PAD68<br />
PAD70<br />
PAD71<br />
PAD72<br />
PAD73<br />
PAD74<br />
PAD75<br />
PAD76<br />
PAD77<br />
PAD78<br />
PAD79 VREF1<br />
PAD80<br />
PAD81<br />
PAD82<br />
PAD83<br />
PAD84<br />
PAD85<br />
PAD86<br />
PAD89<br />
PAD90 VREF1<br />
PAD91 VRP_1<br />
PAD92 VRN_1<br />
PAD93<br />
PAD94<br />
PAD95<br />
PAD96<br />
U5D<br />
VCCO_1<br />
B5<br />
Title<br />
XILINX INC.<br />
2<br />
2100 Logic Drive San Jose California USA 95124<br />
FPGA BANK1CONNECTIONS<br />
Size Document Number Rev<br />
0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 7 of 35<br />
2<br />
1<br />
1
5<br />
5<br />
4<br />
MEMORY_BANK4_DATA_C2<br />
MEMORY_BANK4_DATA_B4<br />
MEMORY_BANK4_DATA_C3<br />
4<br />
3<br />
MEMORY_BANK4_DATA_B3<br />
H8<br />
PAD100 VRN_2 VCCO_2<br />
N9<br />
D<br />
MEMORY_BANK4_DATA_C4<br />
D3<br />
PAD101<br />
VCCO_2<br />
N3<br />
D<br />
MEMORY_BANK4_DATA_B2<br />
MEMORY_BANK4_DATA_C5<br />
MEMORY_BANK4_DATA_B1<br />
MEMORY_BANK4_DATA_C6<br />
MEMORY_BANK4_DATA_B0<br />
MEMORY_BANK4_DATA_C7<br />
MEMORY_BANK4_DATA_A7<br />
MEMORY_BANK4_DATA_D0<br />
MEMORY_BANK4_DATA_A6<br />
MEMORY_BANK4_DATA_D1<br />
MEMORY_BANK4_DATA_A5<br />
MEMORY_BANK4_DATA_D2<br />
MEMORY_BANK4_DATA_A4<br />
MEMORY_BANK4_DATA_D3<br />
MEMORY_BANK4_DATA_A3<br />
MEMORY_BANK4_DATA_D4<br />
MEMORY_BANK4_DATA_A2<br />
C<br />
MEMORY_BANK4_DATA_D5<br />
G3<br />
PAD119<br />
C<br />
MEMORY_BANK4_DATA_A1<br />
F3<br />
PAD120<br />
MEMORY_BANK4_DATA_D6<br />
MEMORY_BANK4_DATA_A0<br />
MEMORY_BANK4_DATA_D7<br />
MEMORY_BANK4_ADDR16<br />
MEMORY_BANK4_ADDR15<br />
MEMORY_BANK4_ADDR14<br />
MEMORY_BANK4_ADDR13<br />
MEMORY_BANK4_ADDR12<br />
MEMORY_BANK4_ADDR11<br />
MEMORY_BANK4_ADDR10<br />
MEMORY_BANK4_ADDR0<br />
MEMORY_BANK4_ADDR1<br />
MEMORY_BANK4_ADDR2<br />
MEMORY_BANK4_ADDR3<br />
MEMORY_BANK4_ADDR4<br />
MEMORY_BANK4_ADDR5<br />
MEMORY_BANK3_ADDR6<br />
B MEMORY_BANK3_ADDR7<br />
K4<br />
PAD138 VREF2<br />
B<br />
MEMORY_BANK3_CEN_Z<br />
MEMORY_BANK3_WEND_Z<br />
MEMORY_BANK3_WENC_Z<br />
MEMORY_BANK3_WENB_Z<br />
MEMORY_BANK3_WENA_Z<br />
MEMORY_BANK3_CLK<br />
MEMORY_BANK3_WEN_Z<br />
MEMORY_BANK3_CLKEN_Z<br />
MEMORY_BANK3_OEN_Z<br />
MEMORY_BANK3_ADV_LDZ<br />
MEMORY_BANK3_ADDR18<br />
MEMORY_BANK3_ADDR17<br />
MEMORY_BANK3_ADDR8<br />
MEMORY_BANK3_ADDR9<br />
MEMORY_BANK3_DATA_B7<br />
MEMORY_BANK3_DATA_C0<br />
MEMORY_BANK3_DATA_B6<br />
MEMORY_BANK3_DATA_C1<br />
A A<br />
3<br />
B1<br />
H9<br />
E3<br />
D2<br />
C2<br />
G7<br />
H7<br />
F4<br />
E4<br />
E1<br />
D1<br />
G6<br />
H6<br />
F5<br />
G5<br />
G2<br />
F2<br />
J8<br />
J7<br />
G1<br />
F1<br />
K8<br />
L8<br />
G4<br />
H4<br />
J2<br />
H2<br />
J6<br />
K6<br />
J5<br />
H5<br />
J3<br />
H3<br />
K7<br />
L7<br />
J4<br />
K1<br />
J1<br />
L6<br />
M6<br />
L5<br />
K5<br />
R2<br />
P2<br />
P8<br />
R8<br />
P4<br />
R4<br />
R1<br />
T2<br />
R7<br />
R6<br />
R3<br />
P3<br />
BANK2<br />
C1<br />
PAD97 VCCO_2<br />
R10<br />
PAD98<br />
PAD99 VRP_2<br />
PAD102 VREF2<br />
PAD103<br />
PAD104<br />
PAD105<br />
PAD106<br />
PAD107<br />
PAD108<br />
PAD109<br />
PAD110<br />
PAD111<br />
PAD112<br />
PAD113<br />
PAD114 VREF2<br />
PAD115<br />
PAD116<br />
PAD117<br />
PAD118<br />
PAD121<br />
PAD122<br />
PAD123<br />
PAD124<br />
PAD125<br />
PAD126 VREF2<br />
PAD127<br />
PAD128<br />
PAD129<br />
PAD130<br />
PAD131<br />
PAD132<br />
PAD133<br />
PAD134<br />
PAD135<br />
PAD136<br />
PAD137<br />
PAD139<br />
PAD140<br />
PAD141<br />
PAD142<br />
PAD143<br />
PAD144<br />
PAD145<br />
PAD146<br />
PAD147<br />
PAD148<br />
PAD149<br />
PAD150 VREF2<br />
PAD151<br />
PAD152<br />
PAD153<br />
PAD154<br />
PAD155<br />
PAD156<br />
Title<br />
U5E<br />
XILINX INC.<br />
2<br />
VCCO_2<br />
VCCO_2<br />
VCCO_2<br />
VCCO_2<br />
VCCO_2<br />
VCCO_2<br />
VCCO_2<br />
VCCO_2<br />
P10<br />
N10<br />
M10<br />
M9<br />
L10<br />
L9<br />
K9<br />
E2<br />
VCC3V3<br />
2100 Logic Drive San Jose California USA 95124<br />
FPGA BANK2 CONNECTIONS<br />
Size Document Number Rev<br />
0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 8 of 35<br />
2<br />
1<br />
1
5<br />
5<br />
4<br />
4<br />
MEMORY_BANK3_DATA_B5<br />
MEMORY_BANK3_DATA_C2<br />
MEMORY_BANK3_DATA_B4<br />
MEMORY_BANK3_DATA_C3<br />
3<br />
D MEMORY_BANK3_DATA_B3<br />
T3<br />
PAD161<br />
VCCO_3<br />
W10<br />
D<br />
MEMORY_BANK3_DATA_C4<br />
MEMORY_BANK3_DATA_B2<br />
MEMORY_BANK3_DATA_C5<br />
MEMORY_BANK3_DATA_B1<br />
MEMORY_BANK3_DATA_C6<br />
MEMORY_BANK3_DATA_B0<br />
MEMORY_BANK3_DATA_C7<br />
MEMORY_BANK3_DATA_A7<br />
MEMORY_BANK3_DATA_D0<br />
MEMORY_BANK3_DATA_A6<br />
MEMORY_BANK3_DATA_D1<br />
MEMORY_BANK3_DATA_A5<br />
MEMORY_BANK3_DATA_D2<br />
MEMORY_BANK3_DATA_A4<br />
MEMORY_BANK3_DATA_D3<br />
MEMORY_BANK3_DATA_A3<br />
MEMORY_BANK3_DATA_D4<br />
MEMORY_BANK3_DATA_A2<br />
C C<br />
MEMORY_BANK3_DATA_D5<br />
AA7<br />
PAD180<br />
MEMORY_BANK3_DATA_A1<br />
MEMORY_BANK3_DATA_D6<br />
MEMORY_BANK3_DATA_A0<br />
MEMORY_BANK3_DATA_D7<br />
MEMORY_BANK3_ADDR16<br />
MEMORY_BANK3_ADDR15<br />
MEMORY_BANK3_ADDR14<br />
MEMORY_BANK3_ADDR13<br />
MEMORY_BANK3_ADDR12<br />
MEMORY_BANK3_ADDR11<br />
MEMORY_BANK3_ADDR10<br />
MEMORY_BANK3_ADDR0<br />
MEMORY_BANK3_ADDR1<br />
MEMORY_BANK3_ADDR2<br />
MEMORY_BANK3_ADDR3<br />
MEMORY_BANK3_ADDR4<br />
MEMORY_BANK3_ADDR5<br />
MPD0<br />
AE3<br />
PAD198<br />
B<br />
MPD1<br />
AD6<br />
PAD199 VREF3<br />
B<br />
MPD2<br />
MPD3<br />
MPD4<br />
MPD5<br />
MPD6<br />
MPD7<br />
MPD8<br />
MPD9<br />
MPD10<br />
MPD11<br />
MPD12<br />
MPD13<br />
MPD14<br />
MPD15<br />
MPA0<br />
MPA1<br />
MPA2<br />
A A<br />
U5G<br />
3<br />
T6<br />
U1<br />
V1<br />
U3<br />
T8<br />
U8<br />
U2<br />
V2<br />
T4<br />
U4<br />
AA6<br />
Y6<br />
AA2<br />
AB2<br />
Y5<br />
AA5<br />
Y8<br />
AA8<br />
AC2<br />
AD2<br />
Y7<br />
AC6<br />
AB6<br />
AD1<br />
AE1<br />
AB3<br />
AC3<br />
AB7<br />
AC7<br />
AB4<br />
AC4<br />
AB5<br />
AC5<br />
AC8<br />
AB8<br />
AE2<br />
AF3<br />
AD3<br />
AD7<br />
AF1<br />
AG1<br />
AD4<br />
AE4<br />
AD8<br />
AE7<br />
AG2<br />
AH2<br />
AD5<br />
AE5<br />
AC9<br />
AD9<br />
AH1<br />
AJ1<br />
AF4<br />
AG3<br />
Title<br />
XILINX INC.<br />
2<br />
BANK3<br />
T7<br />
PAD157 VCCO_3<br />
AF2<br />
PAD158<br />
PAD159<br />
PAD160<br />
PAD162<br />
PAD163 VREF3<br />
PAD164<br />
PAD165<br />
PAD166<br />
PAD167<br />
PAD168<br />
PAD169<br />
PAD170<br />
PAD171<br />
PAD172<br />
PAD173<br />
PAD174<br />
PAD175 VREF3<br />
PAD176<br />
PAD177<br />
PAD178<br />
PAD179<br />
PAD181<br />
PAD182<br />
PAD183<br />
PAD184<br />
PAD185<br />
PAD186<br />
PAD187 VREF3<br />
PAD188<br />
PAD189<br />
PAD190<br />
PAD191<br />
PAD192<br />
PAD193<br />
PAD194<br />
PAD195<br />
PAD196<br />
PAD197<br />
PAD200<br />
PAD201<br />
PAD202<br />
PAD203<br />
PAD204<br />
PAD205<br />
PAD206<br />
PAD207<br />
PAD208<br />
PAD209<br />
PAD210<br />
PAD211 VREF3<br />
PAD212<br />
PAD213 VRP_3<br />
PAD214 VRN_3<br />
PAD215<br />
PAD216<br />
VCCO_3<br />
VCCO_3<br />
VCCO_3<br />
VCCO_3<br />
VCCO_3<br />
VCCO_3<br />
VCCO_3<br />
VCCO_3<br />
VCCO_3<br />
AA9<br />
Y10<br />
Y9<br />
W9<br />
V10<br />
V9<br />
V3<br />
U10<br />
T10<br />
2100 Logic Drive San Jose California USA 95124<br />
FPGA BANK3 CONNECTIONS<br />
Size Document Number Rev<br />
0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 9 of 35<br />
2<br />
1<br />
1<br />
VCC3V3
5<br />
5<br />
4<br />
4<br />
3<br />
3K0 5%<br />
D D<br />
PB_CLOCK<br />
HC3_CFGINIT<br />
R87<br />
20.0 1%<br />
R86<br />
MPA3<br />
MPA4<br />
MPA5<br />
MPA6<br />
MPCE_Z<br />
MPWE_Z<br />
MPOE_Z<br />
MPIRQ<br />
MPBRDY<br />
EXTEND_DCM_RESET<br />
PB_DATA<br />
STARTUP<br />
MEMORY_BANK2_ADDR5<br />
MEMORY_BANK2_ADDR4<br />
MEMORY_BANK2_ADDR3<br />
VCC3V3<br />
C<br />
MEMORY_BANK2_ADDR2<br />
AF8<br />
PAD234 VREF4<br />
C<br />
MEMORY_BANK2_ADDR1<br />
AK7<br />
PAD235<br />
MEMORY_BANK2_ADDR0<br />
AJ6<br />
PAD236<br />
MEMORY_BANK2_ADDR10<br />
AD10<br />
PAD237<br />
MEMORY_BANK2_ADDR11<br />
AD11<br />
PAD238<br />
MEMORY_BANK2_ADDR12<br />
AG8<br />
PAD239<br />
MEMORY_BANK2_ADDR13<br />
AG7<br />
PAD240<br />
MEMORY_BANK2_ADDR14<br />
AJ8<br />
PAD241<br />
MEMORY_BANK2_ADDR15<br />
AJ7<br />
PAD242<br />
MEMORY_BANK2_ADDR16<br />
AE11<br />
PAD243<br />
MEMORY_BANK2_DATA_D7<br />
AE12<br />
PAD244<br />
MEMORY_BANK2_DATA_A0<br />
AG9<br />
PAD245<br />
MEMORY_BANK2_DATA_D6<br />
AG10<br />
PAD246 VREF4<br />
MEMORY_BANK2_DATA_A1<br />
AK9<br />
PAD246<br />
MEMORY_BANK2_DATA_D5<br />
AJ9<br />
PAD248<br />
MEMORY_BANK2_DATA_A2<br />
AH8<br />
PAD249<br />
MEMORY_BANK2_DATA_D4<br />
AH9<br />
PAD250<br />
MEMORY_BANK2_DATA_A3<br />
AF11<br />
PAD251<br />
MEMORY_BANK2_DATA_D3<br />
AF10<br />
PAD252<br />
B MEMORY_BANK2_DATA_A4<br />
AJ14<br />
PAD253 VREF4<br />
B<br />
MEMORY_BANK2_DATA_D2<br />
AJ15<br />
PAD254<br />
MEMORY_BANK2_DATA_A5<br />
AC14<br />
PAD255<br />
MEMORY_BANK2_DATA_D1<br />
AC15<br />
PAD256<br />
MEMORY_BANK2_DATA_A6<br />
AG15<br />
PAD257<br />
MEMORY_BANK2_DATA_D0<br />
AG14<br />
PAD258<br />
MEMORY_BANK2_DATA_A7<br />
AK14<br />
PAD259 VREF4<br />
MEMORY_BANK2_DATA_C7<br />
AK15<br />
PAD260<br />
MEMORY_BANK2_DATA_B0<br />
AD15<br />
PAD261 GCLK3S<br />
R88<br />
MEMORY_CLOCK_FB_IN<br />
AE15<br />
PAD262 GCLK2P<br />
MEMORY_CLOCK_FB_OUT<br />
AH14<br />
PAD263 GCLK1S<br />
20.0 1%<br />
MASTER_CLOCK<br />
AH15<br />
PAD264 GCLK0P<br />
A A<br />
3<br />
Title<br />
BANK4<br />
AK2<br />
PAD217 DOUT_BUSY VCCO_4<br />
AJ5<br />
AJ3<br />
PAD218 INIT<br />
VCCO_4<br />
AH13<br />
AE8<br />
PAD219 D0_DIN<br />
VCCO_4<br />
AB13<br />
AF9<br />
PAD220 D1<br />
VCCO_4<br />
AB12<br />
AH5<br />
PAD221VRP4D2 VCCO_4<br />
AB11<br />
AH6<br />
PAD222 VRN4 D3 VCCO_4<br />
AB10<br />
AJ4<br />
PAD223 VREF4<br />
VCCO_4<br />
AA15<br />
AK4<br />
PAD2245<br />
VCCO_4<br />
AA14<br />
AC10<br />
PAD225 VRP4_ALT VCCO_4<br />
AA13<br />
AC11<br />
PAD226 VRN4_ALT VCCO_4<br />
AA12<br />
AH7<br />
PAD227<br />
VCCO_4<br />
AA11<br />
AG6<br />
PAD228<br />
AK6<br />
PAD229<br />
AK5<br />
PAD230<br />
AE9<br />
PAD231<br />
AE10<br />
PAD232<br />
AF7<br />
PAD233<br />
U5I<br />
XILINX INC.<br />
2<br />
2100 Logic Drive San Jose California USA 95124<br />
FPGA BANK4 CONNECTIONS<br />
Size Document Number Rev<br />
0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 10 of 35<br />
2<br />
1<br />
1<br />
VCC3V3
5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
MEMORY_BANK2_DATA_C6<br />
MEMORY_BANK2_DATA_B1<br />
MEMORY_BANK2_DATA_C5<br />
ALTERNATE_CLOCK<br />
MEMORY_BANK2_DATA_B2<br />
MEMORY_BANK2_DATA_B5<br />
MEMORY_BANK2_DATA_C1<br />
MEMORY_BANK2_DATA_B6<br />
MEMORY_BANK2_DATA_C0<br />
MEMORY_BANK2_ADDR9<br />
C<br />
MEMORY_BANK2_ADDR8<br />
AG22<br />
PAD281<br />
C<br />
MEMORY_BANK2_ADDR17<br />
AG21<br />
PAD282<br />
MEMORY_BANK2_ADV_LDZ<br />
MEMORY_BANK2_OEN_Z<br />
MEMORY_BANK2_WEN_Z<br />
MEMORY_BANK2_WENA_Z<br />
MEMORY_BANK2_WENC_Z<br />
MEMORY_BANK2_CEN_Z<br />
MEMORY_BANK2_ADDR7<br />
MEMORY_BANK2_ADDR6<br />
MEMORY_BANK1_ADDR5<br />
MEMORY_BANK1_ADDR3<br />
B MEMORY_BANK1_ADDR1<br />
AJ24<br />
PAD300<br />
B<br />
VCC3V3<br />
L35<br />
FERRITE BEAD SM<br />
CTCB1210-600-S<br />
1<br />
Y3<br />
ENABLE<br />
VCC<br />
MEMORY_BANK2_DATA_C4<br />
MEMORY_BANK2_DATA_B3<br />
MEMORY_BANK2_DATA_C3<br />
MEMORY_BANK2_DATA_B4<br />
MEMORY_BANK2_DATA_C2<br />
MEMORY_BANK2_DATA_B7<br />
MEMORY_BANK2_ADDR18<br />
MEMORY_BANK2_CLKEN_Z<br />
MEMORY_BANK2_CLK<br />
MEMORY_BANK2_WENB_Z<br />
MEMORY_BANK2_WEND_Z<br />
MEMORY_BANK1_ADDR4<br />
MEMORY_BANK1_ADDR2<br />
MEMORY_BANK1_ADDR0<br />
MEMORY_BANK1_ADDR10<br />
MEMORY_BANK1_ADDR11<br />
MEMORY_BANK1_ADDR12<br />
MEMORY_BANK1_ADDR13<br />
MEMORY_BANK1_ADDR14<br />
MEMORY_BANK1_ADDR15<br />
MEMORY_BANK1_ADDR16<br />
MEMORY_BANK1_DATA_D7<br />
MEMORY_BANK1_DATA_A0<br />
MEMORY_BANK1_DATA_D6<br />
MEMORY_BANK1_DATA_A1<br />
C72<br />
2<br />
NC NC<br />
5<br />
R89<br />
A<br />
0.1uF<br />
3<br />
GND OUT<br />
4<br />
ALTERNATE_CLOCK<br />
A<br />
50.000MHZ 50PPM<br />
6<br />
49.9 1%<br />
AH17<br />
AE16<br />
AD16<br />
AJ16<br />
AJ17<br />
AG17<br />
AG16<br />
AC16<br />
AC17<br />
AK17<br />
AK18<br />
AF21<br />
AF20<br />
AH22<br />
AH23<br />
AF22<br />
AF23<br />
AE19<br />
AE20<br />
AJ23<br />
AJ22<br />
AF24<br />
AG23<br />
AD20<br />
AD21<br />
AK25<br />
AK24<br />
AH24<br />
AH25<br />
AE21<br />
AD22<br />
AJ25<br />
AG25<br />
AG24<br />
AC20<br />
AC21<br />
AK26<br />
AK27<br />
AH26<br />
AJ27<br />
AE22<br />
AE23<br />
AJ28<br />
AK29<br />
3<br />
BANK5<br />
AH16<br />
PAD265 GCLK7S VCCO_5<br />
AJ26<br />
PAD266 GCLK6P<br />
PAD267 GCLK5S<br />
PAD268 GCLK4P<br />
PAD269<br />
PAD270 VREF5<br />
PAD271<br />
PAD272<br />
PAD273<br />
PAD274<br />
PAD275<br />
PAD276 VREF5<br />
PAD277<br />
PAD278<br />
PAD279<br />
PAD280<br />
PAD283 VREF5<br />
PAD284<br />
PAD285<br />
PAD286<br />
PAD287<br />
PAD288<br />
PAD289<br />
PAD290<br />
PAD291<br />
PAD292<br />
PAD293<br />
PAD294<br />
PAD295 VREF5<br />
PAD296<br />
PAD297<br />
PAD298<br />
PAD299<br />
PAD301<br />
PAD302<br />
PAD303 VRP5_ALT<br />
PAD304 VRN5_ALT<br />
PAD305<br />
PAD306 VREF5<br />
PAD307D4VRP5<br />
PAD308D5VRN5<br />
PAD309 D6<br />
PAD310 D7<br />
PAD311 RDWR_Z<br />
PAD312 CS_Z<br />
U5K<br />
Title<br />
VCCO_5<br />
VCCO_5<br />
VCCO_5<br />
VCCO_5<br />
VCCO_5<br />
VCCO_5<br />
VCCO_5<br />
VCCO_5<br />
VCCO_5<br />
VCCO_5<br />
XILINX INC.<br />
2<br />
AH18<br />
AB21<br />
AB20<br />
AB19<br />
AB18<br />
AA20<br />
AA19<br />
AA18<br />
AA17<br />
AA16<br />
VCC3V3<br />
2100 Logic Drive San Jose California USA 95124<br />
FPGA BANK5 CONNECTIONS<br />
Size Document Number Rev<br />
0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 11 of 35<br />
2<br />
1<br />
1
5<br />
5<br />
4<br />
MEMORY_BANK1_DATA_D5<br />
MEMORY_BANK1_DATA_A2<br />
MEMORY_BANK1_DATA_D4<br />
MEMORY_BANK1_DATA_A3<br />
4<br />
3<br />
D MEMORY_BANK1_DATA_D3<br />
AJ30<br />
PAD317<br />
VCCO_6<br />
W22<br />
D<br />
MEMORY_BANK1_DATA_A4<br />
MEMORY_BANK1_DATA_D2<br />
MEMORY_BANK1_DATA_A5<br />
MEMORY_BANK1_DATA_D1<br />
MEMORY_BANK1_DATA_A6<br />
MEMORY_BANK1_DATA_D0<br />
MEMORY_BANK1_DATA_A7<br />
MEMORY_BANK1_DATA_C7<br />
MEMORY_BANK1_DATA_B0<br />
MEMORY_BANK1_DATA_C6<br />
MEMORY_BANK1_DATA_B1<br />
MEMORY_BANK1_DATA_C5<br />
MEMORY_BANK1_DATA_B2<br />
MEMORY_BANK1_DATA_C4<br />
MEMORY_BANK1_DATA_B3<br />
MEMORY_BANK1_DATA_C3<br />
MEMORY_BANK1_DATA_B4<br />
MEMORY_BANK1_DATA_C2<br />
C C<br />
MEMORY_BANK1_DATA_B5<br />
AE29<br />
PAD336<br />
MEMORY_BANK1_DATA_C1<br />
MEMORY_BANK1_DATA_B6<br />
MEMORY_BANK1_DATA_C0<br />
MEMORY_BANK1_DATA_B7<br />
MEMORY_BANK1_ADDR9<br />
MEMORY_BANK1_ADDR8<br />
MEMORY_BANK1_ADDR17<br />
MEMORY_BANK1_ADDR18<br />
MEMORY_BANK1_ADV_LDZ<br />
MEMORY_BANK1_OEN_Z<br />
MEMORY_BANK1_CLKEN_Z<br />
MEMORY_BANK1_WEN_Z<br />
MEMORY_BANK1_CLK<br />
MEMORY_BANK1_WENA_Z<br />
MEMORY_BANK1_WENB_Z<br />
MEMORY_BANK1_WENC_Z<br />
MEMORY_BANK1_WEND_Z<br />
MEMORY_BANK1_CEN_Z<br />
AB30<br />
PAD354 VREF6<br />
B<br />
MEMORY_BANK1_ADDR7<br />
Y25<br />
PAD355<br />
B<br />
MEMORY_BANK1_ADDR6<br />
MEMORY_BANK0_ADDR5<br />
MEMORY_BANK0_ADDR4<br />
MEMORY_BANK0_ADDR3<br />
MEMORY_BANK0_ADDR2<br />
MEMORY_BANK0_ADDR1<br />
MEMORY_BANK0_ADDR0<br />
MEMORY_BANK0_ADDR10<br />
MEMORY_BANK0_ADDR11<br />
MEMORY_BANK0_ADDR12<br />
MEMORY_BANK0_ADDR13<br />
MEMORY_BANK0_ADDR14<br />
MEMORY_BANK0_ADDR15<br />
MEMORY_BANK0_ADDR16<br />
MEMORY_BANK0_DATA_D7<br />
MEMORY_BANK0_DATA_A0<br />
MEMORY_BANK0_DATA_D6<br />
AC22<br />
AB23<br />
AG28<br />
AF28<br />
AH30<br />
AD23<br />
AC23<br />
AF27<br />
AE27<br />
AG29<br />
AH29<br />
AE24<br />
AD24<br />
AE26<br />
AD26<br />
AG30<br />
AF30<br />
AD25<br />
AC25<br />
AE28<br />
AD28<br />
AD29<br />
AC24<br />
AB24<br />
AD27<br />
AC27<br />
AC26<br />
AB26<br />
AA23<br />
Y23<br />
AC28<br />
AB28<br />
AD30<br />
AE30<br />
AB25<br />
AA25<br />
AA24<br />
Y24<br />
AC29<br />
W25<br />
AB27<br />
AA27<br />
AA29<br />
AB29<br />
U23<br />
T23<br />
U27<br />
T27<br />
V29<br />
U29<br />
T24<br />
T25<br />
U28<br />
T28<br />
T30<br />
U30<br />
A A<br />
U5N<br />
3<br />
PAD313<br />
PAD314<br />
BANK6<br />
PAD315 VRN6<br />
PAD316 VRP6<br />
PAD318 VREF6<br />
PAD319<br />
PAD320<br />
PAD321<br />
PAD322<br />
PAD323<br />
PAD324<br />
PAD325<br />
PAD326<br />
PAD327<br />
PAD328<br />
PAD329<br />
PAD330 VREF6<br />
PAD331<br />
PAD332<br />
PAD333<br />
PAD334<br />
PAD335<br />
PAD337<br />
PAD338<br />
PAD339<br />
PAD340<br />
PAD341<br />
PAD342 VREF6<br />
PAD343<br />
PAD344<br />
PAD345<br />
PAD346<br />
PAD347<br />
PAD348<br />
PAD349<br />
PAD350<br />
PAD351<br />
PAD352<br />
PAD353<br />
PAD356<br />
PAD357<br />
PAD358<br />
PAD359<br />
PAD360<br />
PAD361<br />
PAD362<br />
PAD363<br />
PAD364<br />
PAD365<br />
PAD366 VREF6<br />
PAD367<br />
PAD368<br />
PAD369<br />
PAD370<br />
PAD371<br />
PAD372<br />
VCCO_6<br />
VCCO_6<br />
VCCO_6<br />
VCCO_6<br />
VCCO_6<br />
VCCO_6<br />
VCCO_6<br />
VCCO_6<br />
VCCO_6<br />
VCCO_6<br />
Title<br />
AF29<br />
AA22<br />
Y22<br />
Y21<br />
W21<br />
V28<br />
V22<br />
V21<br />
U21<br />
T21<br />
XILINX INC.<br />
2<br />
VCC3V3<br />
2100 Logic Drive San Jose California USA 95124<br />
FPGA BANK6 CONNECTIONS<br />
Size Document Number Rev<br />
0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 12 of 35<br />
2<br />
1<br />
1
5<br />
5<br />
4<br />
MEMORY_BANK0_DATA_A1<br />
MEMORY_BANK0_DATA_D5<br />
MEMORY_BANK0_DATA_A2<br />
MEMORY_BANK0_DATA_D4<br />
MEMORY_BANK0_DATA_A3<br />
4<br />
3<br />
MEMORY_BANK0_DATA_D3<br />
T29<br />
PAD378 VCCO_7<br />
M22<br />
D<br />
MEMORY_BANK0_DATA_A4<br />
R27<br />
PAD379 VREF7 VCCO_7<br />
M21<br />
D<br />
MEMORY_BANK0_DATA_D2<br />
MEMORY_BANK0_DATA_A5<br />
MEMORY_BANK0_DATA_D1<br />
MEMORY_BANK0_DATA_A6<br />
MEMORY_BANK0_DATA_D0<br />
MEMORY_BANK0_DATA_A7<br />
MEMORY_BANK0_DATA_C7<br />
MEMORY_BANK0_DATA_B0<br />
MEMORY_BANK0_DATA_C6<br />
MEMORY_BANK0_DATA_B1<br />
MEMORY_BANK0_DATA_C5<br />
MEMORY_BANK0_DATA_B2<br />
MEMORY_BANK0_DATA_C4<br />
MEMORY_BANK0_DATA_B3<br />
MEMORY_BANK0_DATA_C3<br />
MEMORY_BANK0_DATA_B4<br />
MEMORY_BANK0_DATA_C2<br />
C<br />
MEMORY_BANK0_DATA_B5<br />
H26<br />
PAD397<br />
C<br />
MEMORY_BANK0_DATA_C1<br />
J26<br />
PAD398<br />
MEMORY_BANK0_DATA_B6<br />
MEMORY_BANK0_DATA_C0<br />
MEMORY_BANK0_DATA_B7<br />
MEMORY_BANK0_ADDR9<br />
MEMORY_BANK0_ADDR8<br />
MEMORY_BANK0_ADDR17<br />
MEMORY_BANK0_ADDR18<br />
MEMORY_BANK0_ADV_LDZ<br />
MEMORY_BANK0_OEN_Z<br />
MEMORY_BANK0_CLKEN_Z<br />
MEMORY_BANK0_WEN_Z<br />
MEMORY_BANK0_CLK<br />
MEMORY_BANK0_WENA_Z<br />
MEMORY_BANK0_WENB_Z<br />
MEMORY_BANK0_WENC_Z<br />
MEMORY_BANK0_WEND_Z<br />
MEMORY_BANK0_CEN_Z<br />
B MEMORY_BANK0_ADDR7<br />
G25<br />
PAD416<br />
B<br />
MEMORY_BANK0_ADDR6<br />
TV_OUT_PAL_NTSCZ<br />
TV_OUT_SUB_CARRIER_RESET<br />
VIDEO_ENCODER_DATA<br />
VIDEO_ENCODER_SCLK<br />
TV_OUT_BLANKZ<br />
TV_OUT_VSYNCHZ<br />
TV_OUT_HSYNCZ<br />
VGA_OUT_BLUE7_YCbCr9<br />
VGA_OUT_BLUE6_YCrCb8<br />
VGA_OUT_BLUE5_YCrCb7<br />
VGA_OUT_BLUE4_YCrCb6<br />
VGA_OUT_BLUE3_YCrCb5<br />
VGA_OUT_BLUE2_YCrCb4<br />
VGA_OUT_BLUE1_YCrCb3<br />
VGA_OUT_BLUE0_YCrCb2<br />
R28<br />
R25<br />
R24<br />
R29<br />
P27<br />
R23<br />
P23<br />
N30<br />
P30<br />
K26<br />
L26<br />
M25<br />
L25<br />
J29<br />
K29<br />
K27<br />
J27<br />
L24<br />
K24<br />
H27<br />
J28<br />
K25<br />
J25<br />
H28<br />
H29<br />
G28<br />
F28<br />
L23<br />
K23<br />
F30<br />
G30<br />
F26<br />
G27<br />
J24<br />
H24<br />
F29<br />
G29<br />
G26<br />
H25<br />
G24<br />
D30<br />
E30<br />
E27<br />
F27<br />
J23<br />
H22<br />
C29<br />
D29<br />
E28<br />
D28<br />
H23<br />
G23<br />
B30<br />
C30<br />
U5P<br />
A A<br />
3<br />
BANK7<br />
P28<br />
PAD373 VCCO_7<br />
R21<br />
PAD374<br />
PAD375<br />
PAD376<br />
PAD377<br />
PAD380<br />
PAD381<br />
PAD382<br />
PAD383<br />
PAD384<br />
PAD385<br />
PAD386<br />
PAD387<br />
PAD388<br />
PAD389<br />
PAD390<br />
PAD391 VREF7<br />
PAD392<br />
PAD393<br />
PAD394<br />
PAD395<br />
PAD396<br />
PAD399<br />
PAD400<br />
PAD401<br />
PAD402<br />
PAD403 VREF7<br />
PAD404<br />
PAD405<br />
PAD406<br />
PAD407<br />
PAD408<br />
PAD409<br />
PAD410<br />
PAD411<br />
PAD412<br />
PAD413<br />
PAD414<br />
PAD415 VREF7<br />
PAD417<br />
PAD418<br />
PAD419<br />
PAD420<br />
PAD421<br />
PAD422<br />
PAD423<br />
PAD424<br />
PAD425<br />
PAD426<br />
PAD427 VREF7<br />
PAD428<br />
PAD429 VRN7<br />
PAD430 VRP7<br />
PAD431<br />
PAD432<br />
VCCO_7<br />
VCCO_7<br />
VCCO_7<br />
VCCO_7<br />
VCCO_7<br />
VCCO_7<br />
VCCO_7<br />
VCCO_7<br />
Title<br />
P21<br />
N28<br />
N22<br />
N21<br />
L22<br />
L21<br />
K22<br />
E29<br />
XILINX INC.<br />
2<br />
VCC3V3<br />
2100 Logic Drive San Jose California USA 95124<br />
FPGA BANK 7 CONNECTIONS<br />
Size Document Number Rev<br />
0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 13 of 35<br />
2<br />
1<br />
1
5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
FPGA_DONE<br />
VCC3V3<br />
HC3_CFGTDI<br />
HC3_CFGTMS<br />
HC3_CFGTCK<br />
HC3_CFGTDO<br />
HC3_CFGPROGZ<br />
FPGA_TDO<br />
CCLK<br />
C<br />
M0<br />
AF25<br />
M0<br />
C<br />
M1<br />
AG26<br />
M1<br />
M2<br />
AH27<br />
M2<br />
HSWAP_EN<br />
C27<br />
HSWAP<br />
PWR_DN<br />
AH4<br />
POWERDOWN<br />
E6<br />
RSVD<br />
R92<br />
R93<br />
R94<br />
D26<br />
DXN<br />
3K0 5%<br />
3K0 5% 3K0 5%<br />
E25<br />
DXP<br />
FPGA MODE PINS<br />
SET FOR "JTAG"<br />
B B<br />
VCC3V3<br />
R90<br />
330 5%<br />
R91<br />
20.0 1%<br />
R95<br />
3K0 5%<br />
R96<br />
3K0 5%<br />
C4<br />
D5<br />
A29<br />
B3<br />
AF6<br />
AG5<br />
R97<br />
3K0 5%<br />
B28<br />
TMS<br />
TCK<br />
TDI<br />
TDO<br />
CCLK<br />
DONE<br />
PROG<br />
U5T<br />
A A<br />
3<br />
2<br />
2<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
Title<br />
FPGA CONFIGURATION<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
14 of 35<br />
1
5<br />
5<br />
U15<br />
4<br />
4<br />
3<br />
U14<br />
D GND<br />
GND<br />
AK8<br />
D<br />
U13<br />
U12<br />
U7<br />
T19<br />
T18<br />
T17<br />
T16<br />
T15<br />
T14<br />
T13<br />
T12<br />
R19<br />
R18<br />
R17<br />
R16<br />
R15<br />
R14<br />
R13<br />
C R12<br />
AA28<br />
C<br />
GND<br />
GND<br />
P24<br />
P19<br />
P18<br />
P17<br />
P16<br />
P15<br />
P14<br />
P13<br />
P12<br />
P7<br />
N19<br />
N18<br />
N17<br />
N16<br />
N15<br />
N14<br />
N13<br />
N12<br />
GND<br />
GND<br />
V13<br />
B<br />
M26<br />
GND<br />
GND<br />
V12<br />
B<br />
M19<br />
M18<br />
M17<br />
M16<br />
M15<br />
M14<br />
M13<br />
M12<br />
M5<br />
K28<br />
K3<br />
H30<br />
H1<br />
G17<br />
G14<br />
F25<br />
F6<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
E26<br />
GND GND<br />
E19<br />
A A<br />
U5R<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
AK23<br />
AJ29<br />
AJ2<br />
AH28<br />
AH21<br />
AH10<br />
AH3<br />
AG27<br />
AG4<br />
AF26<br />
AF19<br />
AF12<br />
AF5<br />
AE25<br />
AE6<br />
AD17<br />
AD14<br />
AC30<br />
AC1<br />
AA3<br />
W26<br />
W19<br />
W18<br />
W17<br />
W16<br />
W15<br />
W14<br />
W13<br />
W12<br />
W5<br />
V19<br />
V18<br />
V17<br />
V16<br />
V15<br />
V14<br />
U24<br />
U19<br />
U18<br />
U17<br />
U16<br />
E5<br />
D27<br />
D4<br />
C28<br />
C21<br />
C10<br />
C3<br />
B29<br />
B2<br />
A23<br />
A8<br />
E12<br />
3<br />
Title<br />
XILINX INC.<br />
2<br />
2100 Logic Drive San Jose California USA 95124<br />
FPGA GND CONNECTIONS<br />
Size Document Number Rev<br />
0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 15 of 35<br />
2<br />
1<br />
1
5<br />
5<br />
4<br />
4<br />
BATT1<br />
COIN CELL 2032<br />
3<br />
20mm COIN CELL HOLDER<br />
BT1<br />
BATTERY HOLDER<br />
VINT<br />
AB9<br />
VCC3V3<br />
AK28<br />
VAUX<br />
VINT<br />
AA21<br />
AK16<br />
VAUX<br />
D VINT<br />
AA10<br />
D<br />
AK3<br />
VAUX<br />
VINT<br />
Y20<br />
T1<br />
VAUX<br />
VINT<br />
Y19<br />
R30<br />
VAUX<br />
VINT<br />
Y18<br />
A28<br />
VAUX<br />
VINT<br />
Y17<br />
A15<br />
VAUX<br />
VINT<br />
Y16<br />
A3<br />
VAUX<br />
VINT<br />
Y15<br />
C R20<br />
C<br />
VINT<br />
VINT<br />
K21<br />
B<br />
VINT<br />
K10<br />
B<br />
A A<br />
3<br />
A2<br />
VBATT<br />
Title<br />
U5S<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
VINT<br />
XILINX INC.<br />
2<br />
AB22<br />
Y14<br />
Y13<br />
Y12<br />
Y11<br />
W20<br />
W11<br />
V20<br />
V11<br />
U20<br />
U11<br />
T20<br />
T11<br />
R11<br />
P20<br />
P11<br />
N20<br />
N11<br />
M20<br />
M11<br />
L20<br />
L19<br />
L18<br />
L17<br />
L16<br />
L15<br />
L14<br />
L13<br />
L12<br />
L11<br />
J22<br />
J9<br />
VCC1V5<br />
2100 Logic Drive San Jose California USA 95124<br />
FPGA POWER CONNECTIONS<br />
Size Document Number Rev<br />
0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 16 of 35<br />
2<br />
1<br />
1
5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
VCC3V3<br />
VCC3V3<br />
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF<br />
C C<br />
VCC3V3<br />
B B<br />
VCC3V3<br />
+ C73<br />
47uF @ 16V<br />
C82<br />
C104<br />
0.1uF<br />
C122<br />
0.1uF<br />
C83<br />
C105<br />
0.1uF<br />
C123<br />
0.1uF<br />
+ C74<br />
47uF @ 16V<br />
C84<br />
C106<br />
0.1uF<br />
C85<br />
C107<br />
0.1uF<br />
C124<br />
0.1uF<br />
+ C75<br />
47uF @ 16V<br />
C86<br />
C108<br />
0.1uF<br />
C125<br />
0.1uF<br />
C87<br />
C109<br />
0.1uF<br />
C126<br />
0.1uF<br />
+ C76<br />
47uF @ 16V<br />
C88<br />
C110<br />
0.1uF<br />
C127<br />
0.1uF<br />
C89<br />
C111<br />
0.1uF<br />
+ C77<br />
47uF @ 16V<br />
C128<br />
0.1uF<br />
C90<br />
C112<br />
0.1uF<br />
C129<br />
0.1uF<br />
+ C78<br />
47uF @ 16V<br />
C91<br />
C113<br />
0.1uF<br />
C92<br />
C130<br />
0.1uF<br />
A A<br />
3<br />
+ C79<br />
47uF @ 16V<br />
C93<br />
C131<br />
0.1uF<br />
C94<br />
+ C80<br />
47uF @ 16V<br />
C132<br />
0.1uF<br />
C95<br />
C133<br />
0.1uF<br />
C96<br />
+ C81<br />
470uF @ 10V<br />
C134<br />
0.1uF<br />
C97<br />
C135<br />
0.1uF<br />
2<br />
C98<br />
2<br />
C99<br />
C136<br />
0.1uF<br />
C100<br />
C137<br />
0.1uF<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
Title<br />
C101<br />
C102<br />
C103<br />
FPGA VCCO CAPS<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
17 of 35<br />
1
5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
VCC1V5<br />
VCC1V5<br />
C C<br />
C179 C180 C181 C182 C183 C184 C185 C186 C187 C188 C189 C190 C191 C192 C193 C194 C195 C196 C197 C198 C199 C200 C201 C202<br />
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF<br />
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF<br />
VCC1V5<br />
+ C170<br />
47uF @ 16V<br />
C203<br />
0.1uF<br />
C204<br />
0.1uF<br />
+ C171<br />
47uF @ 16V<br />
C205<br />
0.1uF<br />
+ C172<br />
47uF @ 16V<br />
C206<br />
0.1uF<br />
C207<br />
0.1uF<br />
+ C173<br />
47uF @ 16V<br />
C208<br />
0.1uF<br />
C209<br />
0.1uF<br />
+ C174<br />
47uF @ 16V<br />
C210<br />
0.1uF<br />
C211<br />
0.1uF<br />
+ C175<br />
47uF @ 16V<br />
C114<br />
0.1uF<br />
+ C176<br />
47uF @ 16V<br />
C115<br />
0.1uF<br />
C116<br />
0.1uF<br />
B B<br />
A A<br />
3<br />
+ C177<br />
47uF @ 16V<br />
C117<br />
0.1uF<br />
+ C178<br />
470uF @ 10V<br />
C118<br />
0.1uF<br />
C119<br />
0.1uF<br />
C120<br />
0.1uF<br />
2<br />
C121<br />
0.1uF<br />
2<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
Title<br />
FPGA VINT AND VAUX CAPS<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
18 of 35<br />
1
5<br />
4<br />
MEMORY_BANK0_ADDR[0..18]<br />
3<br />
MEMORY_BANK0_DATA_A[0..7],MEMORY_BANK0_DATA_B[0..7],MEMORY_BANK0_DATA_C[0..7],MEMORY_BANK0_DATA_D[0..7]<br />
MEMORY_BANK0_ADDR0<br />
MEMORY_BANK0_ADDR1<br />
MEMORY_BANK0_ADDR2<br />
U7<br />
D<br />
C<br />
MEMORY_BANK0_ADDR3<br />
MEMORY_BANK0_ADDR4<br />
MEMORY_BANK0_ADDR5<br />
MEMORY_BANK0_ADDR6<br />
MEMORY_BANK0_ADDR7<br />
MEMORY_BANK0_ADDR8<br />
MEMORY_BANK0_ADDR9<br />
MEMORY_BANK0_ADDR10<br />
MEMORY_BANK0_ADDR11<br />
MEMORY_BANK0_ADDR12<br />
MEMORY_BANK0_ADDR13<br />
MEMORY_BANK0_ADDR14<br />
MEMORY_BANK0_ADDR15<br />
MEMORY_BANK0_ADDR16<br />
MEMORY_BANK0_ADDR17<br />
MEMORY_BANK0_ADDR18<br />
MEMORY_BANK0_CLK<br />
MEMORY_BANK0_CLKEN_Z<br />
MEMORY_BANK0_WEN_Z<br />
MEMORY_BANK0_WENA_Z<br />
MEMORY_BANK0_WENB_Z<br />
MEMORY_BANK0_WENC_Z<br />
MEMORY_BANK0_WEND_Z<br />
MEMORY_BANK0_ADV_LDZ<br />
MEMORY_BANK0_OEN_Z<br />
MEMORY_BANK0_CEN_Z<br />
CLOCK to be routed on<br />
INTERNAL layer<br />
R132<br />
20.0 1%<br />
MEMORY_BANK0_ADDR0<br />
MEMORY_BANK0_ADDR1<br />
MEMORY_BANK0_ADDR2<br />
MEMORY_BANK0_ADDR3<br />
MEMORY_BANK0_ADDR4<br />
MEMORY_BANK0_ADDR5<br />
MEMORY_BANK0_ADDR6<br />
MEMORY_BANK0_ADDR7<br />
MEMORY_BANK0_ADDR8<br />
MEMORY_BANK0_ADDR9<br />
MEMORY_BANK0_ADDR10<br />
MEMORY_BANK0_ADDR11<br />
MEMORY_BANK0_ADDR12<br />
MEMORY_BANK0_ADDR13<br />
MEMORY_BANK0_ADDR14<br />
MEMORY_BANK0_ADDR15<br />
MEMORY_BANK0_ADDR16<br />
MEMORY_BANK0_ADDR17<br />
MEMORY_BANK0_ADDR18<br />
MEMORY_BANK0_CLK_R<br />
37<br />
36<br />
35<br />
34<br />
33<br />
32<br />
100<br />
99<br />
82<br />
81<br />
44<br />
45<br />
46<br />
47<br />
48<br />
49<br />
50<br />
83<br />
84<br />
89<br />
87<br />
88<br />
93<br />
94<br />
95<br />
96<br />
31<br />
64<br />
85<br />
86<br />
A0<br />
A1<br />
A2<br />
A3<br />
A4<br />
A5<br />
A6<br />
A7<br />
A8<br />
A9<br />
A10<br />
A11<br />
A12<br />
A13<br />
A14<br />
A15<br />
A16<br />
A17<br />
A18<br />
CLK<br />
CKE<br />
WE<br />
WEA<br />
WEB<br />
WEC<br />
WED<br />
LBO<br />
ZZ<br />
ADV_LD<br />
OE<br />
DQPC<br />
DQC0<br />
DQC1<br />
DQC2<br />
DQC3<br />
DQC4<br />
DQC5<br />
DQC6<br />
DQC7<br />
DQPD<br />
DQD0<br />
DQD1<br />
DQD2<br />
DQD3<br />
DQD4<br />
DQD5<br />
DQD6<br />
DQD7<br />
DQPA<br />
DQA0<br />
DQA1<br />
DQA2<br />
DQA3<br />
DQA4<br />
DQA5<br />
DQA6<br />
DQA7<br />
DQPB<br />
DQB0<br />
DQB1<br />
DQB2<br />
DQB3<br />
DQB4<br />
DQB5<br />
DQB6<br />
DQB7<br />
1<br />
2<br />
3<br />
6<br />
7<br />
8<br />
9<br />
12<br />
13<br />
30<br />
18<br />
19<br />
22<br />
23<br />
24<br />
25<br />
28<br />
29<br />
51<br />
52<br />
53<br />
56<br />
57<br />
58<br />
59<br />
62<br />
63<br />
80<br />
68<br />
69<br />
72<br />
73<br />
74<br />
75<br />
78<br />
79<br />
MEMORY_BANK0_DATA_C1<br />
MEMORY_BANK0_DATA_C0<br />
MEMORY_BANK0_DATA_C2<br />
MEMORY_BANK0_DATA_C3<br />
MEMORY_BANK0_DATA_C4<br />
MEMORY_BANK0_DATA_C5<br />
MEMORY_BANK0_DATA_C6<br />
MEMORY_BANK0_DATA_C7<br />
MEMORY_BANK0_DATA_D0<br />
MEMORY_BANK0_DATA_D1<br />
MEMORY_BANK0_DATA_D2<br />
MEMORY_BANK0_DATA_D3<br />
MEMORY_BANK0_DATA_D4<br />
MEMORY_BANK0_DATA_D5<br />
MEMORY_BANK0_DATA_D6<br />
MEMORY_BANK0_DATA_D7<br />
MEMORY_BANK0_DATA_A0<br />
MEMORY_BANK0_DATA_A1<br />
MEMORY_BANK0_DATA_A2<br />
MEMORY_BANK0_DATA_A3<br />
MEMORY_BANK0_DATA_A4<br />
MEMORY_BANK0_DATA_A5<br />
MEMORY_BANK0_DATA_A6<br />
MEMORY_BANK0_DATA_A7<br />
MEMORY_BANK0_DATA_B0<br />
MEMORY_BANK0_DATA_B1<br />
MEMORY_BANK0_DATA_B2<br />
MEMORY_BANK0_DATA_B3<br />
MEMORY_BANK0_DATA_B4<br />
MEMORY_BANK0_DATA_B5<br />
MEMORY_BANK0_DATA_B6<br />
MEMORY_BANK0_DATA_B7<br />
D<br />
C<br />
MEMORY_BANK0_DATA_A0<br />
MEMORY_BANK0_DATA_A1<br />
MEMORY_BANK0_DATA_A2<br />
MEMORY_BANK0_DATA_A3<br />
MEMORY_BANK0_DATA_A4<br />
VCC3V3<br />
R133<br />
3K0 5%<br />
98<br />
97<br />
92<br />
CS1<br />
CS2<br />
CS2<br />
NC<br />
NC<br />
NC<br />
NC<br />
38<br />
39<br />
42<br />
43<br />
R134<br />
3K0 5%<br />
B<br />
MEMORY_BANK0_DATA_A5<br />
MEMORY_BANK0_DATA_A6<br />
MEMORY_BANK0_DATA_A7<br />
MEMORY_BANK0_DATA_B0<br />
MEMORY_BANK0_DATA_B1<br />
MEMORY_BANK0_DATA_B2<br />
GND<br />
14<br />
15<br />
16<br />
41<br />
65<br />
66<br />
91<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
GND<br />
GND<br />
GND<br />
GND<br />
90<br />
67<br />
40<br />
17<br />
B<br />
MEMORY_BANK0_DATA_B3<br />
MEMORY_BANK0_DATA_B4<br />
MEMORY_BANK0_DATA_B5<br />
MEMORY_BANK0_DATA_B6<br />
MEMORY_BANK0_DATA_B7<br />
MEMORY_BANK0_DATA_C0<br />
MEMORY_BANK0_DATA_C1<br />
MEMORY_BANK0_DATA_C2<br />
MAX NET LENGTH 2.0 inches.<br />
CLOCK net must be the<br />
longest net.<br />
4<br />
11<br />
20<br />
27<br />
54<br />
61<br />
70<br />
77<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
76<br />
71<br />
60<br />
55<br />
26<br />
21<br />
10<br />
5<br />
MEMORY_BANK0_DATA_C3<br />
MEMORY_BANK0_DATA_C4<br />
512k X 36 ZBT SRAM<br />
MEMORY_BANK0_DATA_C5<br />
MEMORY_BANK0_DATA_C6<br />
MEMORY_BANK0_DATA_C7<br />
K7N163601M<br />
GND<br />
A<br />
MEMORY_BANK0_DATA_D0<br />
MEMORY_BANK0_DATA_D1<br />
A<br />
MEMORY_BANK0_DATA_D2<br />
MEMORY_BANK0_DATA_D3<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
MEMORY_BANK0_DATA_D4<br />
MEMORY_BANK0_DATA_D5<br />
MEMORY_BANK0_DATA_D6<br />
MEMORY_BANK0_DATA_D7<br />
Title<br />
Size<br />
MEMORY BANK0 512k x 32<br />
Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 19 of 35<br />
5<br />
4<br />
3<br />
2<br />
1<br />
2<br />
1
5<br />
4<br />
MEMORY_BANK1_ADDR[0..18]<br />
3<br />
MEMORY_BANK1_DATA_A[0..7],MEMORY_BANK1_DATA_B[0..7],MEMORY_BANK1_DATA_C[0..7],MEMORY_BANK1_DATA_D[0..7]<br />
MEMORY_BANK1_ADDR0<br />
MEMORY_BANK1_ADDR1<br />
MEMORY_BANK1_ADDR2<br />
U8<br />
D<br />
C<br />
MEMORY_BANK1_ADDR3<br />
MEMORY_BANK1_ADDR4<br />
MEMORY_BANK1_ADDR5<br />
MEMORY_BANK1_ADDR6<br />
MEMORY_BANK1_ADDR7<br />
MEMORY_BANK1_ADDR8<br />
MEMORY_BANK1_ADDR9<br />
MEMORY_BANK1_ADDR10<br />
MEMORY_BANK1_ADDR11<br />
MEMORY_BANK1_ADDR12<br />
MEMORY_BANK1_ADDR13<br />
MEMORY_BANK1_ADDR14<br />
MEMORY_BANK1_ADDR15<br />
MEMORY_BANK1_ADDR16<br />
MEMORY_BANK1_ADDR17<br />
MEMORY_BANK1_ADDR18<br />
MEMORY_BANK1_CLK<br />
MEMORY_BANK1_CLKEN_Z<br />
MEMORY_BANK1_WEN_Z<br />
MEMORY_BANK1_WENA_Z<br />
MEMORY_BANK1_WENB_Z<br />
MEMORY_BANK1_WENC_Z<br />
MEMORY_BANK1_WEND_Z<br />
MEMORY_BANK1_ADV_LDZ<br />
MEMORY_BANK1_OEN_Z<br />
MEMORY_BANK1_CEN_Z<br />
CLOCK to be routed on<br />
INTERNAL layer<br />
R135<br />
20.0 1%<br />
MEMORY_BANK1_ADDR0<br />
MEMORY_BANK1_ADDR1<br />
MEMORY_BANK1_ADDR2<br />
MEMORY_BANK1_ADDR3<br />
MEMORY_BANK1_ADDR4<br />
MEMORY_BANK1_ADDR5<br />
MEMORY_BANK1_ADDR6<br />
MEMORY_BANK1_ADDR7<br />
MEMORY_BANK1_ADDR8<br />
MEMORY_BANK1_ADDR9<br />
MEMORY_BANK1_ADDR10<br />
MEMORY_BANK1_ADDR11<br />
MEMORY_BANK1_ADDR12<br />
MEMORY_BANK1_ADDR13<br />
MEMORY_BANK1_ADDR14<br />
MEMORY_BANK1_ADDR15<br />
MEMORY_BANK1_ADDR16<br />
MEMORY_BANK1_ADDR17<br />
MEMORY_BANK1_ADDR18<br />
MEMORY_BANK1_CLK_R<br />
37<br />
36<br />
35<br />
34<br />
33<br />
32<br />
100<br />
99<br />
82<br />
81<br />
44<br />
45<br />
46<br />
47<br />
48<br />
49<br />
50<br />
83<br />
84<br />
89<br />
87<br />
88<br />
93<br />
94<br />
95<br />
96<br />
31<br />
64<br />
85<br />
86<br />
A0<br />
A1<br />
A2<br />
A3<br />
A4<br />
A5<br />
A6<br />
A7<br />
A8<br />
A9<br />
A10<br />
A11<br />
A12<br />
A13<br />
A14<br />
A15<br />
A16<br />
A17<br />
A18<br />
CLK<br />
CKE<br />
WE<br />
WEA<br />
WEB<br />
WEC<br />
WED<br />
LBO<br />
ZZ<br />
ADV_LD<br />
OE<br />
DQPC<br />
DQC0<br />
DQC1<br />
DQC2<br />
DQC3<br />
DQC4<br />
DQC5<br />
DQC6<br />
DQC7<br />
DQPD<br />
DQD0<br />
DQD1<br />
DQD2<br />
DQD3<br />
DQD4<br />
DQD5<br />
DQD6<br />
DQD7<br />
DQPA<br />
DQA0<br />
DQA1<br />
DQA2<br />
DQA3<br />
DQA4<br />
DQA5<br />
DQA6<br />
DQA7<br />
DQPB<br />
DQB0<br />
DQB1<br />
DQB2<br />
DQB3<br />
DQB4<br />
DQB5<br />
DQB6<br />
DQB7<br />
1<br />
2<br />
3<br />
6<br />
7<br />
8<br />
9<br />
12<br />
13<br />
30<br />
18<br />
19<br />
22<br />
23<br />
24<br />
25<br />
28<br />
29<br />
51<br />
52<br />
53<br />
56<br />
57<br />
58<br />
59<br />
62<br />
63<br />
80<br />
68<br />
69<br />
72<br />
73<br />
74<br />
75<br />
78<br />
79<br />
MEMORY_BANK1_DATA_C1<br />
MEMORY_BANK1_DATA_C0<br />
MEMORY_BANK1_DATA_C2<br />
MEMORY_BANK1_DATA_C3<br />
MEMORY_BANK1_DATA_C4<br />
MEMORY_BANK1_DATA_C5<br />
MEMORY_BANK1_DATA_C6<br />
MEMORY_BANK1_DATA_C7<br />
MEMORY_BANK1_DATA_D0<br />
MEMORY_BANK1_DATA_D1<br />
MEMORY_BANK1_DATA_D2<br />
MEMORY_BANK1_DATA_D3<br />
MEMORY_BANK1_DATA_D4<br />
MEMORY_BANK1_DATA_D5<br />
MEMORY_BANK1_DATA_D6<br />
MEMORY_BANK1_DATA_D7<br />
MEMORY_BANK1_DATA_A0<br />
MEMORY_BANK1_DATA_A1<br />
MEMORY_BANK1_DATA_A2<br />
MEMORY_BANK1_DATA_A3<br />
MEMORY_BANK1_DATA_A4<br />
MEMORY_BANK1_DATA_A5<br />
MEMORY_BANK1_DATA_A6<br />
MEMORY_BANK1_DATA_A7<br />
MEMORY_BANK1_DATA_B0<br />
MEMORY_BANK1_DATA_B1<br />
MEMORY_BANK1_DATA_B2<br />
MEMORY_BANK1_DATA_B3<br />
MEMORY_BANK1_DATA_B4<br />
MEMORY_BANK1_DATA_B5<br />
MEMORY_BANK1_DATA_B6<br />
MEMORY_BANK1_DATA_B7<br />
D<br />
C<br />
MEMORY_BANK1_DATA_A0<br />
MEMORY_BANK1_DATA_A1<br />
MEMORY_BANK1_DATA_A2<br />
MEMORY_BANK1_DATA_A3<br />
R136<br />
3K0 5%<br />
98<br />
97<br />
92<br />
CS1<br />
CS2<br />
CS2<br />
NC<br />
NC<br />
NC<br />
NC<br />
38<br />
39<br />
42<br />
43<br />
R137<br />
3K0 5%<br />
MEMORY_BANK1_DATA_A4<br />
VCC3V3<br />
B<br />
MEMORY_BANK1_DATA_A5<br />
MEMORY_BANK1_DATA_A6<br />
MEMORY_BANK1_DATA_A7<br />
MEMORY_BANK1_DATA_B0<br />
MEMORY_BANK1_DATA_B1<br />
MEMORY_BANK1_DATA_B2<br />
GND<br />
14<br />
15<br />
16<br />
41<br />
65<br />
66<br />
91<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
GND<br />
GND<br />
GND<br />
GND<br />
90<br />
67<br />
40<br />
17<br />
B<br />
MEMORY_BANK1_DATA_B3<br />
MEMORY_BANK1_DATA_B4<br />
MEMORY_BANK1_DATA_B5<br />
MEMORY_BANK1_DATA_B6<br />
MEMORY_BANK1_DATA_B7<br />
MEMORY_BANK1_DATA_C0<br />
MEMORY_BANK1_DATA_C1<br />
MEMORY_BANK1_DATA_C2<br />
MAX NET LENGTH 2.0 inches.<br />
CLOCK net must be the<br />
longest net.<br />
4<br />
11<br />
20<br />
27<br />
54<br />
61<br />
70<br />
77<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
76<br />
71<br />
60<br />
55<br />
26<br />
21<br />
10<br />
5<br />
MEMORY_BANK1_DATA_C3<br />
MEMORY_BANK1_DATA_C4<br />
512k X 36 ZBT SRAM<br />
MEMORY_BANK1_DATA_C5<br />
MEMORY_BANK1_DATA_C6<br />
MEMORY_BANK1_DATA_C7<br />
K7N163601M<br />
GND<br />
A<br />
MEMORY_BANK1_DATA_D0<br />
MEMORY_BANK1_DATA_D1<br />
A<br />
MEMORY_BANK1_DATA_D2<br />
MEMORY_BANK1_DATA_D3<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
MEMORY_BANK1_DATA_D4<br />
MEMORY_BANK1_DATA_D5<br />
MEMORY_BANK1_DATA_D6<br />
MEMORY_BANK1_DATA_D7<br />
Title<br />
Size<br />
MEMORY BANK1 512k x 32<br />
Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 20 of 35<br />
5<br />
4<br />
3<br />
2<br />
1<br />
2<br />
1
5<br />
4<br />
MEMORY_BANK2_ADDR[0..18]<br />
3<br />
MEMORY_BANK2_DATA_A[0..7],MEMORY_BANK2_DATA_B[0..7],MEMORY_BANK2_DATA_C[0..7],MEMORY_BANK2_DATA_D[0..7]<br />
MEMORY_BANK2_ADDR0<br />
MEMORY_BANK2_ADDR1<br />
MEMORY_BANK2_ADDR2<br />
U9<br />
D<br />
C<br />
MEMORY_BANK2_ADDR3<br />
MEMORY_BANK2_ADDR4<br />
MEMORY_BANK2_ADDR5<br />
MEMORY_BANK2_ADDR6<br />
MEMORY_BANK2_ADDR7<br />
MEMORY_BANK2_ADDR8<br />
MEMORY_BANK2_ADDR9<br />
MEMORY_BANK2_ADDR10<br />
MEMORY_BANK2_ADDR11<br />
MEMORY_BANK2_ADDR12<br />
MEMORY_BANK2_ADDR13<br />
MEMORY_BANK2_ADDR14<br />
MEMORY_BANK2_ADDR15<br />
MEMORY_BANK2_ADDR16<br />
MEMORY_BANK2_ADDR17<br />
MEMORY_BANK2_ADDR18<br />
MEMORY_BANK2_CLK<br />
MEMORY_BANK2_CLKEN_Z<br />
MEMORY_BANK2_WEN_Z<br />
MEMORY_BANK2_WENA_Z<br />
MEMORY_BANK2_WENB_Z<br />
MEMORY_BANK2_WENC_Z<br />
MEMORY_BANK2_WEND_Z<br />
MEMORY_BANK2_ADV_LDZ<br />
MEMORY_BANK2_OEN_Z<br />
MEMORY_BANK2_CEN_Z<br />
CLOCK to be routed on<br />
INTERNAL layer<br />
R138<br />
20.0 1%<br />
MEMORY_BANK2_ADDR0<br />
MEMORY_BANK2_ADDR1<br />
MEMORY_BANK2_ADDR2<br />
MEMORY_BANK2_ADDR3<br />
MEMORY_BANK2_ADDR4<br />
MEMORY_BANK2_ADDR5<br />
MEMORY_BANK2_ADDR6<br />
MEMORY_BANK2_ADDR7<br />
MEMORY_BANK2_ADDR8<br />
MEMORY_BANK2_ADDR9<br />
MEMORY_BANK2_ADDR10<br />
MEMORY_BANK2_ADDR11<br />
MEMORY_BANK2_ADDR12<br />
MEMORY_BANK2_ADDR13<br />
MEMORY_BANK2_ADDR14<br />
MEMORY_BANK2_ADDR15<br />
MEMORY_BANK2_ADDR16<br />
MEMORY_BANK2_ADDR17<br />
MEMORY_BANK2_ADDR18<br />
MEMORY_BANK2_CLK_R<br />
37<br />
36<br />
35<br />
34<br />
33<br />
32<br />
100<br />
99<br />
82<br />
81<br />
44<br />
45<br />
46<br />
47<br />
48<br />
49<br />
50<br />
83<br />
84<br />
89<br />
87<br />
88<br />
93<br />
94<br />
95<br />
96<br />
31<br />
64<br />
85<br />
86<br />
A0<br />
A1<br />
A2<br />
A3<br />
A4<br />
A5<br />
A6<br />
A7<br />
A8<br />
A9<br />
A10<br />
A11<br />
A12<br />
A13<br />
A14<br />
A15<br />
A16<br />
A17<br />
A18<br />
CLK<br />
CKE<br />
WE<br />
WEA<br />
WEB<br />
WEC<br />
WED<br />
LBO<br />
ZZ<br />
ADV_LD<br />
OE<br />
DQPC<br />
DQC0<br />
DQC1<br />
DQC2<br />
DQC3<br />
DQC4<br />
DQC5<br />
DQC6<br />
DQC7<br />
DQPD<br />
DQD0<br />
DQD1<br />
DQD2<br />
DQD3<br />
DQD4<br />
DQD5<br />
DQD6<br />
DQD7<br />
DQPA<br />
DQA0<br />
DQA1<br />
DQA2<br />
DQA3<br />
DQA4<br />
DQA5<br />
DQA6<br />
DQA7<br />
DQPB<br />
DQB0<br />
DQB1<br />
DQB2<br />
DQB3<br />
DQB4<br />
DQB5<br />
DQB6<br />
DQB7<br />
1<br />
2<br />
3<br />
6<br />
7<br />
8<br />
9<br />
12<br />
13<br />
30<br />
18<br />
19<br />
22<br />
23<br />
24<br />
25<br />
28<br />
29<br />
51<br />
52<br />
53<br />
56<br />
57<br />
58<br />
59<br />
62<br />
63<br />
80<br />
68<br />
69<br />
72<br />
73<br />
74<br />
75<br />
78<br />
79<br />
MEMORY_BANK2_DATA_C1<br />
MEMORY_BANK2_DATA_C0<br />
MEMORY_BANK2_DATA_C2<br />
MEMORY_BANK2_DATA_C3<br />
MEMORY_BANK2_DATA_C4<br />
MEMORY_BANK2_DATA_C5<br />
MEMORY_BANK2_DATA_C6<br />
MEMORY_BANK2_DATA_C7<br />
MEMORY_BANK2_DATA_D0<br />
MEMORY_BANK2_DATA_D1<br />
MEMORY_BANK2_DATA_D2<br />
MEMORY_BANK2_DATA_D3<br />
MEMORY_BANK2_DATA_D4<br />
MEMORY_BANK2_DATA_D5<br />
MEMORY_BANK2_DATA_D6<br />
MEMORY_BANK2_DATA_D7<br />
MEMORY_BANK2_DATA_A0<br />
MEMORY_BANK2_DATA_A1<br />
MEMORY_BANK2_DATA_A2<br />
MEMORY_BANK2_DATA_A3<br />
MEMORY_BANK2_DATA_A4<br />
MEMORY_BANK2_DATA_A5<br />
MEMORY_BANK2_DATA_A6<br />
MEMORY_BANK2_DATA_A7<br />
MEMORY_BANK2_DATA_B0<br />
MEMORY_BANK2_DATA_B1<br />
MEMORY_BANK2_DATA_B2<br />
MEMORY_BANK2_DATA_B3<br />
MEMORY_BANK2_DATA_B4<br />
MEMORY_BANK2_DATA_B5<br />
MEMORY_BANK2_DATA_B6<br />
MEMORY_BANK2_DATA_B7<br />
D<br />
C<br />
MEMORY_BANK2_DATA_A0<br />
MEMORY_BANK2_DATA_A1<br />
MEMORY_BANK2_DATA_A2<br />
MEMORY_BANK2_DATA_A3<br />
R139<br />
3K0 5%<br />
98<br />
97<br />
92<br />
CS1<br />
CS2<br />
CS2<br />
NC<br />
NC<br />
NC<br />
NC<br />
38<br />
39<br />
42<br />
43<br />
R140<br />
3K0 5%<br />
MEMORY_BANK2_DATA_A4<br />
VCC3V3<br />
B<br />
MEMORY_BANK2_DATA_A5<br />
MEMORY_BANK2_DATA_A6<br />
MEMORY_BANK2_DATA_A7<br />
MEMORY_BANK2_DATA_B0<br />
MEMORY_BANK2_DATA_B1<br />
MEMORY_BANK2_DATA_B2<br />
GND<br />
14<br />
15<br />
16<br />
41<br />
65<br />
66<br />
91<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
GND<br />
GND<br />
GND<br />
GND<br />
90<br />
67<br />
40<br />
17<br />
B<br />
MEMORY_BANK2_DATA_B3<br />
MEMORY_BANK2_DATA_B4<br />
MEMORY_BANK2_DATA_B5<br />
MEMORY_BANK2_DATA_B6<br />
MEMORY_BANK2_DATA_B7<br />
MEMORY_BANK2_DATA_C0<br />
MEMORY_BANK2_DATA_C1<br />
MEMORY_BANK2_DATA_C2<br />
MAX NET LENGTH 2.0 inches.<br />
CLOCK net must be the<br />
longest net.<br />
4<br />
11<br />
20<br />
27<br />
54<br />
61<br />
70<br />
77<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
76<br />
71<br />
60<br />
55<br />
26<br />
21<br />
10<br />
5<br />
MEMORY_BANK2_DATA_C3<br />
MEMORY_BANK2_DATA_C4<br />
512k X 36 ZBT SRAM<br />
MEMORY_BANK2_DATA_C5<br />
MEMORY_BANK2_DATA_C6<br />
MEMORY_BANK2_DATA_C7<br />
K7N163601M<br />
GND<br />
A<br />
MEMORY_BANK2_DATA_D0<br />
MEMORY_BANK2_DATA_D1<br />
A<br />
MEMORY_BANK2_DATA_D2<br />
MEMORY_BANK2_DATA_D3<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
MEMORY_BANK2_DATA_D4<br />
MEMORY_BANK2_DATA_D5<br />
MEMORY_BANK2_DATA_D6<br />
MEMORY_BANK2_DATA_D7<br />
Title<br />
Size<br />
MEMORY BANK2 512k x 32<br />
Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 21 of 35<br />
5<br />
4<br />
3<br />
2<br />
1<br />
2<br />
1
5<br />
4<br />
MEMORY_BANK3_ADDR[0..18]<br />
3<br />
MEMORY_BANK3_DATA_A[0..7],MEMORY_BANK3_DATA_B[0..7],MEMORY_BANK3_DATA_C[0..7],MEMORY_BANK3_DATA_D[0..7]<br />
MEMORY_BANK3_ADDR0<br />
MEMORY_BANK3_ADDR1<br />
MEMORY_BANK3_ADDR2<br />
U10<br />
D<br />
C<br />
MEMORY_BANK3_ADDR3<br />
MEMORY_BANK3_ADDR4<br />
MEMORY_BANK3_ADDR5<br />
MEMORY_BANK3_ADDR6<br />
MEMORY_BANK3_ADDR7<br />
MEMORY_BANK3_ADDR8<br />
MEMORY_BANK3_ADDR9<br />
MEMORY_BANK3_ADDR10<br />
MEMORY_BANK3_ADDR11<br />
MEMORY_BANK3_ADDR12<br />
MEMORY_BANK3_ADDR13<br />
MEMORY_BANK3_ADDR14<br />
MEMORY_BANK3_ADDR15<br />
MEMORY_BANK3_ADDR16<br />
MEMORY_BANK3_ADDR17<br />
MEMORY_BANK3_ADDR18<br />
MEMORY_BANK3_CLK<br />
MEMORY_BANK3_CLKEN_Z<br />
MEMORY_BANK3_WEN_Z<br />
MEMORY_BANK3_WENA_Z<br />
MEMORY_BANK3_WENB_Z<br />
MEMORY_BANK3_WENC_Z<br />
MEMORY_BANK3_WEND_Z<br />
MEMORY_BANK3_ADV_LDZ<br />
MEMORY_BANK3_OEN_Z<br />
MEMORY_BANK3_CEN_Z<br />
CLOCK to be routed on<br />
INTERNAL layer<br />
R141<br />
20.0 1%<br />
MEMORY_BANK3_ADDR0<br />
MEMORY_BANK3_ADDR1<br />
MEMORY_BANK3_ADDR2<br />
MEMORY_BANK3_ADDR3<br />
MEMORY_BANK3_ADDR4<br />
MEMORY_BANK3_ADDR5<br />
MEMORY_BANK3_ADDR6<br />
MEMORY_BANK3_ADDR7<br />
MEMORY_BANK3_ADDR8<br />
MEMORY_BANK3_ADDR9<br />
MEMORY_BANK3_ADDR10<br />
MEMORY_BANK3_ADDR11<br />
MEMORY_BANK3_ADDR12<br />
MEMORY_BANK3_ADDR13<br />
MEMORY_BANK3_ADDR14<br />
MEMORY_BANK3_ADDR15<br />
MEMORY_BANK3_ADDR16<br />
MEMORY_BANK3_ADDR17<br />
MEMORY_BANK3_ADDR18<br />
MEMORY_BANK3_CLK_R<br />
37<br />
36<br />
35<br />
34<br />
33<br />
32<br />
100<br />
99<br />
82<br />
81<br />
44<br />
45<br />
46<br />
47<br />
48<br />
49<br />
50<br />
83<br />
84<br />
89<br />
87<br />
88<br />
93<br />
94<br />
95<br />
96<br />
31<br />
64<br />
85<br />
86<br />
A0<br />
A1<br />
A2<br />
A3<br />
A4<br />
A5<br />
A6<br />
A7<br />
A8<br />
A9<br />
A10<br />
A11<br />
A12<br />
A13<br />
A14<br />
A15<br />
A16<br />
A17<br />
A18<br />
CLK<br />
CKE<br />
WE<br />
WEA<br />
WEB<br />
WEC<br />
WED<br />
LBO<br />
ZZ<br />
ADV_LD<br />
OE<br />
DQPC<br />
DQC0<br />
DQC1<br />
DQC2<br />
DQC3<br />
DQC4<br />
DQC5<br />
DQC6<br />
DQC7<br />
DQPD<br />
DQD0<br />
DQD1<br />
DQD2<br />
DQD3<br />
DQD4<br />
DQD5<br />
DQD6<br />
DQD7<br />
DQPA<br />
DQA0<br />
DQA1<br />
DQA2<br />
DQA3<br />
DQA4<br />
DQA5<br />
DQA6<br />
DQA7<br />
DQPB<br />
DQB0<br />
DQB1<br />
DQB2<br />
DQB3<br />
DQB4<br />
DQB5<br />
DQB6<br />
DQB7<br />
1<br />
2<br />
3<br />
6<br />
7<br />
8<br />
9<br />
12<br />
13<br />
30<br />
18<br />
19<br />
22<br />
23<br />
24<br />
25<br />
28<br />
29<br />
51<br />
52<br />
53<br />
56<br />
57<br />
58<br />
59<br />
62<br />
63<br />
80<br />
68<br />
69<br />
72<br />
73<br />
74<br />
75<br />
78<br />
79<br />
MEMORY_BANK3_DATA_C1<br />
MEMORY_BANK3_DATA_C0<br />
MEMORY_BANK3_DATA_C2<br />
MEMORY_BANK3_DATA_C3<br />
MEMORY_BANK3_DATA_C4<br />
MEMORY_BANK3_DATA_C5<br />
MEMORY_BANK3_DATA_C6<br />
MEMORY_BANK3_DATA_C7<br />
MEMORY_BANK3_DATA_D0<br />
MEMORY_BANK3_DATA_D1<br />
MEMORY_BANK3_DATA_D2<br />
MEMORY_BANK3_DATA_D3<br />
MEMORY_BANK3_DATA_D4<br />
MEMORY_BANK3_DATA_D5<br />
MEMORY_BANK3_DATA_D6<br />
MEMORY_BANK3_DATA_D7<br />
MEMORY_BANK3_DATA_A0<br />
MEMORY_BANK3_DATA_A1<br />
MEMORY_BANK3_DATA_A2<br />
MEMORY_BANK3_DATA_A3<br />
MEMORY_BANK3_DATA_A4<br />
MEMORY_BANK3_DATA_A5<br />
MEMORY_BANK3_DATA_A6<br />
MEMORY_BANK3_DATA_A7<br />
MEMORY_BANK3_DATA_B0<br />
MEMORY_BANK3_DATA_B1<br />
MEMORY_BANK3_DATA_B2<br />
MEMORY_BANK3_DATA_B3<br />
MEMORY_BANK3_DATA_B4<br />
MEMORY_BANK3_DATA_B5<br />
MEMORY_BANK3_DATA_B6<br />
MEMORY_BANK3_DATA_B7<br />
D<br />
C<br />
MEMORY_BANK3_DATA_A0<br />
MEMORY_BANK3_DATA_A1<br />
MEMORY_BANK3_DATA_A2<br />
MEMORY_BANK3_DATA_A3<br />
R142<br />
3K0 5%<br />
98<br />
97<br />
92<br />
CS1<br />
CS2<br />
CS2<br />
NC<br />
NC<br />
NC<br />
NC<br />
38<br />
39<br />
42<br />
43<br />
R143<br />
3K0 5%<br />
MEMORY_BANK3_DATA_A4<br />
VCC3V3<br />
B<br />
MEMORY_BANK3_DATA_A5<br />
MEMORY_BANK3_DATA_A6<br />
MEMORY_BANK3_DATA_A7<br />
MEMORY_BANK3_DATA_B0<br />
MEMORY_BANK3_DATA_B1<br />
MEMORY_BANK3_DATA_B2<br />
GND<br />
14<br />
15<br />
16<br />
41<br />
65<br />
66<br />
91<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
GND<br />
GND<br />
GND<br />
GND<br />
90<br />
67<br />
40<br />
17<br />
B<br />
MEMORY_BANK3_DATA_B3<br />
MEMORY_BANK3_DATA_B4<br />
MEMORY_BANK3_DATA_B5<br />
MEMORY_BANK3_DATA_B6<br />
MEMORY_BANK3_DATA_B7<br />
MEMORY_BANK3_DATA_C0<br />
MEMORY_BANK3_DATA_C1<br />
MEMORY_BANK3_DATA_C2<br />
MAX NET LENGTH 2.0 inches.<br />
CLOCK net must be the<br />
longest net.<br />
4<br />
11<br />
20<br />
27<br />
54<br />
61<br />
70<br />
77<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
76<br />
71<br />
60<br />
55<br />
26<br />
21<br />
10<br />
5<br />
MEMORY_BANK3_DATA_C3<br />
MEMORY_BANK3_DATA_C4<br />
512k X 36 ZBT SRAM<br />
MEMORY_BANK3_DATA_C5<br />
MEMORY_BANK3_DATA_C6<br />
MEMORY_BANK3_DATA_C7<br />
K7N163601M<br />
GND<br />
A<br />
MEMORY_BANK3_DATA_D0<br />
MEMORY_BANK3_DATA_D1<br />
A<br />
MEMORY_BANK3_DATA_D2<br />
MEMORY_BANK3_DATA_D3<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
MEMORY_BANK3_DATA_D4<br />
MEMORY_BANK3_DATA_D5<br />
MEMORY_BANK3_DATA_D6<br />
MEMORY_BANK3_DATA_D7<br />
Title<br />
Size<br />
MEMORY BANK3 512k x 32<br />
Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 22 of 35<br />
5<br />
4<br />
3<br />
2<br />
1<br />
2<br />
1
5<br />
4<br />
MEMORY_BANK4_ADDR[0..18]<br />
3<br />
MEMORY_BANK4_DATA_A[0..7],MEMORY_BANK4_DATA_B[0..7],MEMORY_BANK4_DATA_C[0..7],MEMORY_BANK4_DATA_D[0..7]<br />
MEMORY_BANK4_ADDR0<br />
MEMORY_BANK4_ADDR1<br />
MEMORY_BANK4_ADDR2<br />
U11<br />
D<br />
C<br />
MEMORY_BANK4_ADDR3<br />
MEMORY_BANK4_ADDR4<br />
MEMORY_BANK4_ADDR5<br />
MEMORY_BANK4_ADDR6<br />
MEMORY_BANK4_ADDR7<br />
MEMORY_BANK4_ADDR8<br />
MEMORY_BANK4_ADDR9<br />
MEMORY_BANK4_ADDR10<br />
MEMORY_BANK4_ADDR11<br />
MEMORY_BANK4_ADDR12<br />
MEMORY_BANK4_ADDR13<br />
MEMORY_BANK4_ADDR14<br />
MEMORY_BANK4_ADDR15<br />
MEMORY_BANK4_ADDR16<br />
MEMORY_BANK4_ADDR17<br />
MEMORY_BANK4_ADDR18<br />
MEMORY_BANK4_CLK<br />
MEMORY_BANK4_CLKEN_Z<br />
MEMORY_BANK4_WEN_Z<br />
MEMORY_BANK4_WENA_Z<br />
MEMORY_BANK4_WENB_Z<br />
MEMORY_BANK4_WENC_Z<br />
MEMORY_BANK4_WEND_Z<br />
MEMORY_BANK4_ADV_LDZ<br />
MEMORY_BANK4_OEN_Z<br />
MEMORY_BANK4_CEN_Z<br />
CLOCK to be routed on<br />
INTERNAL layer<br />
R144<br />
20.0 1%<br />
MEMORY_BANK4_ADDR0<br />
MEMORY_BANK4_ADDR1<br />
MEMORY_BANK4_ADDR2<br />
MEMORY_BANK4_ADDR3<br />
MEMORY_BANK4_ADDR4<br />
MEMORY_BANK4_ADDR5<br />
MEMORY_BANK4_ADDR6<br />
MEMORY_BANK4_ADDR7<br />
MEMORY_BANK4_ADDR8<br />
MEMORY_BANK4_ADDR9<br />
MEMORY_BANK4_ADDR10<br />
MEMORY_BANK4_ADDR11<br />
MEMORY_BANK4_ADDR12<br />
MEMORY_BANK4_ADDR13<br />
MEMORY_BANK4_ADDR14<br />
MEMORY_BANK4_ADDR15<br />
MEMORY_BANK4_ADDR16<br />
MEMORY_BANK4_ADDR17<br />
MEMORY_BANK4_ADDR18<br />
MEMORY_BANK4_CLK_R<br />
37<br />
36<br />
35<br />
34<br />
33<br />
32<br />
100<br />
99<br />
82<br />
81<br />
44<br />
45<br />
46<br />
47<br />
48<br />
49<br />
50<br />
83<br />
84<br />
89<br />
87<br />
88<br />
93<br />
94<br />
95<br />
96<br />
31<br />
64<br />
85<br />
86<br />
A0<br />
A1<br />
A2<br />
A3<br />
A4<br />
A5<br />
A6<br />
A7<br />
A8<br />
A9<br />
A10<br />
A11<br />
A12<br />
A13<br />
A14<br />
A15<br />
A16<br />
A17<br />
A18<br />
CLK<br />
CKE<br />
WE<br />
WEA<br />
WEB<br />
WEC<br />
WED<br />
LBO<br />
ZZ<br />
ADV_LD<br />
OE<br />
DQPC<br />
DQC0<br />
DQC1<br />
DQC2<br />
DQC3<br />
DQC4<br />
DQC5<br />
DQC6<br />
DQC7<br />
DQPD<br />
DQD0<br />
DQD1<br />
DQD2<br />
DQD3<br />
DQD4<br />
DQD5<br />
DQD6<br />
DQD7<br />
DQPA<br />
DQA0<br />
DQA1<br />
DQA2<br />
DQA3<br />
DQA4<br />
DQA5<br />
DQA6<br />
DQA7<br />
DQPB<br />
DQB0<br />
DQB1<br />
DQB2<br />
DQB3<br />
DQB4<br />
DQB5<br />
DQB6<br />
DQB7<br />
1<br />
2<br />
3<br />
6<br />
7<br />
8<br />
9<br />
12<br />
13<br />
30<br />
18<br />
19<br />
22<br />
23<br />
24<br />
25<br />
28<br />
29<br />
51<br />
52<br />
53<br />
56<br />
57<br />
58<br />
59<br />
62<br />
63<br />
80<br />
68<br />
69<br />
72<br />
73<br />
74<br />
75<br />
78<br />
79<br />
MEMORY_BANK4_DATA_C1<br />
MEMORY_BANK4_DATA_C0<br />
MEMORY_BANK4_DATA_C2<br />
MEMORY_BANK4_DATA_C3<br />
MEMORY_BANK4_DATA_C4<br />
MEMORY_BANK4_DATA_C5<br />
MEMORY_BANK4_DATA_C6<br />
MEMORY_BANK4_DATA_C7<br />
MEMORY_BANK4_DATA_D0<br />
MEMORY_BANK4_DATA_D1<br />
MEMORY_BANK4_DATA_D2<br />
MEMORY_BANK4_DATA_D3<br />
MEMORY_BANK4_DATA_D4<br />
MEMORY_BANK4_DATA_D5<br />
MEMORY_BANK4_DATA_D6<br />
MEMORY_BANK4_DATA_D7<br />
MEMORY_BANK4_DATA_A0<br />
MEMORY_BANK4_DATA_A1<br />
MEMORY_BANK4_DATA_A2<br />
MEMORY_BANK4_DATA_A3<br />
MEMORY_BANK4_DATA_A4<br />
MEMORY_BANK4_DATA_A5<br />
MEMORY_BANK4_DATA_A6<br />
MEMORY_BANK4_DATA_A7<br />
MEMORY_BANK4_DATA_B0<br />
MEMORY_BANK4_DATA_B1<br />
MEMORY_BANK4_DATA_B2<br />
MEMORY_BANK4_DATA_B3<br />
MEMORY_BANK4_DATA_B4<br />
MEMORY_BANK4_DATA_B5<br />
MEMORY_BANK4_DATA_B6<br />
MEMORY_BANK4_DATA_B7<br />
D<br />
C<br />
MEMORY_BANK4_DATA_A0<br />
MEMORY_BANK4_DATA_A1<br />
MEMORY_BANK4_DATA_A2<br />
MEMORY_BANK4_DATA_A3<br />
R145<br />
3K0 5%<br />
98<br />
97<br />
92<br />
CS1<br />
CS2<br />
CS2<br />
NC<br />
NC<br />
NC<br />
NC<br />
38<br />
39<br />
42<br />
43<br />
R146<br />
3K0 5%<br />
MEMORY_BANK4_DATA_A4<br />
VCC3V3<br />
B<br />
MEMORY_BANK4_DATA_A5<br />
MEMORY_BANK4_DATA_A6<br />
MEMORY_BANK4_DATA_A7<br />
MEMORY_BANK4_DATA_B0<br />
MEMORY_BANK4_DATA_B1<br />
MEMORY_BANK4_DATA_B2<br />
GND<br />
14<br />
15<br />
16<br />
41<br />
65<br />
66<br />
91<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
GND<br />
GND<br />
GND<br />
GND<br />
90<br />
67<br />
40<br />
17<br />
B<br />
MEMORY_BANK4_DATA_B3<br />
MEMORY_BANK4_DATA_B4<br />
MEMORY_BANK4_DATA_B5<br />
MEMORY_BANK4_DATA_B6<br />
MEMORY_BANK4_DATA_B7<br />
MEMORY_BANK4_DATA_C0<br />
MEMORY_BANK4_DATA_C1<br />
MEMORY_BANK4_DATA_C2<br />
MAX NET LENGTH 2.0 inches.<br />
CLOCK net must be the<br />
longest net.<br />
4<br />
11<br />
20<br />
27<br />
54<br />
61<br />
70<br />
77<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
76<br />
71<br />
60<br />
55<br />
26<br />
21<br />
10<br />
5<br />
MEMORY_BANK4_DATA_C3<br />
MEMORY_BANK4_DATA_C4<br />
512k X 36 ZBT SRAM<br />
MEMORY_BANK4_DATA_C5<br />
MEMORY_BANK4_DATA_C6<br />
MEMORY_BANK4_DATA_C7<br />
K7N163601M<br />
GND<br />
A<br />
MEMORY_BANK4_DATA_D0<br />
MEMORY_BANK4_DATA_D1<br />
A<br />
MEMORY_BANK4_DATA_D2<br />
MEMORY_BANK4_DATA_D3<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
MEMORY_BANK4_DATA_D4<br />
MEMORY_BANK4_DATA_D5<br />
MEMORY_BANK4_DATA_D6<br />
MEMORY_BANK4_DATA_D7<br />
Title<br />
Size<br />
MEMORY BANK4 512k x 32<br />
Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 23 of 35<br />
5<br />
4<br />
3<br />
2<br />
1<br />
2<br />
1
VCC3V3<br />
5<br />
5<br />
4<br />
4<br />
3<br />
U30<br />
20 19 12<br />
U12<br />
D S_VIDEO_Z D<br />
C269<br />
SHDN VCC VL<br />
C270<br />
VCC<br />
14<br />
PAL_NTSC_Z<br />
1<br />
C1+<br />
V+<br />
2<br />
RS232_TX_DATA<br />
2<br />
1A<br />
1Y<br />
3<br />
MOUSE_CLOCK<br />
USER_INPUT1<br />
0.22uF<br />
RS232_RX_DATA<br />
5<br />
MOUSE_DATA<br />
3<br />
0.22uF<br />
2A<br />
2Y<br />
6<br />
C1-<br />
USER_INPUT0<br />
C271<br />
C272<br />
RS232_CTS_OUT<br />
9<br />
3A<br />
3Y<br />
8<br />
KBD_CLOCK<br />
C<br />
0.22uF<br />
RS232_TX_DATA<br />
RS232_DSR_OUT<br />
RS232_CTS_OUT<br />
RS232_RX_DATA<br />
RS232_RTS_IN<br />
5<br />
7<br />
8<br />
9<br />
11<br />
10<br />
C2-<br />
T1IN<br />
T2IN<br />
T3IN<br />
R1OUT<br />
R2OUT<br />
T1OUT<br />
T2OUT<br />
T3OUT<br />
R1IN<br />
R2IN<br />
17<br />
16<br />
15<br />
14<br />
13<br />
RXD<br />
DSR<br />
CTS<br />
TXD<br />
RTS<br />
0.22uF<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
J16<br />
RS232 DCE<br />
RS232_DATA_ENZ<br />
RS232_CTRL_ENZ<br />
1<br />
4<br />
10<br />
13<br />
1OE<br />
2OE<br />
3OE<br />
4OE<br />
GND<br />
IDTQS3125<br />
7<br />
C138<br />
0.1uF<br />
VCC3V3<br />
SW2<br />
SW DIP-2<br />
D29<br />
SW3<br />
SW DIP-2<br />
R241<br />
USER_LED0_Z<br />
C<br />
GND<br />
AMBER<br />
18 MAX3386ECUP<br />
110 5%<br />
open open serial ports disabled<br />
open closed RS232 with handshake<br />
closed open PS2 keyboard & RS232 TX RX only<br />
closed closed PS2 keyboard & mouse<br />
A J21<br />
A<br />
6<br />
4<br />
2<br />
4<br />
PS2_CON<br />
C2+<br />
5<br />
3<br />
1<br />
V-<br />
6<br />
C268<br />
0.1uF<br />
KBD_CLOCK_IN<br />
KBD_DATA_IN<br />
RS232_DSR_OUT<br />
VCC3V3<br />
R273<br />
5K1 5%<br />
3<br />
VCC5V0<br />
KBD_DATA<br />
2<br />
2<br />
VCC3V3<br />
VCC3V3<br />
USER<br />
LEDs<br />
5V TO 3.3V LEVEL<br />
TRANSLATION<br />
FOR PS2 PORTS<br />
SERIAL_SELECT1<br />
D31<br />
SERIAL_SELECT0<br />
1N4148W<br />
U27<br />
B<br />
SW5<br />
VCC<br />
14<br />
B<br />
SW DIP-2<br />
MOUSE_CLOCK_IN<br />
2<br />
1A<br />
1Y<br />
3<br />
MOUSE_CLOCK<br />
VCC5V0<br />
MOUSE_DATA_IN<br />
5<br />
2A<br />
2Y<br />
6<br />
MOUSE_DATA<br />
KBD_CLOCK_IN<br />
9<br />
3A<br />
3Y<br />
8<br />
KBD_CLOCK<br />
R268 R269 R270 R271<br />
KBD_DATA_IN<br />
12<br />
4A<br />
4Y<br />
11<br />
KBD_DATA<br />
VCC5V0<br />
6<br />
4<br />
2<br />
J20<br />
5<br />
3<br />
1<br />
5K1 5% 5K1 5% 5K1 5%<br />
5K1 5%<br />
MOUSE_CLOCK_IN<br />
MOUSE_DATA_IN<br />
SELECTION OF THE ACTIVE<br />
SERIAL PORTS<br />
PS2_PORT1_ENZ<br />
1<br />
4<br />
10<br />
1OE<br />
2OE<br />
3OE<br />
R275<br />
10K 5%<br />
C139<br />
0.1uF<br />
PS2_PORT2_ENZ<br />
13<br />
4OE<br />
PS2_CON<br />
12<br />
4A<br />
R274<br />
5K1 5%<br />
4Y<br />
11<br />
Title<br />
R147<br />
3K0 5%<br />
XILINX INC.<br />
D30<br />
AMBER<br />
IDTQS3125<br />
R149<br />
3K0 5%<br />
GND<br />
R266<br />
110 5%<br />
7<br />
R148<br />
3K0 5%<br />
2100 Logic Drive San Jose California USA 95124<br />
OPTION SELECTS AND SERIAL PORTS<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
24 of 35<br />
1<br />
R233<br />
3K0 5%<br />
USER_LED1_Z<br />
VCC5V0
5<br />
5<br />
4<br />
4<br />
3<br />
100 1%<br />
49.9 1%<br />
U14<br />
2<br />
U13<br />
D C273<br />
0.1uF<br />
1<br />
2<br />
FB1<br />
CREF<br />
FB2<br />
CP<br />
28<br />
27<br />
R153<br />
C274<br />
BAT54S<br />
VCC5V0<br />
3<br />
1<br />
VIN<br />
ADJ<br />
VOUT<br />
TAB<br />
2<br />
4<br />
R152<br />
C275<br />
D<br />
C276<br />
68pF<br />
3<br />
CSLOPE<br />
C2V<br />
26<br />
1uF @ 20V<br />
3<br />
C277 +<br />
LT1587/DD_2<br />
100 1%<br />
0.1uF<br />
C278<br />
330pF<br />
4<br />
5<br />
COSC<br />
VDD<br />
VSS<br />
VHI<br />
25<br />
24<br />
20.0 1%<br />
R154<br />
D21<br />
BAT54S<br />
C280<br />
47uF @ 16V<br />
+ C279<br />
47uF @ 16V<br />
R155<br />
6<br />
VIN<br />
LX<br />
23 C281<br />
39.2 1%<br />
2 1<br />
0.22uF<br />
R156<br />
VCC5V0<br />
+ C285<br />
330uF @ 10V<br />
+<br />
5.11 1%<br />
C287<br />
C486<br />
1uF 25V<br />
+ C286<br />
1uF @ 20V<br />
7<br />
8<br />
9<br />
10<br />
11<br />
VSSP<br />
VIN<br />
VSSP<br />
VSSP<br />
VSSP<br />
LX<br />
LX<br />
LX<br />
VSSP<br />
VSSP<br />
22<br />
21<br />
20<br />
19<br />
18<br />
1<br />
0.1uF L9<br />
2.5uH<br />
PE-53681<br />
2<br />
+ C282<br />
330uF @ 10V<br />
+ C283<br />
330uF @ 10V<br />
+<br />
VCC1V5<br />
C284<br />
330uF @ 10V<br />
165 1%<br />
330uF @ 10V<br />
12<br />
VSSP<br />
TEST<br />
17<br />
C 13<br />
VCC2DET PWRGD<br />
16<br />
1V5GOOD<br />
C<br />
X2<br />
POWER SUPPLY<br />
X3<br />
J12<br />
POWER SWITCH<br />
C288<br />
1<br />
FB1<br />
FB2<br />
28<br />
C289<br />
BAT54S<br />
POWER<br />
VCC5V0<br />
0.1uF<br />
2<br />
CREF<br />
CP<br />
27<br />
R160<br />
POWER<br />
SW1<br />
C290<br />
33pF<br />
3<br />
CSLOPE<br />
C2V<br />
26<br />
1uF @ 20V<br />
3<br />
B<br />
R161<br />
220 5%<br />
+ C291<br />
330uF @ 10V<br />
+ C292<br />
330uF @ 10V<br />
+ C293<br />
330uF @ 10V<br />
C294<br />
R163<br />
330pF<br />
4<br />
5<br />
6<br />
COSC<br />
VDD<br />
VIN<br />
VSS<br />
VHI<br />
LX<br />
25<br />
24<br />
23<br />
20.0 1%<br />
C296<br />
R162<br />
39.2 1%<br />
2 1<br />
D23<br />
BAT54S<br />
C295<br />
0.22uF<br />
B<br />
D24<br />
5 VOLTS OK<br />
GREEN<br />
VCC5V0<br />
+<br />
5.11 1%<br />
C300<br />
7<br />
8<br />
9<br />
VSSP<br />
VIN<br />
VSSP<br />
LX<br />
LX<br />
LX<br />
22<br />
21<br />
20<br />
1<br />
0.1uF L10<br />
2.5uH<br />
PE-53681<br />
2<br />
+ C297<br />
330uF @ 10V<br />
+ C298<br />
330uF @ 10V<br />
+<br />
VCC3V3<br />
C299<br />
330uF @ 10V<br />
VCC3V3<br />
R164<br />
130 5%<br />
VCC3V3<br />
R165<br />
130 5%<br />
VCC3V3<br />
+ C301<br />
330uF @ 10V<br />
330uF @ 10V<br />
1uF 25V<br />
C487<br />
+ C302<br />
1uF @ 20V<br />
10<br />
11<br />
12<br />
VSSP<br />
VSSP<br />
VSSP<br />
VSSP<br />
VSSP<br />
TEST<br />
19<br />
18<br />
17<br />
D25 3.3 VOLTS OK<br />
D26<br />
1.5 VOLTS OK<br />
R166<br />
130 5%<br />
13<br />
14<br />
VCC2DET<br />
OUTEN<br />
PWRGD<br />
OT<br />
16<br />
15<br />
3V3GOOD<br />
X4<br />
X5<br />
X6<br />
X7<br />
X8<br />
X9<br />
GREEN<br />
POWER_CORD<br />
GREEN<br />
R159<br />
5K1 5%<br />
R150<br />
14<br />
OUTEN OT<br />
15<br />
D27<br />
EL7556BC<br />
R151<br />
SYSTEMACE POWER OK<br />
+<br />
R157<br />
A<br />
GREEN<br />
VCC5V0<br />
R167<br />
EL7556BC<br />
BUMPONS BUMPONS BUMPONS BUMPONS BUMPONS BUMPONS<br />
A<br />
3V3_OK_Z<br />
1V5_OK_Z<br />
2V5_OK_Z<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
5K1 5%<br />
100 1%<br />
3<br />
3<br />
D19<br />
R158<br />
232 1%<br />
U15<br />
1<br />
VCC5V0<br />
2<br />
2<br />
+<br />
Title<br />
3<br />
D22<br />
D20<br />
S1A<br />
POWER SUPPLIES<br />
1<br />
2<br />
VCC5V0<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
25 of 35<br />
1<br />
VCC_CORE
5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
YELLOW<br />
YELLOW<br />
C C<br />
PB4<br />
PB7<br />
B B<br />
A PB10<br />
A<br />
RED<br />
BLUE<br />
BLUE<br />
BLUE<br />
BLUE<br />
BLUE<br />
BLUE<br />
BLUE<br />
BLUE<br />
PB3<br />
PB11<br />
VCC3V3<br />
PB1<br />
PB2<br />
PB4<br />
PB5<br />
PB6<br />
PB7<br />
PB8<br />
PB9<br />
PB10<br />
R170<br />
3K0 5%<br />
R171<br />
3K0 5%<br />
R172<br />
3K0 5%<br />
R173<br />
3K0 5%<br />
R174<br />
3K0 5%<br />
R175<br />
3K0 5%<br />
R176<br />
3K0 5%<br />
3<br />
R177<br />
3K0 5%<br />
R178<br />
3K0 5%<br />
R168<br />
3K0 5%<br />
PB11<br />
R169<br />
3K0 5%<br />
PB1<br />
PB2<br />
PB3<br />
PB5<br />
PB6<br />
PB8<br />
PB9<br />
2<br />
2<br />
Title<br />
XILINX INC.<br />
2100 Logic Drive San Jose California USA 95124<br />
PUSHBUTTONS<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
26 of 35<br />
1
5<br />
VCC5V0<br />
L11<br />
GND<br />
4<br />
VGA_VCC<br />
VGA_VCC<br />
3<br />
D<br />
R179<br />
VGA_GND<br />
J6<br />
D<br />
U16<br />
75.0 1% R180<br />
75.0 1%<br />
R181<br />
75.0 1%<br />
VGA_RED_OUT<br />
VGA_GREEN_OUT<br />
VGA_BLUE_OUT<br />
1<br />
2<br />
3<br />
4<br />
5<br />
C<br />
VGA_OUT_RED0<br />
VGA_OUT_RED1<br />
VGA_OUT_RED2<br />
VGA_OUT_RED3<br />
VGA_OUT_RED4<br />
VGA_OUT_RED5<br />
VGA_OUT_RED6<br />
VGA_OUT_RED7<br />
VGA_OUT_GREEN0<br />
VGA_OUT_GREEN1<br />
VGA_OUT_GREEN2<br />
VGA_OUT_GREEN3<br />
VGA_OUT_GREEN4<br />
VGA_OUT_GREEN5<br />
VGA_OUT_GREEN6_YCrCb0<br />
VGA_OUT_GREEN7_YCrCb1<br />
40<br />
41<br />
42<br />
43<br />
44<br />
45<br />
46<br />
47<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
R0<br />
R1<br />
R2<br />
R3<br />
R4<br />
R5<br />
R6<br />
R7<br />
G0<br />
G1<br />
G2<br />
G3<br />
G4<br />
G5<br />
G6<br />
G7<br />
IOR<br />
IOG<br />
33<br />
32<br />
VGA_HSYNCH<br />
VGA_VSYNCH<br />
R182<br />
82.5 1%<br />
R183<br />
82.5 1%<br />
VGA_GND<br />
6<br />
7<br />
8<br />
9 VGA OUTPUT<br />
10<br />
11<br />
12<br />
13<br />
14<br />
15<br />
HD-15PIN VGA DSUB<br />
C<br />
VGA_OUT_BLUE0_YCrCb2<br />
VGA_OUT_BLUE1_YCrCb3<br />
VGA_OUT_BLUE2_YCrCb4<br />
VGA_OUT_BLUE3_YCrCb5<br />
VGA_OUT_BLUE4_YCrCb6<br />
VGA_OUT_BLUE5_YCrCb7<br />
VGA_OUT_BLUE6_YCrCb8<br />
VGA_OUT_BLUE7_YCbCr9<br />
16<br />
17<br />
18<br />
19<br />
20<br />
21<br />
22<br />
23<br />
B0<br />
B1<br />
B2<br />
B3<br />
B4<br />
B5<br />
B6<br />
B7<br />
IOB<br />
29<br />
C303<br />
VGA_VCC<br />
VGA_VCC<br />
R184<br />
VGA_COMP_SYNCH<br />
11<br />
SYNC<br />
COMP<br />
34<br />
0.1uF<br />
VGA_VREF<br />
R185 VGA_OUT_BLANK_Z<br />
10<br />
BLANK<br />
VREF<br />
35<br />
R186<br />
VGA_OUT_PIXEL_CLOCK<br />
20.0 1%<br />
VGA_VCC<br />
26<br />
CLOCK<br />
RREF<br />
36<br />
590 1%<br />
C304<br />
0.1uF<br />
D28<br />
3<br />
B<br />
R187<br />
3K0 5%<br />
12<br />
30<br />
31<br />
13<br />
24<br />
25<br />
37<br />
VCC<br />
VCC<br />
VCC<br />
NC<br />
NC<br />
NC<br />
NC<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
1<br />
14<br />
15<br />
27<br />
28<br />
38<br />
39<br />
48<br />
VGA_GND<br />
VGA_GND<br />
REQUIRED FOR ANLOG<br />
DEVICES DAC ONLY<br />
B<br />
TRIPLE 8 BIT<br />
VIDEO DAC<br />
FMS3810<br />
A +<br />
FERRITE BEAD<br />
2743001112<br />
C305<br />
33uF @ 16V<br />
+ C306<br />
10uF @ 16V<br />
C307<br />
0.1uF<br />
C308<br />
0.1uF<br />
C309<br />
0.1uF<br />
A<br />
L12<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
VGA_GND<br />
Title<br />
GND<br />
FERRITE BEAD<br />
2743001112<br />
VGA_GND<br />
SVGA OUTPUT<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 27 of 35<br />
5<br />
4<br />
3<br />
2<br />
1<br />
2 1<br />
2<br />
1
5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
VCC3V3<br />
SYSTEMACE CAPS<br />
C C<br />
VCC_CORE<br />
C243<br />
0.1uF<br />
C244<br />
0.1uF<br />
SYSTEMACE CAPS<br />
B B<br />
C260<br />
0.1uF<br />
C261<br />
0.1uF<br />
C245<br />
0.1uF<br />
C262<br />
0.1uF<br />
C246<br />
0.1uF<br />
C263<br />
0.1uF<br />
C247<br />
0.1uF<br />
C264<br />
0.1uF<br />
C248<br />
0.1uF<br />
C265<br />
0.1uF<br />
C249<br />
0.1uF<br />
C266<br />
0.1uF<br />
C250<br />
0.1uF<br />
C267<br />
0.1uF<br />
+ C235<br />
47uF @ 16V<br />
+ C251<br />
47uF @ 16V<br />
A A<br />
3<br />
+ C236<br />
47uF @ 16V<br />
+ C252<br />
47uF @ 16V<br />
+ C237<br />
47uF @ 16V<br />
+ C253<br />
47uF @ 16V<br />
+ C238<br />
47uF @ 16V<br />
+ C254<br />
47uF @ 16V<br />
2<br />
+ C239<br />
47uF @ 16V<br />
+ C255<br />
47uF @ 16V<br />
2<br />
+ C240<br />
47uF @ 16V<br />
+ C256<br />
47uF @ 16V<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
Title<br />
+ C241<br />
47uF @ 16V<br />
+ C257<br />
47uF @ 16V<br />
SYSTEMACE CONTROLLER CAPS<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
28 of 35<br />
1<br />
+ C242<br />
47uF @ 16V<br />
+ C258<br />
47uF @ 16V<br />
+ C259<br />
470uF @ 10V
5<br />
5<br />
COMPACT FLASH CONNECTOR<br />
4<br />
4<br />
CFD[0..15]<br />
3<br />
D<br />
C<br />
CFA10<br />
CFA9<br />
CFA8<br />
CFA7<br />
CFA6<br />
CFA5<br />
CFA4<br />
CFA3<br />
CFA2<br />
CFA1<br />
CFA0<br />
CFD3<br />
CFD4<br />
CFD5<br />
CFD6<br />
CFD7<br />
CFD0<br />
CFD1<br />
CFD2<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10<br />
11<br />
12<br />
13<br />
14<br />
15<br />
16<br />
17<br />
18<br />
19<br />
20<br />
21<br />
22<br />
23<br />
24<br />
25<br />
CF_CON<br />
26<br />
27<br />
28<br />
29<br />
30<br />
31<br />
32<br />
33<br />
34<br />
35<br />
36<br />
37<br />
38<br />
39<br />
40<br />
41<br />
42<br />
43<br />
44<br />
45<br />
46<br />
47<br />
48<br />
49<br />
50<br />
CFD11<br />
CFD12<br />
CFD13<br />
CFD14<br />
CFD15<br />
IORDZ<br />
IOWRZ<br />
CSELZ<br />
CFRESET<br />
CFD8<br />
CFD9<br />
CFD10<br />
VCC3V3<br />
R100<br />
3K0 5%<br />
R101<br />
3K0 5%<br />
R98<br />
3K0 5%<br />
R99<br />
3K0 5%<br />
CFA[0..10]<br />
VCC3V3<br />
CFD15<br />
CFD14<br />
CFD13<br />
CFD12<br />
CFD11<br />
CFD10<br />
CFD9<br />
CFD8<br />
CFD7<br />
CFD6<br />
CFD5<br />
CFD4<br />
CFD3<br />
CFD2<br />
CFD1<br />
CFD0<br />
CFA10<br />
CFA9<br />
CFA8<br />
CFA7<br />
CFA6<br />
CFA5<br />
CFA4<br />
CFA3<br />
CFA2<br />
CFA1<br />
CFA0<br />
118<br />
116<br />
114<br />
107<br />
105<br />
12<br />
11<br />
7<br />
117<br />
115<br />
113<br />
106<br />
104<br />
8<br />
6<br />
5<br />
121<br />
125<br />
130<br />
132<br />
134<br />
135<br />
137<br />
139<br />
141<br />
142<br />
4<br />
CFD15<br />
CFD14<br />
CFD13<br />
CFD12<br />
CFD11<br />
CFD10<br />
CFD09<br />
CFD08<br />
CFD07<br />
CFD06<br />
CFD05<br />
CFD04<br />
CFD03<br />
CFD02<br />
CFD01<br />
CFD00<br />
CFA10<br />
CFA09<br />
CFA08<br />
CFA07<br />
CFA06<br />
CFA05<br />
CFA04<br />
CFA03<br />
CFA02<br />
CFA01<br />
CFA00<br />
D<br />
C<br />
B B<br />
CF_REG_Z<br />
3<br />
CFREG<br />
X1<br />
J15<br />
VCC3V3<br />
R232<br />
R228<br />
3K0 5%<br />
R103<br />
3K0 5%<br />
R104<br />
R102<br />
3K0 5%<br />
3K0 5%<br />
COMPACT FLASH CARD<br />
A SYSTEM ACE CONTROLLER U28B<br />
A<br />
SW4<br />
SW DIP-3<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
CONFIGURATION<br />
SELECT<br />
3<br />
CF_CARD_DETECT2_Z<br />
CF_CARD_DETECT1_Z<br />
CF_READY_BUSY<br />
CF_WAIT_Z<br />
CF_OE_Z<br />
CF_WE_Z<br />
CF_CE1_Z<br />
CF_CE2_Z<br />
CFG_ADDR2<br />
CFG_ADDR1<br />
CFG_ADDR0<br />
13<br />
103<br />
133<br />
140<br />
123<br />
131<br />
119<br />
138<br />
88<br />
87<br />
86<br />
CFCD2<br />
CFCD1<br />
CFRDYBSY<br />
CFWAIT<br />
CFOE<br />
CFWE<br />
CFCE1<br />
CFCE2<br />
CFGADDR2<br />
CFGADDR1<br />
CFGADDR0<br />
SystemACE<br />
CONTROLLER<br />
2<br />
2<br />
Title<br />
SYSTEMACE COMPACT FLASH PORT<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
29 of 35<br />
1
5<br />
5<br />
VCC3V3<br />
R229<br />
3K0 5%<br />
R230<br />
3K0 5%<br />
R231<br />
3K0 5%<br />
4<br />
4<br />
R107<br />
3K0 5%<br />
R105<br />
3K0 5%<br />
3<br />
MPD[0..15]<br />
D D<br />
TSTTDO<br />
TSTTMS<br />
TSTTCK<br />
TSTTDI<br />
97<br />
98<br />
101<br />
102<br />
TSTTDO<br />
TSTTMS<br />
TSTTCK<br />
TSTTDI<br />
MPA00<br />
MPA01<br />
MPA02<br />
MPA03<br />
MPA04<br />
MPA05<br />
MPA06<br />
70<br />
69<br />
68<br />
67<br />
45<br />
44<br />
43<br />
MPA0<br />
MPA1<br />
MPA2<br />
MPA3<br />
MPA4<br />
MPA5<br />
MPA6<br />
MPD0<br />
MPD1<br />
MPD2<br />
MPD3<br />
MPD4<br />
MPD5<br />
MPD6<br />
MPD7<br />
MPD8<br />
MPD9<br />
C<br />
HC3_CFGINIT<br />
HC3_CFGPROGZ<br />
HC3_CFGTMS<br />
HC3_CFGTCK<br />
HC3_CFGTDI<br />
HC3_CFGTDO<br />
R109<br />
56.2 1%<br />
R112<br />
56.2 1%<br />
R110<br />
56.2 1%<br />
R111<br />
56.2 1%<br />
78<br />
79<br />
85<br />
80<br />
81<br />
82<br />
16<br />
124<br />
CFGINIT0<br />
CFGPROG0<br />
CFGTMS0<br />
CFGTCK0<br />
CFGTDI0<br />
CFGTDO0<br />
CFGINIT3<br />
CFGPROG3<br />
MPD00<br />
MPD01<br />
MPD02<br />
MPD03<br />
MPD04<br />
MPD05<br />
MPD06<br />
MPD07<br />
MPD08<br />
MPD09<br />
MPD10<br />
MPD11<br />
MPD12<br />
MPD13<br />
MPD14<br />
MPD15<br />
66<br />
65<br />
63<br />
62<br />
61<br />
60<br />
59<br />
58<br />
56<br />
53<br />
52<br />
51<br />
50<br />
49<br />
48<br />
47<br />
MPD0<br />
MPD1<br />
MPD2<br />
MPD3<br />
MPD4<br />
MPD5<br />
MPD6<br />
MPD7<br />
MPD8<br />
MPD9<br />
MPD10<br />
MPD11<br />
MPD12<br />
MPD13<br />
MPD14<br />
MPD15<br />
MPD10<br />
MPD11<br />
MPD12<br />
MPD13<br />
MPD14<br />
MPD15<br />
MPA0<br />
MPA1<br />
MPA2<br />
MPA3<br />
MPA4<br />
MPA5<br />
MPA6<br />
C<br />
J11<br />
20<br />
CFGTDI3<br />
MPWE<br />
76<br />
MPWE_Z<br />
JTAG<br />
PORT<br />
TEST<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
VCC3V3<br />
TSTTDO<br />
TSTTDI<br />
TSTTCK<br />
TSTTMS<br />
122<br />
19<br />
22<br />
CFGTDO3<br />
CFGINIT2<br />
CFGPROG2<br />
MPOE<br />
MPIRQ<br />
MPBRDY<br />
77<br />
41<br />
39<br />
D17 SYSTEMACE ERROR<br />
R116<br />
MPOE_Z<br />
MPIRQ<br />
MPBRDY<br />
JTAG_PROG_CON<br />
23<br />
CFGTMS2<br />
ERRLED<br />
96 HC3_ERROR<br />
B 24<br />
27<br />
CFGTCK2<br />
CFGTDI2<br />
STATLED<br />
95 HC3_STATUS<br />
RED<br />
D18 SYSTEMACE STATUS<br />
130 5%<br />
R118<br />
VCC3V3<br />
B<br />
21<br />
CFGTDO2<br />
RESET<br />
33<br />
GREEN<br />
130 5%<br />
HC3_RESET_Z<br />
VCC3V3<br />
R108<br />
3K0 5%<br />
R121<br />
R106<br />
3K0 5%<br />
127<br />
14<br />
90<br />
29<br />
30<br />
31<br />
32<br />
28<br />
89<br />
CFGTMS3<br />
CFGTCK3<br />
CFGINIT1<br />
CFGPROG1<br />
CFGTMS1<br />
CFGTCK1<br />
CFGTDI1<br />
CFGTDO1<br />
CFGMODE<br />
3K0 5%<br />
A A<br />
SYSTEM ACE CONTROLLER<br />
3<br />
U28A<br />
SystemACE<br />
CONTROLLER<br />
MPCE<br />
CLK<br />
42<br />
93<br />
2<br />
2<br />
Title<br />
MPA[0..6]<br />
XILINX INC.<br />
2100 Logic Drive San Jose California USA 95124<br />
SYSTEMACE MICRO PORT & JTAG TEST PORT<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
30 of 35<br />
1<br />
MPCE_Z<br />
HC3_SYSTEM_CLOCK
5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
VCC_CORE<br />
C GND<br />
100<br />
C<br />
VCC3V3<br />
U28C<br />
SystemACE<br />
CONTROLLER<br />
10<br />
VCCL GND<br />
9<br />
15<br />
25<br />
57<br />
84<br />
94<br />
99<br />
126<br />
1<br />
17<br />
37<br />
55<br />
73<br />
92<br />
109<br />
128<br />
B<br />
34<br />
NC<br />
NC<br />
40<br />
B<br />
36<br />
NC<br />
POR_BYPASS<br />
108<br />
143<br />
2<br />
VCCL<br />
VCCL<br />
VCCL<br />
VCCL<br />
VCCL<br />
VCCL<br />
VCCL<br />
VCCH<br />
VCCH<br />
VCCH<br />
VCCH<br />
VCCH<br />
VCCH<br />
VCCH<br />
VCCH<br />
NC<br />
NC<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
POR_TEST<br />
POR_RESET<br />
NC<br />
NC<br />
GND<br />
GND<br />
SYSTEM ACE CONTROLLER<br />
18<br />
26<br />
35<br />
46<br />
54<br />
64<br />
75<br />
83<br />
91<br />
111<br />
120<br />
129<br />
136<br />
144<br />
74<br />
72<br />
38<br />
71<br />
112<br />
110<br />
A A<br />
3<br />
2<br />
2<br />
Title<br />
XILINX INC.<br />
2100 Logic Drive San Jose California USA 95124<br />
SYSTEMACE CONTROLLER POWER<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
31 of 35<br />
1
5<br />
5<br />
4<br />
4<br />
3<br />
U18<br />
J4<br />
U17<br />
D<br />
DAC_A<br />
R190<br />
604 1%<br />
L15<br />
15 uH<br />
L16<br />
470 nH<br />
C311<br />
22pF<br />
R191<br />
604 1%<br />
3<br />
2<br />
+<br />
-<br />
6<br />
AD8051AR<br />
R242<br />
75.0 1%<br />
1 GREEN<br />
BNC<br />
DAC_D<br />
R188<br />
604 1%<br />
L13<br />
15 uH<br />
L14<br />
470 nH<br />
C310<br />
22pF<br />
R189<br />
604 1%<br />
3<br />
2<br />
+<br />
-<br />
6<br />
AD8051AR<br />
R259<br />
75.0 1%<br />
2<br />
3<br />
1<br />
J2A<br />
RCA<br />
COMP<br />
VIDEO<br />
D<br />
TV_GND<br />
DAC_B<br />
R194<br />
L19<br />
15 uH<br />
L20<br />
470 nH<br />
C313<br />
R195<br />
3<br />
2<br />
+<br />
-<br />
U20<br />
6<br />
R248<br />
75.0 1%<br />
1<br />
J5<br />
BLUE<br />
BNC<br />
DAC_E<br />
R192<br />
604 1%<br />
L17<br />
15 uH<br />
L18<br />
470 nH<br />
C312<br />
22pF<br />
R193<br />
604 1%<br />
3<br />
2<br />
+<br />
-<br />
6<br />
AD8051AR<br />
R247<br />
75.0 1%<br />
C<br />
604 1%<br />
22pF<br />
604 1%<br />
AD8051AR<br />
R249<br />
TV_VEE<br />
R250<br />
C<br />
TV_GND<br />
TV_VEE<br />
TV_GND<br />
R251<br />
R252<br />
619 1%<br />
619 1%<br />
TV_GND<br />
619 1%<br />
619 1%<br />
C491<br />
R262<br />
3<br />
J18<br />
C492<br />
R263<br />
2K0 5%<br />
4.7pF<br />
2K0 5%<br />
TV_VAA<br />
1<br />
S<br />
VIDEO<br />
4.7pF<br />
TV_VAA<br />
2<br />
DAC_C<br />
R198<br />
L23<br />
15 uH<br />
L24<br />
470 nH<br />
R199<br />
3<br />
2<br />
+<br />
-<br />
U22<br />
6<br />
R254<br />
75.0 1%<br />
1<br />
J3<br />
BNC<br />
RED<br />
DAC_F<br />
R196<br />
L21<br />
15 uH<br />
L22<br />
470 nH<br />
C314<br />
R197<br />
3<br />
2<br />
+<br />
-<br />
U21<br />
6<br />
R253<br />
75.0 1%<br />
4<br />
TV_GND<br />
604 1%<br />
C315<br />
22pF<br />
604 1%<br />
AD8051AR<br />
604 1%<br />
22pF<br />
604 1%<br />
AD8051AR<br />
B<br />
TV_VEE<br />
TV_GND<br />
R255<br />
TV_VEE<br />
R256<br />
B<br />
R257<br />
R258<br />
TV_GND<br />
TV_VAA<br />
+ C319<br />
10uF @ 16V<br />
TV_GND<br />
TV_VEE<br />
R244<br />
4.7pF<br />
TV_VAA<br />
TV_GND<br />
A 0.01uF 0.1uF<br />
0.01uF 0.1uF<br />
0.01uF 0.1uF<br />
TV_GND<br />
A<br />
+ C337<br />
+ C338<br />
+ C339<br />
C346 C347 10uF @ 16V C348 C349 10uF @ 16V C350 C351<br />
10uF @ 16V<br />
TV_VEE<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
0.01uF 0.1uF<br />
0.01uF 0.1uF<br />
0.01uF 0.1uF<br />
TV_GND<br />
Title<br />
TV_VEE<br />
C328<br />
0.1uF<br />
C329<br />
0.01uF<br />
R243<br />
619 1%<br />
+ C320<br />
10uF @ 16V<br />
7<br />
4<br />
TV_VAA<br />
619 1%<br />
C490<br />
7<br />
4<br />
619 1%<br />
C330<br />
0.1uF<br />
R261<br />
2K0 5%<br />
C331<br />
0.01uF<br />
7<br />
4<br />
C494<br />
4.7pF<br />
619 1%<br />
R265<br />
2K0 5%<br />
+ C321<br />
10uF @ 16V<br />
2<br />
2<br />
C332<br />
0.1uF<br />
2<br />
C333<br />
0.01uF<br />
3<br />
C340<br />
TV_GND<br />
TV_VAA<br />
+ C316<br />
10uF @ 16V<br />
C341<br />
C322<br />
0.1uF<br />
+ C334<br />
10uF @ 16V<br />
C323<br />
0.01uF<br />
7<br />
4<br />
C342<br />
2<br />
TV_VAA<br />
2<br />
R245<br />
619 1%<br />
619 1%<br />
U19<br />
+ C317<br />
10uF @ 16V<br />
C343<br />
TV_VEE<br />
7<br />
4<br />
7<br />
4<br />
+ C335<br />
TV_VAA<br />
619 1%<br />
C489<br />
4.7pF<br />
619 1%<br />
C493<br />
4.7pF<br />
C324<br />
0.1uF<br />
R246<br />
10uF @ 16V<br />
R260<br />
2K0 5%<br />
R264<br />
2K0 5%<br />
C325<br />
0.01uF<br />
+ C318<br />
10uF @ 16V<br />
C344<br />
C345<br />
PAL_NTSC TV OUTPUT<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
32 of 35<br />
1<br />
TV_GND<br />
Y<br />
C<br />
C326<br />
0.1uF<br />
GND<br />
C327<br />
0.01uF<br />
+ C336<br />
10uF @ 16V
5<br />
4<br />
3<br />
J1A<br />
C352<br />
U23<br />
D<br />
COMP<br />
VIDEO RCA<br />
S<br />
VIDEO<br />
2 CHAN1_COMP_VIDEO_IN<br />
CHAN1_COMP<br />
3<br />
R202<br />
1<br />
75.0 1%<br />
0.1uF<br />
CHAN1_Y<br />
AVSS<br />
AVSS<br />
C353<br />
J19 3<br />
CHAN1_LUMA_IN<br />
1<br />
R211 0.1uF<br />
75.0 1%<br />
C354<br />
CHAN1_C<br />
2<br />
0.1uF<br />
AVSS<br />
AVSS 4<br />
42<br />
41<br />
44<br />
43<br />
46<br />
45<br />
58<br />
57<br />
60<br />
59<br />
62<br />
AIN1<br />
AIN_GND1<br />
AIN2<br />
AIN_GND2<br />
AIN3<br />
AIN_GND3<br />
AIN4<br />
AIN_GND4<br />
AIN5<br />
AIN_GND5<br />
AIN6<br />
P19<br />
P18<br />
P17<br />
P16<br />
P15<br />
P14<br />
P13<br />
P12<br />
P11<br />
P10<br />
P9<br />
P8<br />
P7<br />
P6<br />
P5<br />
P4<br />
P3<br />
P2<br />
P1<br />
P0<br />
73<br />
74<br />
75<br />
76<br />
5<br />
6<br />
7<br />
8<br />
17<br />
18<br />
19<br />
20<br />
21<br />
22<br />
23<br />
24<br />
32<br />
33<br />
34<br />
35<br />
R200<br />
20.0 1%<br />
R206<br />
20.0 1%<br />
R201<br />
20.0 1%<br />
R207<br />
20.0 1%<br />
R203<br />
20.0 1%<br />
R208<br />
20.0 1%<br />
R212<br />
3K0 5%<br />
R204<br />
20.0 1%<br />
R209<br />
20.0 1%<br />
R213<br />
3K0 5%<br />
R205<br />
20.0 1%<br />
R210<br />
20.0 1%<br />
VCC3V3<br />
CHAN1_VIDEO_DATA9<br />
CHAN1_VIDEO_DATA8<br />
CHAN1_VIDEO_DATA7<br />
CHAN1_VIDEO_DATA6<br />
CHAN1_VIDEO_DATA5<br />
CHAN1_VIDEO_DATA4<br />
CHAN1_VIDEO_DATA3<br />
CHAN1_VIDEO_DATA2<br />
CHAN1_VIDEO_DATA1<br />
CHAN1_VIDEO_DATA0<br />
D<br />
AVSS<br />
CHAN1_CHROMA_IN R214<br />
61<br />
AIN_GND6<br />
XTAL1<br />
28<br />
GND<br />
Y C<br />
75.0 1%<br />
XTAL<br />
29<br />
R215<br />
VIDEO_DECODER_CLOCK<br />
C<br />
C355<br />
10uF<br />
C356<br />
0.1uF<br />
C357<br />
AVSS<br />
AVSS<br />
51<br />
52<br />
REFOUT<br />
CML<br />
SCLOCK<br />
SDATA<br />
READ<br />
DATA_VALID<br />
68<br />
67<br />
77<br />
78<br />
100 1%<br />
R216<br />
100 1%<br />
CHAN1_I2C_CLOCK<br />
CHAN1_I2C_DATA<br />
C<br />
C358<br />
AVSS<br />
AVSS<br />
0.1uF<br />
48<br />
49<br />
CAPY1<br />
CAPY2<br />
OE<br />
VREF<br />
HREF<br />
79<br />
69<br />
70<br />
0.1uF<br />
C361<br />
C359<br />
10uF<br />
C360<br />
0.1uF<br />
54<br />
55<br />
CAPC1<br />
CAPC2<br />
LLCREF<br />
LLC2<br />
LLC1<br />
25<br />
26<br />
27<br />
R217<br />
20.0 1%<br />
R218<br />
CHAN1_LINE_LOCK_CLOCK2<br />
AVSS<br />
0.1uF<br />
AVSS<br />
C362<br />
DVDD<br />
VCC3V3<br />
AVDD<br />
30<br />
10<br />
72<br />
4<br />
15<br />
DVDD<br />
DVDD<br />
DVDD<br />
DVDDIO<br />
DVDDIO<br />
AEF<br />
HFF<br />
AFF<br />
13<br />
12<br />
11<br />
20.0 1%<br />
CHAN1_LINE_LOCK_CLOCK1<br />
B<br />
0.1uF<br />
C365<br />
0.1uF<br />
C363<br />
10uF<br />
C364<br />
0.1uF<br />
PVDD<br />
PVSS<br />
50<br />
38<br />
39<br />
40<br />
47<br />
53<br />
56<br />
63<br />
AVDD<br />
AVDD<br />
AVSS<br />
AVSS<br />
AVSS<br />
AVSS<br />
AVSS<br />
AVSS<br />
CLKIN<br />
FIELD<br />
HS<br />
VS<br />
ISO<br />
16<br />
80<br />
2<br />
1<br />
65<br />
GND<br />
I2C ADDRESS 8AH for WRITES<br />
I2C ADDRESS 8BH for READS<br />
CHAN1_ISO<br />
B<br />
AVSS AVSS<br />
L25<br />
AVDD<br />
AVSS<br />
31<br />
9<br />
71<br />
3<br />
14<br />
DVSS<br />
DVSS<br />
DVSS<br />
DVSSIO<br />
DVSSIO<br />
RESET<br />
PWRDN<br />
ALSB<br />
64<br />
36<br />
66<br />
VCC3V3<br />
VIDEO_DECODER_RESET_Z<br />
PVDD<br />
VCC5V0<br />
+ C366 FERRITE BEAD<br />
33uF @ 16V2961666671<br />
L27<br />
+ C367<br />
10uF @ 16V<br />
C368<br />
0.1uF<br />
C369<br />
0.01uF<br />
GND<br />
ELPF<br />
VIDEO DECODER<br />
ADV7185<br />
37<br />
R219<br />
5K62 1%<br />
VCC5V0<br />
+<br />
L26<br />
FERRITE BEAD<br />
C373 2961666671<br />
33uF @ 16V<br />
+ C370<br />
10uF @ 16V<br />
C371<br />
0.1uF<br />
C372<br />
0.01uF<br />
C374<br />
L28<br />
FERRITE BEAD<br />
2961666671<br />
AVSS<br />
DVDD<br />
68pF<br />
A<br />
VCC3V3<br />
GND<br />
L29<br />
VCC3V3<br />
C375<br />
2.2nF<br />
PVDD<br />
GND<br />
FERRITE BEAD<br />
2961666671<br />
XILINX INC.<br />
PVSS<br />
2100 Logic Drive San Jose California USA 95124<br />
A<br />
+<br />
FERRITE BEAD<br />
C3872961666671<br />
33uF @ 16V<br />
+ C376<br />
10uF @ 16V<br />
C377<br />
0.1uF<br />
C378<br />
0.01uF<br />
C379<br />
0.1uF<br />
C380<br />
0.01uF<br />
C381<br />
0.1uF<br />
C382<br />
0.01uF<br />
C383<br />
0.1uF<br />
C384<br />
0.01uF<br />
C385<br />
0.1uF<br />
C386<br />
0.01uF<br />
Title<br />
VIDEO DECODER<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong> 01<br />
GND<br />
Rick Ballantyne Xilinx Labs<br />
Date: Tuesday, October 22, 2002 Sheet 33 of 35<br />
5<br />
4<br />
3<br />
2<br />
1<br />
2<br />
1
5<br />
4<br />
TV_VAA<br />
3<br />
D 0.1uF 0.1uF<br />
U24<br />
D<br />
C390<br />
0.1uF<br />
C391<br />
0.01uF<br />
C392<br />
0.1uF<br />
C393<br />
0.01uF<br />
C394<br />
0.1uF<br />
C395<br />
0.01uF<br />
C396<br />
0.1uF<br />
C397<br />
0.01uF<br />
TV_VAA<br />
GND<br />
C388<br />
C389<br />
57<br />
VREF<br />
56<br />
COMP1<br />
45<br />
38<br />
48<br />
53<br />
21<br />
34<br />
I2C ADDRESS 56H for WRITES<br />
I2C ADDRESS 57H for READS<br />
75<br />
Cb0<br />
DAC_A<br />
55<br />
DAC_A<br />
76<br />
Cb1<br />
77<br />
Cb2<br />
DAC_B<br />
54<br />
DAC_B<br />
78<br />
Cb3<br />
26<br />
Cb4<br />
DAC_C<br />
51<br />
DAC_C<br />
27<br />
Cb5<br />
28<br />
Cb6 PAL_NTSC DAC_D<br />
50<br />
DAC_D<br />
29<br />
Cb7<br />
30<br />
Cb8 VIDEO<br />
DAC_E<br />
47<br />
DAC_E<br />
31<br />
Cb9 ENCODER<br />
DAC_F<br />
46<br />
DAC_F<br />
63<br />
Cr0<br />
64<br />
Cr1<br />
R220<br />
65<br />
Cr2<br />
66<br />
Cr3<br />
RSET1<br />
58<br />
TV_GND<br />
67<br />
Cr4<br />
VCC3V3<br />
C 70<br />
Cr5<br />
C<br />
1K21 1% R223<br />
71<br />
R221 R222<br />
Cr6<br />
RSET2<br />
44<br />
72<br />
3K0 5% 3K0 5%<br />
Cr7<br />
73<br />
Cr8<br />
74<br />
ADV7194KST<br />
R224<br />
Cr9<br />
1K21 1%<br />
SCL<br />
39<br />
VIDEO_ENCODER_SCLK<br />
100 1%<br />
VGA_OUT_GREEN6_YCrCb0<br />
1<br />
P0<br />
R225<br />
VGA_OUT_GREEN7_YCrCb1<br />
2<br />
P1<br />
SDATA<br />
40<br />
VIDEO_ENCODER_DATA<br />
100 1%<br />
VGA_OUT_BLUE0_YCrCb2<br />
3<br />
P2<br />
VGA_OUT_BLUE1_YCrCb3<br />
4<br />
P3<br />
COMP_HSYNC_OUT<br />
61<br />
VGA_OUT_BLUE2_YCrCb4<br />
5<br />
P4<br />
VGA_OUT_BLUE3_YCrCb5<br />
6<br />
P5<br />
VSYCH_OUT<br />
62<br />
VGA_OUT_BLUE4_YCrCb6<br />
7<br />
P6<br />
VGA_OUT_BLUE5_YCrCb7<br />
8<br />
P7<br />
PAL_NTSC<br />
59<br />
TV_OUT_PAL_NTSCZ<br />
VGA_OUT_BLUE6_YCrCb8<br />
9<br />
P8<br />
VGA_OUT_BLUE7_YCbCr9<br />
10<br />
P9<br />
RESET<br />
60<br />
TV_OUT_RESET_Z<br />
B<br />
VCC3V3<br />
11<br />
12<br />
13<br />
14<br />
15<br />
16<br />
17<br />
18<br />
19<br />
20<br />
37<br />
Y0_P10<br />
Y9_P11<br />
Y9_P12<br />
Y9_P13<br />
Y9_P14<br />
Y9_P15<br />
Y9_P16<br />
Y9_P17<br />
Y9_P18<br />
Y9_P19<br />
CLKOUT<br />
HSYNC<br />
VSYNC<br />
BLANK<br />
SCRESET<br />
TTXREQ<br />
CLKIN<br />
ALSB<br />
23<br />
24<br />
25<br />
41<br />
32<br />
36<br />
42<br />
VCC3V3<br />
TV_OUT_HSYNCZ<br />
TV_OUT_VSYNCHZ<br />
TV_OUT_BLANKZ<br />
TV_OUT_SUB_CARRIER_RESET<br />
TV_OUT_CLOCK<br />
1<br />
NTE0505M<br />
U25<br />
DC-DC<br />
CONV<br />
GND NC<br />
14<br />
B<br />
VCC5V0<br />
L30<br />
3<br />
VIN NC<br />
12<br />
AGND<br />
35<br />
COMP2<br />
AGND<br />
49<br />
VAA<br />
AGND<br />
52<br />
VAA<br />
DGND<br />
22<br />
VAA<br />
DGND<br />
33<br />
VDD<br />
DGND<br />
43<br />
TV_VAA<br />
TV_GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
+ C399<br />
C400<br />
VCC3V3<br />
L31<br />
TV_VAA<br />
1uF @ 20V 0.1uF<br />
TV_VEE<br />
FERRITE BEAD<br />
2743001112<br />
NEG5V L32<br />
A + C401<br />
33uF @ 16V<br />
+ C402<br />
10uF @ 16V<br />
C403 C404 C405 C406 C407 C408<br />
47uH<br />
A<br />
L33<br />
0.1uF 0.01uF 0.1uF<br />
0.01uF 0.1uF 0.01uF<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
TV_GND<br />
Title<br />
GND<br />
FERRITE BEAD<br />
2743001112<br />
TV_GND<br />
PAL_NTSC VIDEO ENCODER<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet 34 of 35<br />
5<br />
4<br />
3<br />
2<br />
1<br />
VDD<br />
69<br />
68<br />
DGND<br />
VDD<br />
80<br />
79<br />
DGND<br />
VDD<br />
VCC3V3<br />
R240<br />
3K0 5%<br />
2<br />
47uH<br />
+ C398<br />
1uF @ 20V<br />
5<br />
7<br />
NC<br />
0V<br />
NC<br />
V+<br />
10<br />
8<br />
1
5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
VCC3V3<br />
C409<br />
0.1uF<br />
VCC3V3<br />
C424<br />
0.1uF<br />
C C<br />
VCC3V3<br />
C439<br />
0.1uF<br />
VCC3V3<br />
C454<br />
0.1uF<br />
C440<br />
0.1uF<br />
C455<br />
0.1uF<br />
C426<br />
0.1uF<br />
C444<br />
0.1uF<br />
B VCC3V3<br />
B<br />
C469<br />
0.1uF<br />
C410<br />
0.1uF<br />
C425<br />
0.1uF<br />
C470<br />
0.1uF<br />
C411<br />
0.1uF<br />
C441<br />
0.1uF<br />
C456<br />
0.1uF<br />
C471<br />
0.1uF<br />
C412<br />
0.1uF<br />
C427<br />
0.1uF<br />
C442<br />
0.1uF<br />
C457<br />
0.1uF<br />
C472<br />
0.1uF<br />
C413<br />
0.1uF<br />
C428<br />
0.1uF<br />
C443<br />
0.1uF<br />
C458<br />
0.1uF<br />
C473<br />
0.1uF<br />
C414<br />
0.1uF<br />
C429<br />
0.1uF<br />
C459<br />
0.1uF<br />
C474<br />
0.1uF<br />
C415<br />
0.1uF<br />
C430<br />
0.1uF<br />
C445<br />
0.1uF<br />
C460<br />
0.1uF<br />
C475<br />
0.1uF<br />
C416<br />
0.1uF<br />
C431<br />
0.1uF<br />
C446<br />
0.1uF<br />
C461<br />
0.1uF<br />
C476<br />
0.1uF<br />
A A<br />
3<br />
C417<br />
0.1uF<br />
C432<br />
0.1uF<br />
C447<br />
0.1uF<br />
C462<br />
0.1uF<br />
C477<br />
0.1uF<br />
C418<br />
0.1uF<br />
C433<br />
0.1uF<br />
C448<br />
0.1uF<br />
C463<br />
0.1uF<br />
C478<br />
0.1uF<br />
C419<br />
0.1uF<br />
C434<br />
0.1uF<br />
C449<br />
0.1uF<br />
C464<br />
0.1uF<br />
C479<br />
0.1uF<br />
C420<br />
0.1uF<br />
C435<br />
0.1uF<br />
C450<br />
0.1uF<br />
C465<br />
0.1uF<br />
C480<br />
0.1uF<br />
C421<br />
0.1uF<br />
C436<br />
0.1uF<br />
C451<br />
0.1uF<br />
C466<br />
0.1uF<br />
C481<br />
0.1uF<br />
2<br />
VCC3V3<br />
C422<br />
0.1uF<br />
VCC3V3<br />
C437<br />
0.1uF<br />
VCC3V3<br />
C452<br />
0.1uF<br />
VCC3V3<br />
C467<br />
0.1uF<br />
VCC3V3<br />
C482<br />
0.1uF<br />
2<br />
C423<br />
0.1uF<br />
C438<br />
0.1uF<br />
C453<br />
0.1uF<br />
C468<br />
0.1uF<br />
C483<br />
0.1uF<br />
Title<br />
XILINX INC. 2100 Logic Drive San Jose California USA 95124<br />
ZBT MEMORY CAPS<br />
Size Document Number Rev<br />
B 0381112 Microblaze & <strong>Multimedia</strong> Demonstration <strong>Board</strong><br />
Rick Ballantyne Xilinx Labs<br />
01<br />
Date: Tuesday, October 22, 2002 Sheet<br />
1<br />
35 of 35<br />
1
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