Presentation - Analysis of High-speed Differential Line on PCB ...

<strong>Analysis</strong> <strong>of</strong> <strong>High</strong>-<strong>speed</strong> <strong>High</strong> <strong>speed</strong> <strong>Differential</strong> <strong>Line</strong> on PCB using HFSS
2002. 10. 1
Terahertz Interconnection and Package Laboratory
KAIST (Korea Advanced Institute <strong>of</strong> Science and Technology)
Seungyong Baek (? ??)
Homepage : http://tera.kaist.ac.kr

Research Fields at TERA Lab. (in the view <strong>of</strong> Motherboard)
Twisted Pair on PCB/Chip
Modular Jack
EMI
Signal line across Split plane design
Spread Spectrum Clock Driver
Connector Modeling
Power Plane Design
Mixed Mode Power Plane Modeling
Split Power System Modeling
MESH Plane Modeling
Via Modeling
Crosstalk Modeling
Single <strong>Line</strong> Modeling
ESD
Embedded Passive Modeling
SMT Component Modeling
SATA
<strong>Differential</strong> <strong>Line</strong> Modeling
BGA Modeling
Adaptive Output Driver
2/31
Meander LINE
Memory Module Design
RAMBUS
WLP

Contents
� Introduction <strong>of</strong> <strong>Differential</strong> Signaling Scheme
� Characterization <strong>of</strong> <strong>Differential</strong> Signaling Scheme by Fabrication Error
� Impedance Change by Edge-Placement <strong>of</strong> <strong>High</strong>-<strong>speed</strong> <strong>Differential</strong> <strong>Line</strong>s
� An Evaluation <strong>of</strong> <strong>Differential</strong> Impedance in PCBs Using Two Single-
Ended Probes Only
� Conclusion
3/31

Introduction – Frequency Increase
Frequency [GHz]
7
6
5
4
3
2
On-chip Local Clock
(<strong>High</strong>-performance)
1
Chip-to-Board
(<strong>of</strong>f-chip) Speed (high-performance, for peripheral buses)
0
2000 2002 2004 2006 2008
Year
2010 2012 2014
Ref.) ITRS (International Technology Roadmap for Semiconductors), 2000, SIA
� Off-chip data rate should move to the range <strong>of</strong> Gb/s-per-pin
? increased complexity and cost due to massive parallelism
4/31

Introduction – Power Supply Voltage Decrease
Power Supply Voltage [V]
2.1
1.8
1.5
1.2
0.9
0.6
0.3
Minimum logic V dd (V)
for minimum power
Minimum logic V dd (V)
for maximum performance
0
2000 2002 2004 2006 2008 2010 2012 2014
Year
Ref.) ITRS (International Technology Roadmap for Semiconductors), 2000, SIA
� Reduction <strong>of</strong> power supply voltage
? power dissipation, transistor channel length, reliability <strong>of</strong> gate dielectric
5/31

Why <strong>Differential</strong> Signaling?
� Reduction <strong>of</strong> Crosstalk between Circuits
� Reduction <strong>of</strong> Simultaneous Switching Noise (SSN)
� Reduction <strong>of</strong> EMI
� Minimization <strong>of</strong> Common-mode noise
� Design <strong>of</strong> Low-voltage, Low-power
⇒ <strong>High</strong>-<strong>speed</strong> digital circuit
6/31

Objective
� Using HFSS simulation and Testing,
� A Characterization <strong>of</strong> <strong>Differential</strong> Signaling Scheme by Fabrication Error
� A Demonstration <strong>of</strong> Impedance Change by Edge-Placement <strong>of</strong> <strong>High</strong>-<strong>speed</strong>
<strong>Differential</strong> <strong>Line</strong>s
� An Evaluation <strong>of</strong> New Test Method <strong>of</strong> <strong>Differential</strong> <strong>Line</strong>s Using Two Single-
Ended Probes Only
7/31

Process Variation Problem in <strong>Differential</strong> <strong>Line</strong> Scheme
Seungyoung Ahn, Albert Chee W. Lu, Wei fan, lai L Wai, and Joungho Kim, “Solution Space <strong>Analysis</strong> <strong>of</strong> Interconnects
for Low Voltage <strong>Differential</strong> Signaling ( LVDS) Applications”, IEEE 10th Topical Meeting on Electrical Performance <strong>of</strong>
Electronic Packaging (EPEP2001), pp. 297-330, Boston, USA, Oct. 2001.
? w
? s
<strong>Differential</strong>-Mode
� Variation <strong>of</strong> fabrication error : (? w, ? s) > (? h)
Common-Mode
� Variation <strong>of</strong> fabrication error ? field change ? variation <strong>of</strong> electrical characteristics
� Variation <strong>of</strong> electrical characteristics by fabrication error
<strong>Differential</strong>-mode > Common-mode
? h
8/31

Device Under Test
DUT Width Space Width ? ?
#1
#2
#3
#4
#5
100 µm 125 µm –20 %
112.5 µm
125 µm
137.5 µm
150 µm
125 µm
125 µm
125 µm
125 µm
–10 %
0 %
10 %
20 %
� ??? ? 10%? ?? ??? ???.
???
� ?? ??? ??? ???? ???? ??
DUT Width Space Space ? ?
#6
125 µm
125 µm
125 µm
125 µm
125 µm
100 µm –20 %
112.5 µm
125 µm
137.5 µm
150 µm
???? ???? Signal line? Width? Space? ±10%, ±20% ? ?.
#7
#8
#9
#10
9/31
–10 %
0 %
10 %
20 %

Characteristic Parameters – 1.Characteristic Impedance (Z 0 )
Voltage (V)
±20% <strong>of</strong> Width variation for <strong>Differential</strong>-mode signaling
Circuit Simulation (? ? TDR Setup) Full-wave simulation
4.9 % reflection
Time (ns)
� Z <strong>Differential</strong>-mode (100 Ohm) ˜ Z Cable (50×2 = 100 Ohm) ? ? Matching.
� Width? (20%) � Reflection ? ? (4.9 %)
1 + Γref
1 + Γ
ΔZ
= Z ref − Z = 100 × −100
× ? ??, Z0 ? (10.3 %)
1 − Γref
1 − Γ
� 4.9% reflection � 10.9% Z0 ?? (full-wave Simulation),
Z 0 (Ohm)
140
120
100
80
10.9 %
100 125 150
Width (µm)
10/31

Characteristic Parameters – 1.Characteristic Impedance (Z 0 )
±20% <strong>of</strong> Width variation for Common-mode signaling
Circuit Simulation (? ? TDR Setup) Full-wave simulation
Voltage (V)
4.8 % reflection
Time (ns)
� Z Common-mode (33Ohm) > Z Cable (50/2=25Ohm)? ? ?? Mismatching
� Width? (20%) � Reflection ? ? (4.8 %)
� 4.8% reflection � 10.9 % Z 0 ?? (full-wave Simulation)
Z 0 (Ohm)
70
50
30
10
10.9 %
100 125 150
Width (µm)
11/31

Characteristic Parameters – 1.Characteristic Impedance (Z 0 )
±20% <strong>of</strong> Space variation for <strong>Differential</strong>-mode signaling
Circuit Simulation (? ? TDR Setup) Full-wave simulation
Voltage (V)
1.8 % reflection
Time (ns)
� Z <strong>Differential</strong>-mode (100 Ohm) ˜ Z Cable (50×2 = 100 Ohm) ? ? Matching.
� Space? (20%) � Reflection ? ? (1.8 %)
Z 0 (Ohm)
� 1.8% reflection � 3.2% Z 0 ?? (full-wave Simulation)
140
120
100
80
3.2 %
100 125 150
Space (µm)
12/31

Characteristic Parameters – 1.Characteristic Impedance (Z 0 )
Voltage (V)
±20% <strong>of</strong> Space variation for Common-mode Signaling
Circuit Simulation (? ? TDR Setup) Full-wave simulation
1.1 % reflection
Time (ns)
Z 0 (Ohm)
70
50
30
10
2.6 %
100 125 150
Space (µm)
� Z Common-mode (33 Ohm) > Z Cable (50/2=25 Ohm) ? ? ?? Mismatching
� Space? (20%) � Reflection ? ? (1.1 %)
� 1.1% reflection � 2.6% Z 0 ?? (full-wave Simulation)
13/31

Effect by Edge Placement <strong>of</strong> <strong>Differential</strong> <strong>Line</strong>
Seungyong Baek, Derek Kam, Bongcheol Park, Jung-Gun Byun, Cheol-Seung Choi, and Joungho Kim, “Increased Radiated
Emission and Impedance Change by Edge-Placement <strong>of</strong> <strong>High</strong>-<strong>speed</strong> <strong>Differential</strong> <strong>Line</strong>s on Printed Circuit Board,” 2002
IEEE International Symposium on Electromagnetic Compatibility, vol 1, pp 200-204, Minnesota USA.
? Consider the effects by edge placement <strong>of</strong> high-<strong>speed</strong> differential lines
? Demonstrate differential mode impedance change by edge placement
? Certificate variation <strong>of</strong> radiated emission using simulation and measurement
<strong>Line</strong> Width = 0.4mm
Pitch=0.7mm
Substrate Width=20mm
Distance to edge (D)
Height = 0.3mm
Substrate
length=80mm
Test PCB with finite width ground
14/31
10mm
0.8mm

Current density <strong>of</strong> differential pair (Simulation)
Substrate
Air
Trace 1 Trace 2 Trace 1 Trace 2
Substrate
(a) (b)
Air
10mm 1mm
Current density when the distance to edge is 10mm Current density when the distance to edge is 1mm
� When differential pair is located in the center <strong>of</strong> PCB, current density is balanced in case <strong>of</strong> (a)
� The balance <strong>of</strong> current density is broken by edge placement in case <strong>of</strong> (b)
15/31

<strong>Differential</strong> impedance change by edge placement (Simulation)
Impedance [ohm]
110
100
90
80
70
60
50
40
30
65
60
55
50
45
40
35
30
<strong>Differential</strong> mode impedance
25
1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6
Common mode impedance
20
10 9 8 7 6 5 4 3 2 1 0
Distance to edge (D) [mm]
� <strong>Differential</strong> mode impedance remains about 100Ω from 10mm to 2mm
� <strong>Differential</strong> mode impedance suddenly falls <strong>of</strong>f when D is 1mm
16/31

Measurement setup <strong>of</strong> differential impedance
<strong>Differential</strong> TDR module 80E04 + Sampling Oscilloscape TDS 8000B
( Reflected rising time= 30ps )
Test PCB
50Ω termination
Test setup for measuring the differential mode impedance
17/31

Measurement results – differential mode impedance
<strong>Differential</strong> Impedance [ohm]
120
110
100
90
80
70
60
Distance to the edge (D) = 10mm
Reduction <strong>of</strong> 17%
Distance to the edge (D) = 0.8mm
44.4 44.6 44.8 45 45.2 45.4 45.6 45.8 46 46.2
Time [ns]
� Distance to the edge = 10mm � <strong>Differential</strong> mode impedance = 102Ω
� Distance to the edge = 0.8mm � <strong>Differential</strong> mode impedance = 85Ω
� The differential mode impedance suddenly falls <strong>of</strong>f to 85Ω when D = 0.8mm
18/31

Variation <strong>of</strong> radiated emission by edge placement
Edge placement <strong>of</strong> high-<strong>speed</strong> differential lines
Balance <strong>of</strong> the differential lines is collapsed
Balance <strong>of</strong> the current density is also broken
Increase <strong>of</strong> common mode current
Variation <strong>of</strong> radiated emission
19/31

Radiated emission according to location <strong>of</strong> differential pair
150
210
Total electric field plot at 1GHz (V/m)
120
240
90
0.2
0.6
0.4
60
30
180 0
270
300
D=10mm (a)
D=3mm (b)
D=1mm (c)
D=0.8mm (d)
330
Simulated total electric field at 1GHz
MAX : 0.25V/m
MAX : 0.522V/m
(a)
(b)
(c)
(d)
20/31
10mm
3mm
1mm
0.8mm

Measurement setup <strong>of</strong> radiation emission
DC
Power
Supply
100MHz
Crystal
Oscillator
Spectrum Analyzer
180°
Phase Shifter
Shielding Box
180°
0°
Antenna
Anechoic Chamber
Radiated Emission
Test PCB
Test setup for measuring an amount <strong>of</strong> the radiated emission
21/31

Measurement result – maximum radiated emission
dBm
-55
-60
-65
-70
-75
-80
Maximum Spectrum (Peak-to-Peak envelop)
D=10mm
D=7mm
D=5mm
D=3mm
-85
100 200 300 400 500 600 700 800 900 1000
Frequency [MHz]
? The closer differential pair to the PCB edge, the more radiated emission occur
? When the differential pair is placed at the edge <strong>of</strong> the PCB, the shielding effect
by the ground plane is no longer effective
22/31

Conventional Method 1: <strong>Differential</strong> TDR
Dong Gun Kam, Heeseok Lee, Woonghwan Ryu, Jonghoon Kim, Bongcheol Park, and Joungho Kim, "An Evaluation <strong>of</strong>
<strong>Differential</strong> Impedance in PCBs Using Two Single-Ended Probes Only," IEEE Workshop on Signal Propagation on
Interconnects (SPI), 2002
S. Corey, et al., “Electronic Package Characterization Using <strong>Differential</strong> TDR Techniques”,
Proc. IEEE 9 th Topical Meeting on Electrical Performance <strong>of</strong> Electronic Packaging, 2000, pp. 172-174.
� Only a small skew <strong>of</strong> TDR pulses can result in considerable error.
B. J. Rubin, “Understanding Modeling and Measurements <strong>of</strong> <strong>Differential</strong> Transmission <strong>Line</strong>s”,
Proc. IEEE 10 th Topical Meeting on Electrical Performance <strong>of</strong> Electronic Packaging, 2001, pp. 313-316
� Its instrumentation is expensive because <strong>of</strong> such difficulties as
synchronizing two TDR pulses.
23/31

Conventional Method 2: Balun
2-port VNA
Balun DUT
Balun
� Balun = Power Splitter + Phase Shifter
� It is very difficult to make broadband baluns.
24/31

Conventional Method 3: Mixed-Mode Mixed Mode S-parameters
S parameters
D. E. Bockelman, “Combined <strong>Differential</strong> and Common-Mode Scattering Parameters: Theory and
Simulation”, IEEE Trans-MTT, Vol. 43, No. 7 (1995), pp. 1530-1539
� Although it is theoretically perfect, it is very expensive.
25/31

What’s What s the Matters with the Conventional Methods
Balun
Only narrow-band
Need for
de-embedding balun effect
4-port Measurement
Expensive
<strong>Differential</strong> TDR
Accurate synchronization <strong>of</strong>
two TDR pulses is required
Expensive
26/31

Proposed Method
� Two single-ended probes are connected to each signal traces
with a metallic plane on the bottom layer floating.
27/31

Measured Results
� Device-Under-Test (DUT) : Coupled Microstrip <strong>Line</strong>
DUT
#1
#2
#3
W
(width)
3mm
2mm
1mm
� Measured <strong>Differential</strong> Impedance at 500MHz
DUT
#1
#2
#3
Proposed
Method
67.1O (-1.0%)
86.7O (-2.1%)
126O (-2.3%)
4-port
Measurement
67.8O
88.6O
129O
S
(space)
2mm
3mm
4mm
H
(dielectric)
28/31
1mm
1mm
1mm
Simulation
(MoM)
68.9O (+1.1%)
91.1O (+2.8%)
132O (+2.3%)

Full Wave Simulation (Using Ans<strong>of</strong>t HFSS)
DUT
#1
#2
#3
500 MHz
72.9O (+7.5%)
91.4O (+3.2%)
126.8O (-1.7%)
2 GHz
72.3O (+6.6%)
91.3O (+3.0%)
126.5O (-1.9%)
5 GHz
73.2O (+8.0%)
91.0O (+2.7%)
126.8O (-1.7%)
29/31
Ref.
67.8O
88.6O
129 O

The PROS and CONS <strong>of</strong> the Proposed Method
Disadvantage
Advantage
<strong>Differential</strong> only
Simple
Cheap
Non-invasive
Practical !!!
30/31

Conclusion
? We have been researching Signal Integrity, Power/Ground Integrity
and EMI in Tera Lab.
? We introduced <strong>Differential</strong> Signaling Scheme
� Variation <strong>of</strong> differential line characteristics by fabrication error
� Change <strong>of</strong> differential impedance by edge placement
� Proposal <strong>of</strong> new test method <strong>of</strong> differential lines
31/31