Dual-pipeline heterogeneous ASIP design - School of Computer ...

Figure 9: 2-pipes .vs. 1-pipe
ness of the created two-pipe processors, and our design a p
proach, we also implemented those functions with single
pipe ASIPs produced by ASIPMeister. The verification sys-
tem for sin le pipe and two-pi e processors are shown in
Figure 10. %,e that the sirnurated results are for the in-
struction set after Phase I. All applications used the same
sample data set for both single and parallel implementations.
Figure 10: Synthesis/Simulation System
the moeram in'terms of clock cvcles ICC,). We also o kin
microns from AMI.
The simulation results are shown in Table 2. The first col-
umn gives the name of the application, the second and third
the area cost of single and arallel implementations respec-
tively, the fourth and the &th columns give the number of
clock cycles for execution of the application, and the sixth
and the seventh gives the switching activity when the appli-
cation was executed. Eight and ninth columns give the clock
period for the processors designed (results obtained from
Synplify ASIC). Tenth, eleventh and the twelfth columns
give the percentage increase in area, percentage speed im-
provements, and percentage switching activity reductions.
These three columns (10,ll and 12) are plotted in Figure 9.
As can be seen from the table, there is up to 36% im rove-
ment in speed. The speed improvement is at the cost orsome
extra chip area. The two-instruction sets in each design
were created with very little overlap, i.e., few instructions
were in both pipes. The clock eriod reductions came from
the decreased controller compyexity. The extra area cost
mainly comes from the second controller, additional func-
tional blocks and data buses for parallel processin which
is common to all dual-pi e designs. Therefore, tfe extra
area cost is almost same t% all the design, which is around
16%
Switching activity reductions are obtained by reduced switch-
ing in program counter and simplified functional circuitry.
For exam le, two parallel add instructions can have less
number ofswitches than the two instructions executed in
a single pipe, since addition is implemented with an adder
instead of an ALU in second pipe.
17
5. CONCLUSIONS
In this paper we have described a system which expands
the design space of ASIPs, by increasing the number of
pipelines. We allocate load/store operations to one of the
pipes, and in general ALU operation to the other pipe. If
there are additional ALU operations which can be paral-
lelized, then they are spread over the next pipe. We see
speed improvements of up to 36% and switching activity
reductions of up to 11%. The additional area costs approx-
imately 16%.
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