Sailesh Chittipeddi - EEWeb

Most design references assume the gain of 1 design
is most advantageous for amplifier bandwidth and
sensitivity reasons. However, it turns out this conditions
always requires that R11) – and sometimes
significantly less. Sweeping the C ratio from about 0.2 to
5 for a gain of 1 and plotting the R2/R1 ratio for different
target Q’s gives Figure 8. It is desirable that this ratio
be low. Using equal C gives the minimum but as the
required Qp goes up, R1 must be much lower than R2
as shown in the log/log plot of Figure 8.
R2/R1 Ratio
Figure 8: Required R2/R1 ratio for swept C2/C1 parametric
on Q using K=1.
Getting some of the Q with gain in the amplifier has
a dramatic effect on this in a desirable direction.
Using an amplifier gain of 2 and repeating this same
calculation gives the required R2/R1 ratio of Figure 9.
Using just a bit of gain has moved the required R1 value
up significantly if R2 is chosen for loading, noise, and
input offset voltage reasons. These curves also suggest
selecting C2/C1>1 might be desirable.
R2/R1 Ratio
1000
100
10
10
1
R2/R1 Ratio vs C2/C1 Ratio K=1
Q=.577 Q=.707 Q=1 Q=5.27
1
0.1 1 10
C2/C1 Ratio
R2/R1 Ratio vs C2/C1 Ratio K=2
Q=.577 Q=.707 Q=1 Q=5.27
0.1
0.1 1 10
C2/C1 Ratio
Figure 9: Required R2/R1 ratio for swept C2/C1 parametric
on Q using K=2.
Using these two gains of 1 and 2, the difference in input
impedance will be shown for a Q = 5.27 design (this
is the approximate highest Q stage required for a 6th
order 0.25dB Chebychev filter).
TECH ARTICLE
Example design for 1kHz 2nd order high
pass with >1Mhz signal bandwidth for
K=1
The lowest R2/R1 ratio in figure 2 is for equal C at K=1.
Use the ISL28113 (ref.3) to get a signal bandwidth
exceeding 1Mhz in a μPower design as shown in the
circuit of figure 4 (ref.4). This device offers a 2MHz Gain
Bandwidth Product (GBP) using only 90μA (typical,
130μA max) supply current on a 1.8V to 5.5V supply.
Use an R2 that adds an input noise approximately equal
to the amplifier’s 25nV/√Hz and start the design with
R2=50kΩ. This high Q design will be peaking the input
noise around Fo quite a lot, so it is best to not let R2 get
too high. The design of Figure 4 used 50k for R2, but that
forced R1 down to 457Ω using Eq. 4.
Vin
33.3n
C 1
33.3n
C 2
1.25u
Figure 10: High Q, K=1 design with 1kHz Fo and
Q = 5.27
Figure 11 shows the expected frequency response
while Figure 12 shows the relatively high noise peaking
around Fo. The response curve is showing the expected
peaking at 1kHz, and then a gain of 1 over a broad
passband with the amplifier rolling off above 2Mhz.
The output spot noise peaks approximately 60X around
Fo. This is common for high Q stages but is even higher
here due to the very high resistor ratio. Since this is
happening at lower frequencies it should not impact the
integrated noise too much, but will be degrading the
loop gain at the lower end of the intended passband.
Reducing this noise gain peaking for high Q poles is
desirable and easily achieved by adding some gain in
the amplifier.
The added concern in Figure 10 is the several regions of
capacitive input impedance. Figure 13 shows simulated
input impedance showing the initial capacitive response
up to Fo which then recovers to the R2 resistor value.
The phase response across the R1 resistor comes down
to approximately 0deg above Fo over a wide frequency
range effectively bootstrapping out the relatively low R1
value. However, even a slight phase deviation over the
457
R 2
50k
20
Rb ISL28113
+
+
–
–
Visit www.eeweb.com
R 1
10k
R f
V+
V–
-9.29209u
19