Design for Testability (II)
Design for Testability (II)
Design for Testability (II)
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Testing Digital Systems <strong>II</strong><br />
Scan Path Methods <strong>for</strong><br />
Flip-Flop Machines<br />
Copyright 2010, M. Tahoori TDS <strong>II</strong>: Lecture 3 9<br />
Scan Path Methods <strong>for</strong> Flip-Flop Machines<br />
Each of the circuit flip-flops is replaced by<br />
Multiplexed data flip-flop (MD flip-flop)<br />
T<br />
D0<br />
D1<br />
CK<br />
MUX<br />
d<br />
G1<br />
0<br />
1<br />
1D<br />
C1<br />
Q<br />
D0<br />
& +<br />
T d<br />
D1<br />
(a) (b)<br />
(a) flip-flop with multiplexer (MUX)<br />
(b) multiplexer circuit diagram<br />
Copyright 2010, M. Tahoori TDS <strong>II</strong>: Lecture 3 10<br />
Lecture 3 5<br />
D0<br />
D1<br />
T<br />
CK<br />
0, 2D<br />
1, 2D<br />
(c) symbol <strong>for</strong> multiplexed data flip-flop (MD flip-flop)<br />
C2<br />
(c)<br />
Q
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