ERROR CONTROL AND CODING QUESTION BANK Subject Code ...

ERROR CONTROL AND CODING
QUESTION BANK
Subject Code: 10EC 039 Faculty: Kavitha Y.C.
INTRODUCTION TO ALGEBRA
1) Construct the group under modulo-6 addition.
2) Construct the group under modulo-3 multiplication.
3) Let m be the positive integer. If m is not a prime, prove that the set {1,2.,.,.,,m-1} is not a group under modulo-m
multiplication.
4) Construct the prime field GF(11) with modulo -11 addition and multiplication. Find all the primitive elements and
determine the order of other elements.
5) Let m be the positive integer. If m is not a prime, prove that the set {0,1,2.,.,.,,m-1} is not a field under modulo-m
addition and multiplication.
6) Prove that every finite field has a primitive element.
7) Solve the following simultaneous equations of X,Y,Z and W with modulo-2 arithmetic :
X+Y+W=1, X+W+Z=0, Y+Z+W=1,Y+Z+W=0
8) Show thatX 5 +X 3 +1 is irreducible over(2)
9) Find all irreducible polynomials of degree 5 over GF(2).
10) Prove that GF(2 m )is a vector space over GF(2)
11) Construct the vector space V5 of all 5-tuples over GF(2).Find the three dimensional subspace and determine its null
space.
12) Let v be a vector space over a field F.for any element c in F, prove that c 0=0.
13) Let S1 S2 be the two subspaces of a vector v.show that intersection of S1 S2 is also a subspace in v.
LINEAR BLOCK CODES
14) Consider a systematic (8,4) code whose parity check equations are vo=u1+u2+u3, v1=uo+u1+u2,
V2=uo+u1+u3, v3=uo+u2+u3 where uo,u1, u2 and u3 are message digits and vo,v1,v2,and v3 are parity check
digits. Find the generator and parity check matrices for this code. show analytically that minimum distance of this
code is 4.
15) Construct the encoder for the code given in problem 14..
16) Construct the syndrome circuit for the problem in 14.
17) Let c be a linear code with both even weight and odd weight code vectors. Show that number of even weight code
vectors is equal to odd weight code vectors.
18) Prove that hamming distance satisfies triangular in equality that is let x,y and z three n tuples over GF(2), and show
that d(x,y)+d(y,z)>=d(x,z).
19) Prove that a linear code is capable of correcting λ or fewer errors and simultaneously detecting l (l>λ) or fewer errors
if its minimum distance dmin>= λ+l+1.
20) Determine the weight distribution of the (8,4) linear code given in problem 14 .let the transition probability of a BSC
be p=10 -2 . Compute the probability of an undetected error of this code.
P.E.S.I.T DEPT. OF TE III SEM M.Tech. (DECS) 1/8

21) Because the (8,4) linear code given in problem 14 has minimum distance 4, it is capable of correcting all the single –
error patterns and simultaneously detecting any combination of double errors. Construct a decoder for this code.
The decoder must be capable of correcting any single error and detecting any double errors.
22) The (8,4) linear code given in problem 14. Is capable of correcting 16 error patterns. Suppose that this code is used
for a BSC. Devise a decoder for this code based on the table-lookup decoding scheme. The decoder is designed to
correct the 16 most probable error patterns.
CYCLIC CODE
23) Consider (15,11) cyclic hamming code generated by g(x) =1+X+X 4
a) Determine the parity polynomial h(x) of this code.
b) Determine the generator polynomial of its dual code.
c) Find the generator and parity matrices in systematic form for this code.
24) Devise an encoder and a decoder for the (15,11) cyclic hamming code generated by g(X)= 1+X+X 4
25) Show that g(X) =1+x 2 +X 4 +X 6 +X 7 +X 10 generates a (21,11) cyclic code. Devise a syndrome computation circuit for
this code. Let r(X) =1+X 5 +X 17 be a received polynomial. Compute the syndrome of r(X).display the contents of the
syndrome register after each digit of r has been shifted in to the syndrome computation circuit.
26) Shorten this (15,11) cyclic hamming by deleting the seven leading high order message digits.the resultant code is
an (8,4) shortened cyclic code. design a decoder for this code that eliminates the extra shifts of the syndrome
register.
27) Shorten the (31,26) cyclic hamming by deleting the 11 leading high order message digits. The resultant code is a
(20,15) shortened cyclic code. devise a decoding circuit for this code that requires no extra shifts of the syndrome
register.
28) Suppose that the (15,10) cyclic hamming code of minimum distance 4 is used for error detection over a BSC with
transition probability p=10 -2 .compute the probability of an undetected error ,pu(E), for this code.
29) Devise a decoding circuit for the (7,3) hamming code generated by g(X)=(X+1)(X 3 +X+1).The decoding circuits
corrects all the single error patterns and all the double adjacent error patterns.
30) For a cyclic code, if an error pattern e(X) is detectable ,show that its ith cyclic shift e (i) (X) is also detectable.
31) Let g(X) be the generator polynomial of an (n,k)cyclic code c. suppose c is interleaved to a depth of λ.prove that the
interleaved code c λ is also cyclic and its generator polynomial is g(X λ ).
32) Show that the probability of an undetected error for the distance -4 cyclic hamming codes is upper bounded by
2 -(m+1).
BINARY BCH CODES
33) Determine the generator polynomials of all the primitive BCH codes of length 31.use the Galois field GF(2 5 )
generated by p(X) =1+X 2 +X 5.
34) Suppose that the double error correcting BCH code of length 31 constructed in problem 33 is used for error
correction on a BSC. Decode the received polynomials r1(X)=X 7 +X 30 and r2(X)=1+X 17 +X 28 .
35) Devise a chien’s searching circuit for the binary double error correcting (31,21)BCH code.
36) Devise a syndrome computation circuit for the binary double error correcting (31,21) BCH code.
37) Is there a binary t-error correcting BCH code of length 2 m +1 for m>=3 and t

MAJORITY- LOGIC DECODABLE AND FINITE GEOMETRY CODES
39) Consider the (31,5) maximum –length code whose parity check polynomial is p(X)=1+X+X 2 +X 5 .Find all the
polynomials orthogonal on the digit position X 30 .Devise both type-I and type –II majority –logic decoders for this
code.
40) Example 39 shows that the (15,7)BCH code is one step majority logic decodable and is capable of correcting any
combination of two or fewer errors.show that the code is also capable of correcting some error patterns of three
errors and some error patterns of four errors. List some of these error patterns.
41) Show that the extended cyclic hamming code is invariant under the affine permutations.
42) Show that the extended primitive BCH code is invariant under the affine permutations.
43) Prove that if J parity check sums orthogonal on any digit position can be formed for a linear code(cyclic or
noncyclic), the minimum distance of the code is at least J+1.
44) Find the generator polynomial of the first order cyclic RM code of length 2 5 -1.describe how to decode this code.
45) Find the generator polynomial of the third order cyclic RM code of length 2 6 -1.describe how to decode this code.
BURST –ERROR- CORRECTING CODES
46) Show that if an (n,k) cyclic code is designed to correct all burst errors of length l or less and simultaneously to detect
all burst errors of length d>=l or less, the number of parity check digits of the code must be at least l+d.
47) Devise an error trapping decoder for an l-burst error correcting cyclic code. The received polynomial is shifted in to
the syndrome register from the right end. Describe the decoding operation of your decoder.
48) Prove that the fire code generated by (20,4) is capable of correcting any error burst of length l or less.
49) The polynomial p(X)=1+X+X 4 is a primitive polynomial over GF(2). Find the generator polynomial of a fire code
that is capable of correcting any single error burst of length 4 or less .what is the length of this code? Devise a
simple error trapping decoder for this code.
50) Devise a high speed error trapping decoder for the fire code constructed in problem 49 .describe the decoding
operation.
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P.E.S.I.T DEPT. OF TE III SEM M.Tech. (DECS) 3/8

MULTI MEDIA COMMUNICATION
QUESTION BANK
Subject Code: 10EC052 Faculty: Mr. MJR
Chapter: Multimedia Communication
1) What is Multimedia?
2) Differentiate between Multimedia and Hypermedia?
3) What are the different types of communication networks?
4) What is Dither matrix?
5) Briefly explain network QOS parameters
6) Briefly explain Application QOS parameters.
Chapter: Information Representation
7) Explain different types of multimedia information representation.
8) Explain different multimedia applications
9) Name lossless and lossy compression algorithms
10) Explain Huffman coding with an example.
11) Explain Dynamic Huffman coding.
12) Explain LZW Compression.
13) Explain Linear predictive coding
14) Explain DPCM and ADPCM
15) Explain the differences between uniform and non-uniform quantization.
16) Explain H.261 encoding and decoding.
17) What is motion estimation and motion compensation?
18) Explain different types frames.
19) What are the differences between I-Frame and P-Frames?
20) What is the significance of D-Frame?
21) Explain P1.323 compression technique?
22) Explain MPEG1 encoding and decoding techniques.
Chapter: Detailed Study of MPEG-4
23) Explain MPEG4 encoding and decoding techniques
24) Explain JPEG encoding and decoding techniques.
25) Compare MPEG4 with MPEG1.
26) Compare MPEG4 with MPEG2.
27) What do you meant VOP?
28) What are the salient features of JPEG 2000?
P.E.S.I.T DEPT. OF TE III SEM M.Tech. (DECS) 4/8

Chapter: Synchronization
29) What is the notion of Synchronization?
30) Explain SMIL.
31) Explain different Multimedia Operating Systems.
32) Explain Resource Management.
33) Explain Process Management.
Chapter: Multimedia Communication across Networks
34) What is layered video coding?
35) Explain Error resilient video coding technique?
36) Explain RSVP protocol.
37) Explain RTP protocol.
38) Explain RTCP protocol.
39) Explain DVMPP protocol.
40) Explain the applications of Multimedia in mobile networks.
41) Explain the applications of multimedia in broadcast networks.
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P.E.S.I.T DEPT. OF TE III SEM M.Tech. (DECS) 5/8

REAL TIME OPERATING SYSTEMS
QUESTION BANK
Subject Code: 10EC126 Faculty: Ms. BVK
Chapter 1: Introduction
1. Define i) Real Time System ii) Organic System
2. Compare soft, hard and firm real time systems, with an example for each
3. Differentiate between asynchronous and synchronous events
4. Describe the following addressing modes
i) Direct
ii) Immediate
iii) Register direct
iv) Register indirect
5. Write a program to evaluate the function sum = (a+b) – (c*d), using one address instruction format
6. Write a program that performs the calculation using zero address machine
x 2 – xy + y 2
Z =
x 2 + y 2
7. Write a program that performs the calculation using zero address machine
– b + √b2 – 4*a*c
root =
2*a
8. Write short notes on the following:
i) Pipelining
ii) Coprocessors
iii) DMA Controller
iv) Programmed I/O and Interrupt I/O
v) Interrupt controller
vi) Watchdog timer
Chapter 2: Device drivers
9. Explain the steps involved in writing a device driver
10. Describe a device driver using interrupt service routine
11. Define context switching, latency with respect to interrupts
Chapter 3: Embedded systems
12. Compare different processor architectures for real time embedded system design.
13. Compare RISC and CISC architectures
14. Explain the architecture of ARM processors
15. Explain the various features of Strong ARM Processor
P.E.S.I.T DEPT. OF TE III SEM M.Tech. (DECS) 6/8

16. Write short notes on the foll:
i) Big Endean vs Little Endean
ii) Exceptions
Chapter 4: Real Time Operating System
17. Explain various fundamental requirements of RTOS
18. Explain Kernel hierarchy and different types of Kernel
19. A simple process consists of 3 states, at the end of each state a flag is set and the process is terminated. Upon
termination the process resumes where it left off. Write the pseudo code.
20. Explain polled loop system with an example. What are its merits & demerits
21. Explain the different approaches to CPU scheduling in real time OS. Comment upon the suitability of them for
process, task and thread scheduling.
22. With a state transition diagram and TCB, explain the functions of the various states.
23. Describe round robin scheduling policy
24. Explain preemptive scheduling
25. Explain the cooperative round robin scheduling using a circular queue of ready tasks
26. Write short notes on:
i) Scheduling of periodic, sporadic and aperiodic tasks
ii) Advanced scheduling algorithm
27. Define tasks. What are different features of tasks
28. What is the need for synchronization between process, tasks and threads? What are the various methods of
synchronization?
Chapter 5: Memory and File Management
29. Define internal and external fragmentation. What is the use of a relocation register?
30. Describe virtual memory concept and demand paged memory allocation technique
31. Explain segmentation in memory management. What are the approaches followed by different processors for
implementation of segmentation.
32. Explain how pipelines, message queues and mail boxes can be used for inter-process synchronization.
33. Compare message queue, mailbox & pipes
34. Write short notes on the foll:
i) Semaphores
ii) Mail box
iii) Massage Queues
iv) Inter task comunication
35. Explain cache organization. What are the different address translation mechanisms used for mapping
addresses to cache locations.
P.E.S.I.T DEPT. OF TE III SEM M.Tech. (DECS) 7/8

Chapter 6: Case Study
36. Explain the features of VxWorks.
37. Compare the tools needed for verification, validation and testing of embedded systems.
38. Explain the features of MUCOS
39. Explain the features of Psos.
Chapter 7: Development and Verification of Real Time Software
40. Explain building of real time applications
41. What are the approaches to double buffering in real time embedded systems?
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P.E.S.I.T DEPT. OF TE III SEM M.Tech. (DECS) 8/8