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LPGD 

A Low-Power Design Methodology/Flow and its Application to the 

Implementation of a DCS1800-GSM/DECT 

Modulator/Demodulator 

(ESPRIT 25256) 

Title: “Report on the General IC&D” 

Author(s): D. Soudris 1 , C. Dre 2 , and C. Goutis 3 

1 

Democritus University of Thrace (DUTH) 

2 

Intracom 

3 

University of Patras (UP) 

Editor: DUTH+UP+INTRACOM 

Type: Report 

LPGD Id: LPGD/WP2/DUTH+UP+INTRACOM/D2R2 

CEC Identifier: EP25256/ DUTH+UP+INTRACOM/D2R2 

Document Version: 1 

Status: Deliverable 

Confidentiality: Public 

Actual Date: December 31, 1999 

Contractual Date: November 30, 1999 

WorkPackage: WP2 

Keywords: dissemination activities, type of dissemination, final report 

Abstract: In this IC&D report, we provide the various kinds of 

dissemination activities aimed at different target groups, 

where we used a variety of information transfer mechanisms 

realizing from certain forms of supporting material. 

Copyright © 1999 

INTRACOM 

UP 

DUTH

Report on the General IC&D LPGD/WP2/DUTH+UP+INTRACOM/D2R2 

History 

Date Version Comments 

December 31, 1999 1 Deliverable 

Purpose /Scope 

The purpose of the final Information Capturing and Dissemination report is to provide all the dissemination 

activities which done during the twenty four months of LPGD projects. The consortium through the different 

activities tried to disseminate the project results into a variety of target groups coming from academia and 

industry. 

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TABLE OF CONTENTS 

1. INTRODUCTION ........................................................................................................................................ 4 

2. SUMMARY ................................................................................................................................................. 4 

2.1 GMSK DIGITAL MODULATOR...................................................................................................................... 4 

2.2 DECT RECEIVER......................................................................................................................................... 4 

2.3 FIR FILTER DESCRIPTION ............................................................................................................................ 6 

3. INFORMATION CAPTURING AND DISSEMINATION ACTIVITIES...................................................... 7 

3.1 EVENTS/PATMOS ’99 WORKSHOP.............................................................................................................. 7 

3.2 MEETINGS................................................................................................................................................... 7 

3.3 PUBLICATIONS............................................................................................................................................. 7 

3.4 AWARD....................................................................................................................................................... 9 

3.5 FUTURE PLANS ............................................................................................................................................ 9 

3.6 CONCLUSIONS ............................................................................................................................................. 9 

4. REFERENCES............................................................................................................................................. 9 

List Of Figures 

Figure 1. FPGA Interface ................................................................................................................................. 5 

Figure 2. The Architecture of DECT receiver. .................................................................................................. 6 

Table of Contents Public Page 3


1. Introduction 

This report includes all the dissemination activities which done during the twenty four months of LPGD 

projects. The consortium through the different activities tried to disseminate the project results into a 

variety of target groups coming from academia and industry. The target group’s people were 

undergraduate and graduate students coming from universities and research institutes, professors from 

European and Northern America Universities, and designers and managers from industry. Depending on 

the audience, we used different information transfer mechanism. More specifically, we participated in the 

technical meetings and ESD-LPD workshop organized by DIMES, where we provided appropriate talks, 

we had close cooperation with DIMES during PATMOS 99 workshop where we organized common 

actions, we published a plethora of journals and conference papers and two book chapters, we established 

a functional web-sites to all partners, where all the public material (i.e. deliverable reports) can be 

downloaded, and we developed tools for power estimation. For supporting the dissemination activities we 

prepared many articles, demos for the developed software tools, and material for presentations. 

The rest of this report is organized as follows: Section 2 presented a summary the design experiment. The 

Section 3 presented all the IC&D activities done during the LPGD project. Some conclusions are drawn in 

Section 4. 

2. Summary 

Figure 1 depicts the main building blocks of the implemented GSM/DECT Modulator/Demodulator as 

well as the interface links or signals with ASPIS processor [1,2], the chosen Analog-to-Digital and 

Digital-to-Analog Converters, and Automatic Gain Control (AGC) & DC Offset. The main building 

blocks of the designed module are: 

i) the GSM/DECT modulator, based on a look-up-table principle which creates the GMSK 

waveforms, 

ii) the DECT demodulator, which is based in a zero-IF architecture, and 

iii) the digital FIR filters. 

The main characteristics of each building block of GMSK/GFSK modulator/demodulator will be given in 

the next paragraphs. The system description will begin with the uplink path and through downlink path, 

will end up with the detailed implementation of FIR filters. 

2.1 GMSK Digital Modulator 

The architecture of the digital GMSK modulator designed to satisfy both GSM and DECT standards. The 

modulator receives data from ASPIS processor and produces two output streams, I and Q, which are 

eventually the input of D/A converter. 

The input stream of GMSK Modulator, , comes from ASPIS processor, while the outcome of 

modulator is two GMSK modulated digital streams Iout and Qout of 10 bits. The input data of inData 

appear after (N+1/2)×Tb time units, where Tb is the period of Data_Clock and N integer ranging between 

0 and 511. The inData are read either with falling edges of Data_clock or before the use of phi clock 

8x1152kb/s. It can be stressed that the time point where the data of inData will be read is not so critical 

(i.e. enable of read In). The signal SynReset is activated during a falling-edge of Data_Clock. The rate of 

inData stream is equal to the rate GSM/DECT standard. Regarding with GSM and DECT, an 

interpolation factor 16 (=4.33MHz) and 8 (=9.2MHz) is used, respectively. Then, using a suitable 

multiplexer, the multiplexed data are feed to a Digital-to-Analog converter (DAC). The demonstrator 

board uses the DAC AD9761 of Analog Devices. This particular DAC has one parallel port of 10 bits, 

which read the multiplexed data of I & Q every rising edge of clock. The value of SELECT determines 

whether the current input value belongs to I or Q output streams. During the idle state the signals 

CLOCK/WRITE are LOW. 

2.2 DECT Receiver 

The complete design of the implemented DECT receiver, shown in Fig. 2, consists of four blocks: 

• The Phase Difference Decoder Block (PDD) 

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• The Automatic Frequency Correction Block (AFC) 

• The Phase Difference Transition Mapper Block (PDTM) 

• The Symbol Timing Estimation Block (STE) 

ASPIS 

Processor 

t_en 

do 

H_mode 

b_clk 

EMI_clk 

bsclk 

r_en 

rec_data 

dpllsynchom 

slotsynchom 

aux_fso_out 

aux_do 

aux_fsin 

aux_fso_din 

aux_clk 

Aux Clock 

synReset 

inData 

gsmDect 

13.824MHz 

27.648MHz 

Start_Detection 

Symbol 

preamble_detected 

b_clk 13.824MHz 

Data_Clock 

slot_detected 

I/F 

Start_Detection 

LPGD FPGA 1 

I/F 

phi 

8x1152kHz 

GMSK 

Digital 

Modulator 

Clock 

generator 

block 

DECT 

Detector Receiver 

6 

Select 

6 

6 6 8 8 

8 

8 

AGC & 

DC offset block 

FIR 

FIR 

10 

10 

2 

Clock 

4x1152kHz 

Clock 

4x1152kHz 

Figure 1. FPGA Interface 

8 

8 

MUX 

DEMUX 

FPGA 2 

I/F 

readIn 

IQ 10bits 

SELECT 

WRITE 

CLOCK 

CLOCK 

SELECT 

IQ 8bits 

CS 

SCLK 

DIN 

AD9761 

AD9281 

Input 

Streams 

MAX549A 

Output 

Streams 

The circuit accepts at its input a quantized IQ stream consisting of a pair (I, Q) of 6-bit vectors in sizemagnitude 

form received on each clock cycle. The processing of the above stream by the five blocks 

presented above yields the bit stream of the data section contained in a DECT slot. More specifically, the 

differential detector uses the symbol rate sampled streams of the in-phase, I, and quadrature-phase, Q, 

components of the received baseband GMSK signal and calculates the phase difference between the two 

sampling instants. The AFC system operates using one sample per symbol period and estimates the phase 

rotation between two successive symbols, and produces a phase error estimate that corrects the phase 

difference.The phase difference, after being corrected by the AFC block, is fed to the Phase Difference 

Transition Mapper (PDTM). This block, depending on the phase difference, will produce a 01, 10 or 00, 

which in turn, with the help of a simple FSM, will extract the estimated data. Finally, the functions of slot 

synchronization and symbol timing estimation block of the proposed receiver use the same basic 

principles. As a result, these functions are implemented by the same functional block and occur 

simultaneously, thus resulting in a joint slot Synchronization and symbol timing estimation. The detailed 

functional description of DECT detector were presented in [3]. 

In order to design efficiently the DECT receiver in terms of power consumption, we used existing 

low power techniques and developed two new power optimization techniques, namely the behavioural 

power management and the dynamic frequency reduction. These techniques can be applied on a large 

class of wireless communications algorithms. The power management discipline implies that when the 

output of a component becomes unobservable then this component can be shutdown [4]. The technique 

applied here is based on the fact that unobservability can be introduced for a behavioural cluster after the 

occurrence of an event. For example the outputs of a behavioural cluster responsible for the computation 

of a series become unobservable once the series converges. The same situations can be met in a 

behavioural cluster responsible for synchronization after the synchronization is achieved. The application 

of this technique achieves 31% power reduction for the DECT receiver circuit with respect to the power 

consumption of the DECT receiver circuit with no power management features. 

OUT I 

OUT Q 

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The second technique reduces the frequency operation depending on the input data streams. More 

specifically, adaptive sampling through oversampling imposes that the whole receiving algorithm is 

computed on N input data streams, each one of which corresponds to a different sampling instance during 

the symbol period, while only one stream corresponds to the correct sampling instance. This introduces a 

significant power overhead. For this purpose a novel frequency reduction technique is introduced. 

Specifically, the operation frequency can be reduced to the symbol frequency after the synchronization 

pattern detection and up to the end of the frame. During this time interval, the receiver is forced to 

operate only on the input stream that corresponds to the correct sampling instance. After the end of each 

frame the receiver operates again at the oversampling frequency. For the design of the DECT receiver 

design, the application of dynamic frequency reduction lead to 65% power reduction, with an area 

overhead of 1,02%. 

Table 1 gives the area estimation, the number of equivalent gates and the power dissipation of each 

block separately as well as the total power consumption of DECT receiver. 

6 Bits 

6 Bits 

CLOCK 

CONTROL 

PHASE 

DIFFERENCE 

DETECTOR 

2.3 FIR Filter Description 

2 

SYMBOL TIMING 

ESTIMATION 

8 

AUTOMATIC 

FREQUENCY 

CORRECTION 

8 

DECT 

RECEIVER 

PHASE 

TRANSITION 

MAPPER 

Figure 2. The Architecture of DECT receiver. 

Filtering in most digital communication systems is accomplished by a combination of analog and digital 

lowpass filters. Digital lowpass filters are designed as Finite Impulse Response (FIR) filters. In this way 

there is more flexibility in the design and on the other hand it is a lot easier to obtain some very desirable 

characteristics like phase linearity and high accuracy in the response. Usually some windowing methods 

are used to derive the coefficients of the impulse response of the FIR filter. It should be stressed here that 

during the design of FIR filters the features of the analog filters of the uplink and downlink path were 

taken into account. Particularly, the receiver part uses 4th order Butterworth antialiasing analog filter, 

with fc=0.8*R. After extensive simulations we have reached the conclusion that a 13 taps FIR filters with 

interpolation factor 4 and cut-off frequency approximately 0.6*R(691xMHz) yields satisfactory 

performan-ce (BER results vs. SNR or Eb/N0). In addition, they meet the specifications of the DECT 

standard. Finally, it should be mentioned that a Kaiser window with beta=3.5 has been used. 

The input and the output of FIR are 8-bit sign magnitude integer (MSB is the sign and the seven LSBs 

is the value of signal). To attain sufficient accuracy and avoid the overflow possibility the internal buses 

have 24-bit length. 

Since the given coefficients are real numbers between –1 and 1, possible filter implementation with 

these coefficients would require a floating-point architecture. For that purpose, to simplify the design, a 

scaling technique is used to convert the filter coefficients into integer numbers. Thus, all the coefficients 

are multiplied by 16384. Because of these multiplications, the output of FIR multiplied with 16384, the 

output should be divided by 16384. 

We implemented the FIR filter using Cadence environment. After synthesis and simulation, we 

concluded that the FIR operates with 4.608 MHz clock frequency, the area is 7.075mm 2 using 0.7 m 

technology. 

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3. Information Capturing and Dissemination Activities 

3.1 Events/PATMOS ’99 Workshop 

In the context of 9th International Workshop on Power And Timing, Modeling, Optimization, Simulation 

(PATMOS ’99), 6-8 October, 1999 and the Digital Interest Group Meeting at Kos, October 5, 1999, 

PATMOS organizing committee (Note: The Contact person for IC&D of LPGD was also the General 

Chair of PATMOS 99) and DIMES had very effective cooperation and organized two very attractive panel 

sessions. 

More specifically, a panel session entitled “Does Logic Design only requires software skills?” took place 

an the 5th October 1999 in Kos, Greece. The Coordinator was Prof. Christian Piguet, CSEM, Switzerland 

and the panelists were: i) Professor W. Nebel, Uni-Oldenburg, Germany for “CAD for low-power”, ii) 

Professor D. Auvergne, LIRMM, France for “Teaching”, and iii) Ed Huigbrechts, Philips, Netherlands, 

for “Low-Power IC design”. 

The second panel was coordinated by Prof. Reinder Nouta and Rene van Leuken, DIMES in 7th October 

1999 ESD-LPD in Kos, Greece. Its title was "Power Analysis/Estimation Tools: Experiences and 

Expectations” and panelists were excellent experts from industry and academia; i) Prof. Steve Furber, 

Univ. of Manchester, UK, ii) Dr. Ed Huijbregts, PHILIPS, iii) Beata Paige, SENTE, and iv) Prof. Enrico 

Macii, Politecnico di Torino, ITALY. 

3.2 Meetings 

LPGD people participated actively in a series of technical meetings/workshops of the Digital Interest 

Group, which were organized by DIMES, TU Delft. Below, we provided the completed list of the 

technical meetings with the corresponding participants. 

i) Digital Interest Group Workshop at Sheraton Amsterdam Airport Hotel, July2, 1998. 

Participants: Dr. Dimitris Dervenis, Intracom. 

ii) Digital Interest Group Workshop at Sheraton Amsterdam Airport Hotel, November 23-24, 1998. 

Participants: Professor C.E. Goutis, University of Patras and Ass. Prof. D. Soudris, Democritus Univ. 

of Thrace. 

iii) Digital Interest Group Workshop and the ESD-LPD Open Workshop at Como, March 3, 1999. 

Participants: Professor C.E. Goutis, University of Patras and Ass. Prof. D. Soudris, Democritus Univ. 

of Thrace. 

iv) Digital Interest Group Workshop and the ESD-LPD Open Workshop at Kos, October 5, 1999. During 

the Open Part of Workshop a presentation of 30 min about the research results of LPGD was given by 

Ass. Prof. D. Soudris, , Democritus Univ. of Thrace and N. Zervas, University of Patras. 

Participants: Professor C.E. Goutis and N. Zervas, University of Patras, Ass. Prof. D. Soudris and 

Prof. A. Thanailakis, Democritus Univ. of Thrace, and Dr. C. Dre, INTRACOM. 

3.3 Publications 

During LPGD project several kinds of documents, which covered various aspects of the design 

experiment, the new low power design and estimation techniques, the design methodology for wireless 

applications and the main characteristics of the developed software tools, were published. Three kinds of 

publications were used: i) Public RDP and ICD Deliverables, ii) Journal papers, and iii) Conference 

papers. All the public material is available at the following sites of: 

INTRACOM: http://www.intracom.gr/lpgd 

UP: http://www.vlsi.ee.upatras.gr/Projects/lpgd/lpgd_pubs.html 

DUTH: http://www.vlsi.ee.duth.gr/projects/lpgd/lpgd_pubs.html 

Public Deliverables 

Public RDP Deliverables: 

i) D1.1R1: Survey of Low-Power Techniques, 

ii) D1.2R1: Structure of the Low-Power Design Flow, 

iii) D1.3R1: Generalised Low-Power Design Flow, 

iv) D2.1R1: Study, Analysis, and Exploration of Candidate Algorithms, 

v) D2.2R1: Low-Power Methodology for Transformations of Wireless Communication Algorithms, 

vi) D3.2R1: Low-Power Methodology for Designing Multiple Filters, and 

vii) D4.1R2: Report on Demonstration in DECT & GSM/DCS Environment. 

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Public IC&D Deliverables: 

i) D1R1 Proceedings of first Workshop, 

ii) D1R2 Proceedings of second Workshop, 

iii) D1R3 Dissemination results, 

iv) D2R1: Structure and techniques of the Low Power Design Flow, and 

v) D2R2: Report on the General IC&D. 

Journal/Conference Papers 

Regarding with the research results of LPGD a number of journal and conference papers were published, 

as the following list: 

Journal Papers 

1. G. Theodoridis, S. Theoharis, D. Soudris, and C.E. Goutis, “A Probabilistic Power Estimation Method 

for Combinational Circuits Under Real Gate Delay Model,” accepted for presentation in VLSI Design, 

Journal of Custom-Chip Design, Simulation, and Testing (invited paper). 

2. S. Theoharis, G. Theodoridis, P. Merakos, and C. Goutis, “Accurate Data Path Models for Fast RTlevel 

Power Estimation,” accepted for publication in IEE Proceedings - Circuits, Devices and Systems. 

Conference Papers 

1. D. Soudris, M. Perakis, X. Mizas, V. Mardiris, K. Katis, C. Dre, A.E. Tzimas, E.G. Metaxakis, G. 

Kalivas, N. Zervas, S. Theoharis, G. Theodoridis, A. Thanailakis, and C. Goutis, “Low-Power Design 

Of A Multi-Mode Transceiver,” accepted for presentation at ISCAS 2000, May 28 - 31, Geneva, 

Switzerland. 

2. N. Zervas, D. Soudris, S. Theoharis, C.E. Goutis, and A. Thanailakis, “A Methodology for the 

Behavioral-Level Event-Driven Power Management of Digital Receivers,” accepted for presentation at 

ISCAS 2000, May 28 - 31, Geneva, Switzerland. 

3. D.Soudris, N.D. Zervas, M. Perakis, S. Theoharis, G. Theodoridis, G. Kalivas, C. Dre, C.E. Goutis, 

and A. Thanailakis, “On the Low Power Design of Digital Receivers for Wireless Applications,” 

accepted for presentation in DATE 2000 User Forum, Paris, 27 - 30 March 2000. 

4. D. Soudris, C. Z. Lolas, and A. Thanailakis, “A Modified Energy Recovery Technique For 

Implementing DSP Algorithms,” accepted for presentation in 9th Int. Workshop Power And Timing 

Modeling, Optimization And Simulation (PATMOS `99), Kos, Greece, October 6-8, 1999, pp. 113- 

122. 

5. Z. Lolas, D. Soudris, I. Karafyllidis, A. Thanailakis, “A New Adiabatic Technique for Designing Low 

Power Array Architectures,” in Proc. of Int. Conf. on Electronics, Circuits and Systems (ICECS ’99), 

September 5-8, 1999, Pafos, Cyprus, pp. 795-798. 

6. M. Perakis, A.E. Tzimas, E.G. Metaxakis, D. Soudris, G.A. Kalivas, C. Katis, C. Dre, C.E. Goutis, 

and A. Thanailakis, “The VLSI Implementation Of A Baseband Receiver For Dect-Based Portable 

Applications,” in Int. Symp. on Circuits and Systems (ISCAS), Orlando, Florida, USA, May 30 - June 

2, 1999, Vol. I pp. 198-201. 

7. S.Theoharis, G. Theodoridis, D. Soudris, and C.E. Goutis,“An Efficient Probabilistic Method for 

Logic Circuits Using Under Real Delay Gate Model”, in Int. Symp. on Circuits and Systems (ISCAS), 

Orlando, Florida, USA, May 30 - June 2, 1999, Vol. I pp. 258-261. 

8. C.Z. Lolas, D. Soudris, I. Karafyllidis, And A. Thanailakis, “A New Adiabatic Technique For 

Designing Low Power Array Architectures”, In Proc. Of 6th IEEE Int. Conf. On Electronics, Circuits, 

And Systems (ICECS), September 5-8, Pp. 795-798, Pafos, Cyprus, 1999. 

9. S. Theoharis, G. Theodoridis, D. Soudris, and C.E. Goutis, "Accurate Data Path Module for RT Level 

Power Estimation" in Proc. of 8th Int. Workshop Power and Timing Modeling, Optimization and 

Simulation (PATMOS `98), pp. 213-222, October 7-9, Lyngby, Denmark. 

10. A.E. Tzimas, E.G. Metaxakis, and G.A. Kalivas "The design of a Baseband Receiver for a zero-IF 

DECT System Architecture" presented in Communication Systems of DSP, Sheffield, UK, 1998. 

11. A.E. Tzimas, E.G. Metaxakis, and G.A. Kalivas "A Low complexity Baseband Receiver for direct 

conversion Burst-type radio System" presented in Int. Sympos. on Computers and Communications 

(ISCC) Athens, Greece, 1998. 

12. E.G. Metaxakis, A.E. Tzimas, G.A. Kalivas, and G. Papadopoulos, "A Low complexity Baseband 

Receiver for direct conversion DECT-based Portable Communications" accepted for presentation in 

Int. Conf. on Universal Personal Communications (ICUMP), Florence, Italy, 1998. 

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Software Demostration 

During DATE 2000, we provide a demonstration of a software power estimation tool. 

3.4 Award 

The entire technical description of LPGD results (about 4,000 words) was submitted for review in Low 

Power Design Contest of 2000 IEEE Computer Elements Mesa Workshop, January 16-19 2000, Arizona. 

Our contribution selected and received an award of 2,000$ sponsored by Intel and IBM. 

3.5 Future Plans 

Our participation in Low Power Design Cluster and especially in LPGD project provides us with 

significant experiences, due to a variety of activities. Although LPGD project was completed by the end 

of October 1999, as consortium are willing to provide (and we provide) all the additional manpower for 

further dissemination of the gain experiences and the scientific results. 

i. According to the discussions in last ESD-LPD meetings, we have started preparing two book chapters, 

which are LPGD contributions in the book with the tentative title “Unified low-power design flow for 

data-dominated multimedia and telecom applications”, whose editor is Prof. F. Catthoor, IMEC, 

Belgium. The titles of our contributed chapters are: 

a) “Unified low-power design flow for data-dominated multimedia and telecom applications” 

b) "Power efficient synthesis of sum-of-products computations", with authors K. Masselos and C. E. 

Goutis. 

ii. The schedule is to prepare the whole book within the summer of 2000. 

iii. In addition, a second book will be prepared, with editor the Prof. Peter Ivey, Univ. of Sheffield, United 

Kingdom. LPGD will contribute a chapter about logic-level low power design techniques and power 

estimation methods. We hope finishing that work by end of this year. 

iv. During ESD-LPD'00 Workshop, Portofino, Italy, July 25-28, 2000, one presentation will be organized. 

v. Two journal papers are preparing for submission to: IEEE Trans. on Circuits and Systems II and IEEE 

Trans. on VLSI. 

3.6 Conclusions 

In the approved Technical Annex of IC&D, we have promised a series of activities, which would satisfy 

not only the general goals of IC&D action but also the IC&D activities described in the Technical Annex 

of IC&D. The various kinds of dissemination activities aimed at different target groups, where we used a 

variety of information transfer mechanisms realizing from certain forms of supporting material. 

A large variety of dissemination activities were made during the accomplishment of LPGD project. 

Comparing these activities with ones described in Technical Annex of IC&D, it can be easily inferred that 

the consortium made more activities that the promised ones without any additional expenses. Since LPGD 

partners have strong links through many other activities, the dissemination will continue as it can be seen 

in subsection 3.5, which indicates that the partners will provide all the necessary manpower to continue 

the dissemination the developed low power techniques and methodologies beyond the end of LPGD 

project. 

In conclusion, the partners of LPGD (INTRACOM SA, University of Patras, and Democritus University 

of Thrace) through the plethora of IC&D activities mentioned in Section 2-6 fulfilled entirely the 

objectives of IC&D Technical Annex and participated actively in more activities than the ones promised 

in IC&D Technical Annex of LPGD. 

4. References 

[1] D. Moolenaar, 'Building Blocks Preliminary Design Report (Processor Core)', ASPIS project deliverable, 

EP20287/IMEC/VSDM/DS/D4.2.R1/a1, May 1997. 

[2] H.C. Karathanasis, V. Bella, S. Blionas, D. Dervenis, C. Dre, 'Market Input Report for Multi-mode Terminal 

Specifications', ASPIS project deliverable, P20287/ ICOM/DPD/DS/D6.1.R1/a1, Version 4, 15 June 1996. 

[3] M. Perakis, A.E. Tzimas, E.G. Metaxakis, D. Soudris, G.A. Kalivas, C. Katis, C. Dre, C.E. Goutis, 

and A. Thanailakis, “The VLSI Implementation of a Baseband Receiver For DECT-Based Portable 

Applications,” in Int. Symp. on Circuits and Systems (ISCAS), Orlando, Florida, USA, May 30 - 

June 2, 1999, Vol. I pp. 198-201. 

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[4] N.Zervas, D. Soudris, S. Theoharis, C.E. Goutis, and A. Thanailakis, A Methodology for the 

Behavioral-Level Event-Driven Power Management of Digital Receivers, accepted for 

presentation at ISCAS 2000, May 28 - 31, Geneva, Switzerland. 

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