CMPE100, Fall 2003 Midterm Review Guide

S.C. Petersen, Cmpe100L F03\Midterm Reviw.doc 1
CMPE100, Fall 2003
Midterm Review Guide
Our exam will be based on assigned homework, relevant supporting sections from the Textbook and material
introduced in lecture. General coverage will be up to where we stopped at the end of Chapter 5 in Wakerly. There
may be some questions on VHDL or HDL’s.
Practical Electrial Topics:
• Notably taken from Ch-3; use the homework, lecture and labwork as a guide to guage depth of treatment.
• Understand how voltage maps to logic states.
• Be able to interpret a datasheet and find relevant parameters, like those necessary to determine DC fanout,
logic high and low noise margins.
• Be able to draw a simple timing diagram showing how an output varies in time with several logic inputs;
time delay could also be involved.
• Know what defines a logic family and what needs to be considered when mixing them.
• Floating inputs.
• The difference between AC and DC fanout.
Combinational Logic Skills (Ch-4):
• Basically the content of Ch-4 limited to what we discussed in lecture and assigned in homework.
• Switching algebra; axioms and theorems; perfect induction; duality and complementarity.
• The relationship between DeMorgans’s theorem and duality.
• Basic definitions on page 207.
• Be able form the Cononical Sum and Product expressions from a truth table, a Boolean equation, or directly
off a K-Map.
• Multilevel combinational logic circuits: And-Or; Nand-Nand etc.
• How SOP and POS forms are related and what they tell us.
• Minimization techniques involving K-maps. K-map problems will be limited to 4-variables or less. But
there may be conceptual questions about 5 or 6 variable K-maps.
• Be able to find a minimal sum or minmal product using K-maps. You may be asked to cover 1’s or 0’s for
find either type.
• Clearly understand the underlying basis of Karnaugh Maps: logical adjacency and what theorems are
expressely involved.
• Static hazards; static-1 and static-0. Understand how to fix them using k-maps.
• The practical significance of logic levels.
• Hazard covers and their relation to propagation delay.
Practical MSI Logic blocks (Ch-5):
• Based on what we covered in Ch-5. Note that you are not expected to memorize various chips discussed in
this chapter, like the 74138, 139 etc. If they appear on the exam, suitable datasheets or block diagrams will
be made available.
• Documentation Standards; differences between a block diagram and and engineering schematic.
• Logically equivalent gate symbols using DeMorgan’s theorem.
• Active high and active low signals; “assertion levels.”
• Bubble-to-bubble logic design.
• Timing diagrams basics (sec. 5.2); propagation delay.
• Binary decoders (74139, 74138); possible simple problem involving cascading these devices.
• 7-segment decoders.
• Priority Encoders (74148).
• Multiplexers (74151, 74157).
• Understand how comparators work, and how XOR gates are used inside them.
• Understand the difference between Half and Full Adders.
• Understand problems 5.46 and 5.82.

S.C. Petersen, Cmpe100L F03\Midterm Reviw.doc 2
Number Systems and Codes (Ch-2):
• Problems will principally be based on those given in the homework and discussed and lecture.
• Representation and conversion of numbers between different bases. There will be no exotic number bases;
Expect 2, 8, 10 and 16 mostly. You may be asked to convert between bases not listed here.
• Negative number representations: 1 and 2’s complement; able to work easily with 2’s complement numbers.
• Understand the basic idea behind Gray codes.