Hardware Flowchart - SERC - Indian Institute of Science

CISC Processor Design
Hardware Flowchart
Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org
Computer
Design
Laboratory
& Test
Advance Computer Architecture

Processor - Block Diagram
Clock-Phase Reset & Power-On Logic
Generator
Bus Controller
Interrupt Logic
Control
Store
Next State
Control
Branch Control
unit
IR
Decoder
Encoded Control Word Fields
Control Word Decoder
Decoded d Datapath Control
Instruction
Prefetch
Register
Address
Out Reg.
PC R0 R1
Internal A Bus
Rn Shifter ALU
Internal B Bus
Datapath
Data
Reg.
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Design
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Hardware Flowchart
Hardware Flowchart
‣ Tells us how to get from the architecture to the
implementation
i
‣ Links programmer’s (external) model and the
hardware (internal) implementation
‣ Specify exactly how commands from the
instruction set are carried out using Datapath
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Design
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Hardware Flowchart
Pre-requisites: ii
Instruction set summary
‣ Instruction Format
‣ Operations
‣ Addressing modes
‣ Registers
Datapath
‣ Programmer’s register set
‣ Additional registers
‣ ALU and any special
functional units
‣ Internal data paths
‣ Rules of operation
• Datapath will evolve
Advance Computer Architecture 4
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Design
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Development of
Implementation
Clock Phase
Generator
Datapath
‣ The architecture
t
specification is the only
input
‣ Begin with a guess of
Datapath
‣ Do flowchart for the
instructions
‣ This modifies and
refines the Datapath
and develops the
control store and
control strategy
‣ The final Datapath is
derived output
Advance Computer Architecture 5
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Design
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Development of
Implementation
Clock Phase
Generator
Control
Store
Control Word
‣ Once flowcharts are
fairly complete, derive
the control word
format using the
flowchart states
‣ When the flowcharts
are complete, so is
the Datapath
‣ Control word format
is derived output
Datapath
Advance Computer Architecture 6
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Design
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Development of
Implementation
Clock Phase
Generator
Control
Store
‣ After defining control
word format, you
assign bit patterns to
the control fields in a
way that minimizes
control word decoders
between the control
store and the
Datapath
Control Word Decoder
Datapath
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Design
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Development of
Implementation
Clock Phase
Generator
Control
Store
Instruction
Decoder
‣ Instruction decoders
are defined the
flowcharts and the
architecture
specification
Control Word Decoder
Datapath
Advance Computer Architecture 8
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Design
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Development of
Implementation
Clock Phase
Generator
Control
Store
Bus Controller
Instruction
Decoder
‣ Completed flowchars,
control word format,
and the initial bus
specification defines
the bus controller
Control Word Decoder
Datapath
Advance Computer Architecture 9
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Design
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Development of
Implementation
Clock Phase
Generator
Control
Store
Control Word Decoder
State
Sequencer
Datapath
Bus Controller
Instruction
Decoder
‣ Last is the logic of the
state sequencer, the
part of the chip that
says what to do next
(where is the next
control word?)
‣ Once every thing
around it is defined,
you build exactly
what you need! (The
state sequencer is
derived output)
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Flowchart Objective
Flowchart Objective
‣ Limit controller size to some fraction of chip area
‣ Make CPU as fast as possible
‣ Complete the project as early as possible
‣ Make the flowcharts easy to translate into
hardware
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MIN Instruction ti Set
Instruction Format
First Word
Op-code Rx Mode Ry
Operation First Second First
Code
Operand
Register
Second Word
Operand
Address
Mode
Displacement
st
Operand
Register
Optional, depending on second operand address mode
Programmer’s
Register Set
R0
R1
R2
.
.
.
Rn
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MIN Instruction ti Set
MIN Instruction Set
ADD
AND
BZ – Branch if zero bit is set. (Register Indirect only)
LOAD – Second operand is source and Rx is destination
POP – Postincrement with register indirect only
PUSH – Predecrement with register indirect only
STORE
SUB
TEST
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MIN Instruction ti Set
Second Operand Address
Mode
Second Operand
Address Mode
Ry
First Operand
Register
Address Modes
‣ AB - Base (Ry) plus displacement (second instruction
word) is an operand address
‣ AI – Register indirect. Ry holds an operand address
‣ AR – Register direct: The result is stored in Ry. For two
operand dinstructions, ti Ry also is an operand source
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MIN Datapath
th
IRE
IRF
Internal A Bus
DO
AO PC T2 R0 R1 Rn T1 ALU
k
Internal B Bus
DI
External Address
Bus (EAB)
External Data
Bus (EDB)
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MIN Datapath
th
Rules of Operation
1. A transfer from source to bus to destination takes one state time
2. A source can drive up to three destination loads
3. Inputs to the ALU are from A (internal) bus and either k (values 0,
+1, -1) or the B (internal) bus
4. When ALU is destination. Ti is automatically loaded from the ALU
output
5. A transfer to AO activates the on-chip external bus controller. This
bus controller postpones the next state until the external transfer
is complete.
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Flowcharts
ADD RX AR RY
ADD RX AI (RY)
Register-to-Register
Register-to-Memory
R → R ADD R → M ADD
rx → a → alu
ry → b → alu
edb → di
ry → b → ao
State
t1 → b → ry
di → b → alu
rx → a → alu
Sequence
IRE
Internal
AO PC T2 R0 R1 A Bus
Rn T1 ALU
Internal
B Bus
IRF
DO
k
DI
ry → b → ao
t1 → a → do
Advance Computer Architecture 17
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Design
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Flowcharts
ADD RX AR RY
Register-to-Register
R → R
edb → if irf
pc → b → ao
rx → a → alu
ry → b → alu
t1 → b → ry
pc → a → alu
+1 → alu
t1 → b → pc
ADD
ADD RX AI (RY)
Register-to-Memory
R → M ADD
edb → irf
pc → b → ao
edb → di
ry → b → ao
di → b → alu
rx → a → alu
ry → b → ao
t1 → a → do
pc → a → alu
+1 → alu
t1 → b → pc
‣ Execution
Speed
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Design
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MIN Datapath
th
IRE
IRF
Internal A Bus
DO
AO PC T2 R0 R1 Rn T1 ALU
k
Internal B Bus
DI
External Address
Bus (EAB)
External Data
Bus (EDB)
Advance Computer Architecture 19

Level 1 Flowchart - ADD
ADD RX AR RY
Register-to-Register
R → R
ADD
rx → a → alu
ry → b → alu
edb → irf
pc → b → ao
pc → a → alu
+1 → alu
t1 → b → ry
irf → ire
t1 → b → pc
IRE
IRF
Operation
tasks
Housekeeping
tasks
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
Internal
B Bus
(EAB)
DO
k
DI
(EDB)
Advance Computer Architecture 20

Level 2 Flowchart - ADD
R → R
ADD RX AR RY
Register-to-Register
rx → a → alu
ry → b → alu
t1 → b → ry
ADD
edb → irf
pc → b → ao
pc → a → alu
+1 → alu
irf → ire
t1 → b → pc
R → R
rx → a → alu
ry → b → alu
ADD
edb → irf
pc → a → alu, ao
t1 → b → ry
+1 → alu
irf → ire
t1 → b → pc
Merger
• Speed
• Identical states
Advance Computer Architecture 21

Level 2 Flowchart - ADD
ADD RX AI (RY)
R → M ADD
Register-to-Memory
edb → irf
R → M ADD
pc → a → alu, ao
edb → di
edb → irf
+1 → alu
ry → b → ao
di → b → alu
rx → a → alu
pc → b → ao
pc → a → alu
+1 → alu
edb → di
ry → b → ao
t1 → a → pc
ry → b → ao
t1 → a → do
Internal
AO PC R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
irf → ire
t1 → b → pc
IRE
k
IRF
DO
DI
(EDB)
di → b → alu
rx → a → alu
t1 → a → do
ry → b → ao
irf → ire
Advance Computer Architecture
22

Level 2 Flowchart - ADD
ADD RX AI (RY)
Register-to-Memory
R → M ADD
edb → di
ry → b → ao
di → b → alu
rx → a → alu
ry → b → ao
t1 → a → do
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
R → M
di → b → alu
rx → a → alu
irf → ire
t1 → a → do
t2 → b → ao
ADD
edb → irf
edb → irf
pc → a → alu, ao
pc → b → ao
+1 → alu
pc → a → alu
edb → di
+1 → alu
ry → b → ao, t2
t1 → a → pc
irf → ire
t1 → b → pc
IRE
k
IRF
DO
DI
(EDB)
Advance Computer Architecture
23

Level 2 Flowchart - ADD
ADD RX AR RY
Register-to-Register
R → R ADD
rx → a → alu
when AO is connected
ry → b → alu
to B (internal) bus only
edb → irf
pc → b → ao
Do level2 flowchart of the fastest
instruction
t1 → a → ry
Point out inadequacy in Datapath
pc → a → alu
+1 → alu
IRE
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
k
IRF
DO
DI
(EDB)
irf → ire
t1 → b → pc
Advance Computer Architecture
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Flowchart
Flowchart
‣ How many sequences?
‣ Motorola 68000 (14 address modes and 50
instruction types)
Control Word Sequence
‣ Address Mode Sequence
‣ Calculate address (may or may not include operand fetch)
‣ Execution Sequence
‣ Completes the execution (after address mode sequence)
Advance Computer Architecture
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Control Word Sequence
Address Mode Sequence
‣ Can be shared for different instructions
‣ Calculate l the operand address
‣ Fetch the operand
‣ Place the operand in DIN
Execution Sequence
‣ Address mode sequences can be shared
‣ Find the operand in DIN
‣ Execute the instruction (without knowing how the address
was calculated etc..)
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26

Level1 Flowchart
Level1 Flowchart
‣ At the beginning of instruction execution, IRE is
assumed to contain the current instruction
i
‣ Instruction execution begins with the address
mode sequence
‣ The execution sequences for Register-to-
Register instructions cannot be shared
‣ The execution sequences for standard dual
operand instructions are identical
Advance Computer Architecture
27

Level 1 Flowchart-
Address Mode Sequences
Base Plus Displacement
Register Indirect
edb → di
pc → a → alu, ao
+1 → alu
edb → di
ry → b → ao, t2
t1 → a → pc
di → b → alu
ry → a → alu
edb → di
t1 → b → ao, t2
Advance Computer Architecture
IRE
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
28
IRF
DO
k
DI
(EDB)

Level 1 Flowchart-
Address Mode Sequences
Branch Instruction
ti
edb → irf
ry → a → alu, ao
+1 → alu
IRE
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
IRF
DO
k
DI
(EDB)
Z = 1 (Branch)
irf → ire
t1 → b → pc
Z = 0 (no branch)
edb → irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → b → pc
Advance Computer Architecture
29

Level 1 Flowchart -
Execution Sequences
Execution sequences with memory operand reference
LOAD
di → b → rx, t2
edb → if irf
pc → a → alu, ao
+1 → alu
STORE
rx → a → alu, do
edb → if irf
t2 → b → ao pc → a → alu, ao
0 → alu +1 → alu
t2 → a → alu
0 → alu
irf → ire
t1 → b → pc
irf → ire
t1 → b → pc
IRE
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
IRF
DO
k
DI
(EDB)
Advance Computer Architecture
30

Level 1 Flowchart -
Execution Sequences
Execution sequences with memory operand reference
di → b → alu
rx → a → alu
ADD
edb → if irf
pc → a → alu, ao
+1 → alu
di → b → alu
rx → a → alu
SUB
edb → irf
pc → a → alu, ao
+1 → alu
t1 → a → do
t2 → b → ao
irf → ire
t1 → b → pc
t1 → a → do
t2 → b → ao
irf → ire
t1 → b → pc
IRE
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
IRF
DO
k
DI
(EDB)
Advance Computer Architecture
31

Level 1 Flowchart -
Execution Sequences
Execution sequences with memory operand reference
di → b → alu
rx → a → alu
AND
edb → if irf
pc → a → alu, ao
+1 → alu
di → b → t2
TEST
edb → irf
pc → a → alu, ao
+1 → alu
t1 → a → do
t2 → b → ao
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
irf → ire
t1 → b → pc
IRE
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
IRF
DO
k
DI
(EDB)
Advance Computer Architecture
32

Level 1 Flowchart -
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
LOAD
ry → a → alu,rx
0 → alu
edb → if irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → a → pc
rx → a → alu, ry
0 → alu
STORE
edb → if irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → a → pc
IRE
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
IRF
DO
k
DI
(EDB)
Advance Computer Architecture
33

Level 1 Flowchart -
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
rx → a → alu
ry → b → alu
ADD
edb → if irf
pc → a → alu, ao
+1 → alu
rx → a → alu
ry → b → alu
SUB
edb → irf
pc → a → alu, ao
+1 → alu
t1 → a → ry
irf → ire
t1 → a → pc
t1 → a → ry
irf → ire
t1 → a → pc
IRE
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
IRF
DO
k
DI
(EDB)
Advance Computer Architecture
34

Level 1 Flowchart -
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
POP
edb → di
ry → a → alu, ao
+1 → alu
edb → if irf
pc → a → alu, ao
+1 → alu
ry → a → alu
-1 → alu
PUSH
edb → if irf
pc → a → alu, ao
+1 → alu
di → b → rx
t1 → a → ry
irf → ire
t1 → a → pc
rx → a → do
t1 → b → ao, ry
irf → ire
t1 → a → pc
IRE
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
IRF
DO
k
DI
(EDB)
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35

Merged Level 1 Flowchart:
Address Mode Sequences
Base Plus Displacement
Register Indirect
edb → di
pc → a → alu, ao
+1 → alu
t1 → a → pc
di → b → alu
ry → a → alu
abdm1
abdm2
abdm3
edb → di
ry → b → ao, t2
adrm1
edb → di
Internal
A Bus
t1 → b → ao, t2
AO PC T2 R0 R1 Rn T1 ALU
abdm4
(EAB)
Advance Computer Architecture
Internal
B Bus
36
IRE
k
IRF
DO
DI
(EDB)

Merged Level 1 Flowchart:
Address Mode Sequences
Branch Instruction
ti
edb → irf
ry → a → alu, ao
+1 → alu
brzz1
IRE
Internal
AO PC T2 R0 R1
A Bus
Rn T1 ALU
(EAB)
Internal
B Bus
IRF
DO
k
DI
(EDB)
Z = 1 (Branch)
irf → ire
t1 → b → pc
brzz2
Z = 0 (no branch)
edb → irf
pc → a → alu, ao
+1 → alu
brzz3
irf → ire
t1 → b → pc
brzz4
Advance Computer Architecture
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
LOAD
di → b → rx, t2
edb → if irf
pc → a → alu, ao
+1 → alu
LOAD
di → b → rx, t2
edb → irf
pc → a → alu, ao
+1 → alu
t2 → a → alu
0 → alu
irf → ire
t1 → b → pc
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
ldrm1
ldrm2
Advance Computer Architecture
38

Merged Level 1 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
STORE
STORE
rx → a → alu, do
edb → if irf
t2 → b → ao pc → a → alu, ao
0 → alu +1 → alu
rx → a → alu, do
t2 → b → ao
0 → alu
strm1
irf → ire
t1 → b → pc
edb → irf
pc → a → alu, ao
+1 → alu
strm2
irf → ire
t1 → b → pc
strm3
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
ADD, AND, SUB
di → b → alu
rx → a → alu
t1 → a → do
t2 → b → ao
ADD
edb → if irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → b → pc
di → b → alu
rx → a → alu
t1 → a → do
t2 → b → ao
edb → irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → b → pc
oprm1
oprm2
oprm3
oprm4
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
di → b → t2
t2 → a → alu
0 → alu
TEST
edb → irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → b → pc
TEST
di → b → t2
edb → irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
test1
test2
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
LOAD
ry → a → alu,rx
0 → alu
edb → if irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → a → pc
LOAD
edb → irf
pc → a → alu, ao
ry → a → rx, t2
+1 → alu
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
ldrr1
ldrr2
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register and special instructions
STORE
STORE
rx → a → alu, ry
0 → alu
edb → if irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → a → pc
edb → irf
pc → a → alu, ao
rx → b → ry, t2
+1 → alu
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
strr1
strr2
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
rx → a → alu
ry → b → alu
t1 → a → ry
ADD
edb → if irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → a → pc
ADD, SUB, AND
rx → a → alu
ry → b → alu
edb → irf
pc → a → alu, ao
t1 → a → ry
+1 → alu
oprr1
oprr2
irf → ire
t1 → a → pc
oprr3
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Level 1 Flowchart -
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
POP
edb → di
ry → a → alu, ao
+1 → alu
di → b → rx
t1 → a → ry
edb → if irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → a → pc
POP
edb → di
ry → a → alu, ao
+1 → alu
di → b → rx
t1 → a → ry
edb → irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → a → pc
popr1
popr2
popr3
popr4
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Merged Level 1 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
PUSH
PUSH
ry → a → alu
-1 → alu
edb → irf
push1
ry → a → alu
pc → a → alu, ao
-1 → alu
rx → a → do
+1 → alu
t1 → b → ao, ry
push2
rx → a → do
t1 → b → ao, ry
irf → ire
t1 → a → pc
edb → irf
pc → a → alu, ao
+1 → alu
irf → ire
t1 → a → pc
push3
push4
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Level 2 Flowcharts
Format for Level 2 flowchart state ‣ DR – Data Read
‣ DW – Data Write
Label A
Label B
‣ IR - Instruction Read
Access Type ‣ NA – No aceess
State ID
Tasks
Synonym
ALU and CC •S–Set
Duplicates •N–Not set
Page and Loc
•X–Don’t care
Acess
Next State • BC – Branch conditionally
Width
• IB – Instruction branch
• SB – Sequence branch
• StateID – Direct branch
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Level 2 Flowchart:
Address Mode Sequences
Base Plus Displacement
(RY+d)@
edb → di
pc → a → alu, ao
+1 → alu
ir
add-n
di → b → alu
ry → a → alu
na
add-n
abdm1
t1 → a → pc
abdm2
na
x-n
abdm3
edb → di
t1 → b → ao, t2
abdm4
dr
x-n
abdm2
abdm3
abdm4
sb
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Level 2 Flowchart:
Address Mode Sequences
Register Indirect
RY@
edb → di
ry → b → ao, t2
adrm1
dr
x-n
sb
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Level 2 Flowchart:
Address Mode Sequences
Branch Instruction
edb → irf
ry → a → alu, ao
+1 → alu
brzz1
ir
add-n
bc
Z = 0 (no branch)
Z = 1 (Branch)
na
irf → ire
x-n
t1 → b → pc
brzz2
ib
edb → irf
pc → a → alu, ao
+1 → alu
brzz3
irf → ire
t1 → b → pc
ir
add-n
brzz4
na
x-n
Advance Computer Architecture
brzz4
50
ib

Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
Mem → RX
di → b → rx, t2
edb → irf
pc → a → alu, ao
+1 → alu
ldrm1
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
ldrm2
LOAD
ir
add-x
ldrm2
na
add-s
ib
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Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
RX → Mem
rx → a → alu, do
t2 → b → ao
0 → alu
STORE
dw
add-s
strm1
strm2
edb → irf
pc → a → alu, ao
+1 → alu
ir
add-n
irf → ire
t1 → b → pc
strm3
na
x-n
ib
strm2
strm3
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Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
RX OP Mem → Mem
ADD, AND, SUB
di → b → alu
rx → a → alu
na
op-s
edb → irf
pc → a → alu, ao
+1 → alu
ir
add-n
oprm1 oprm2 oprm3 oprm3
t1 → a → do
t2 → b → ao
dw
x-s
irf → ire
t1 → b → pc
oprm2 oprm3 oprm4 ib
na
x-n
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Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
Mem → ALU TEST
di → b → t2
edb → if irf
pc → a → alu, ao
+1 → alu
test1
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
test2
ir
add-x
test2
na
add-s
ib
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Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
RX OP RY → RY
ADD, SUB, AND
rx → a → alu
ry → b → alu
na
op-s
irf → ire
t1 → a → pc
na
x-n
oprr1
oprr2
edb → irf
pc → a → alu, ao
t1 → a → ry
+1 → alu
ir
add-n
oprr3
ib
oprr2
oprr3
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Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
RX → RY
edb → irf
pc → a → alu, ao
ry → a → rx, t2
+1 → alu
ldrr1
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
LOAD
ir
add-x
ldrr2
na
add-s
RX → RY
edb → irf
pc → a → alu, ao
rx → b → ry, t2
+1 → alu
strr1
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
STORE
ir
add-x
strr2
na
add-s
ldrr2 ib strr2 ib
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56
Computer
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Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
RY@ → RX
RY+1 → RY
edb → di
ry → a → alu, ao
+1 → alu POP
dr
add-n
edb → irf
pc → a → alu, ao
+1 → alu
ir
add-n
popr1 popr2 popr3 popr4
di → b → rx
t1 → a → ry
na
x-n
irf → ire
t1 → a → pc
popr2 popr3 popr4 ib
na
x-n
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Merged Level 2 Flowchart:
Address Mode Sequences
Base Plus Displacement
(RY+d)@
edb → di
pc → a → alu, ao
+1 → alu
ir
add-n
di → b → alu
ry → a → alu
na
add-n
abdm1
t1 → a → pc
abdm2
na
x-n
abdm3
edb → di
t1 → b → ao, t2
abdm4
dr
x-n
abdm2
abdm3
abdm4
sb
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Merged Level 2 Flowchart:
Address Mode Sequences
Register Indirect
RY@
edb → di
ry → b → ao, t2
adrm1
dr
x-n
sb
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Merged Level 2 Flowchart:
Address Mode Sequences
Branch Instruction
edb → irf
ry → a → alu, ao
+1 → alu
brzz1
ir
add-n
bc
Z = 0 (no branch)
Z = 1 (Branch)
na
irf → ire
x-n
t1 → b → pc
edb → irf
pc → a → alu, ao
+1 → alu
brzz3
ir
add-n
brzz2
brzz2
ib
Advance Computer Architecture
60
Computer
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Merged Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
Mem → RX
di → b → rx, t2
edb → irf
pc → a → alu, ao
+1 → alu
LOAD
ir
add-x
Mem → RX
rx → a → alu, do
t2 → b → ao
0 → alu
STORE
dw
add-s
ldrm1
ldrm2
strm1
brzz3
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
na
add-s
ldrm2
ib
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Merged Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
RX OP Mem → Mem
di → b → alu
rx → a → alu
ADD, AND, SUB
na
op-s
oprm1
oprm2
t1 → a → do
t2 → b → ao
dw
x-s
Mem → ALU
di → b → t2
edb → irf
pc → a → alu, ao
+1 → alu
test1
TEST
ir
add-x
ldrm2
oprm2
brzz3
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Merged Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
RX → RY
LOAD
RX OP RY → RY ADD, SUB, AND
edb → irf
ir
na
rx → a → alu
pc → a → alu, ao
add-x
op-s
ry → b → alu
ry → a → rx, t2
+1 → alu
oprr1 oprr2 ldrr1 ldrm2
edb → irf
pc → a → alu, ao
t1 → a → ry
+1 → alu
oprr2
ir
add-n
brzz2
RX → RY
edb → irf
pc → a → alu, ao
rx → b → ry, t2
+1 → alu
STORE
ir
add-x
strr1
ldrm2
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Merged Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
RY@ → RX
RY+1 → RY
edb → di
ry → a → alu, ao
+1 → alu
POP
dr
add-n
RY-1 → RY
RY@ → RX
ry → a → alu
-1 → alu
PUSH
na
add-n
popr1
di → b → rx
t1 → a → ry
popr2
na
x-n
push1
rx → a → do
t1 → b → ao, ry
push2
dw
x-n
popr2 brzz3 push2 brzz3
Advance Computer Architecture
64
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Processor Block Diagram
Control
Store
Next
State
Control
IB
SB
BC
DB
Instruction
Decoder
Control Word
Register
OP TY NA
Control Fields (dynamic)
Branch
Control
Control word
Decoders
Control Fields
(Static)
IRE
Control lines
Condition
Codes
IRF
Datapath
Advance Computer Architecture
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Level 2 Flowcharts
Format for Level 2 flowchart state ‣ DR – Data Read
‣ DW – Data Write
Label A
Label B
‣ IR - Instruction Read
Access Type ‣ NA – No aceess
State ID
Tasks
Synonym
ALU and CC •S–Set
Duplicates •N–Not set
Page and Loc
•X–Don’t care
Acess
Next State • BC – Branch conditionally
Width
• IB – Instruction branch
• SB – Sequence branch
• StateID – Direct branch
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Computer
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Level 2 Flowchart:
Address Mode Sequences
Base Plus Displacement
(RY+d)@
edb → di
pc → a → alu, ao
+1 → alu
ir
add-n
di → b → alu
ry → a → alu
na
add-n
abdm1
t1 → a → pc
abdm2
na
x-n
abdm3
edb → di
t1 → b → ao, t2
abdm4
dr
x-n
abdm2
abdm3
abdm4
sb
Advance Computer Architecture
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Computer
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Level 2 Flowchart:
Address Mode Sequences
Register Indirect
RY@
edb → di
ry → b → ao, t2
adrm1
dr
x-n
sb
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Computer
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Level 2 Flowchart:
Address Mode Sequences
Branch Instruction
edb → irf
ry → a → alu, ao
+1 → alu
brzz1
ir
add-n
bc
Z = 0 (no branch)
Z = 1 (Branch)
na
irf → ire
x-n
t1 → b → pc
brzz2
ib
edb → irf
pc → a → alu, ao
+1 → alu
brzz3
irf → ire
t1 → b → pc
ir
add-n
brzz4
na
x-n
Advance Computer Architecture
brzz4
69
ib

Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
Mem → RX
di → b → rx, t2
edb → irf
pc → a → alu, ao
+1 → alu
ldrm1
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
ldrm2
LOAD
ir
add-x
ldrm2
na
add-s
ib
Advance Computer Architecture
70
Computer
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Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
RX → Mem
rx → a → alu, do
t2 → b → ao
0 → alu
STORE
dw
add-s
strm1
strm2
edb → irf
pc → a → alu, ao
+1 → alu
ir
add-n
irf → ire
t1 → b → pc
strm3
na
x-n
ib
strm2
strm3
Advance Computer Architecture
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Computer
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Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
RX OP Mem → Mem
ADD, AND, SUB
di → b → alu
rx → a → alu
na
op-s
edb → irf
pc → a → alu, ao
+1 → alu
ir
add-n
oprm1 oprm2 oprm3 oprm3
t1 → a → do
t2 → b → ao
dw
x-s
irf → ire
t1 → b → pc
oprm2 oprm3 oprm4 ib
na
x-n
Advance Computer Architecture
72
Computer
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Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
Mem → ALU TEST
di → b → t2
edb → if irf
pc → a → alu, ao
+1 → alu
test1
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
test2
ir
add-x
test2
na
add-s
ib
Advance Computer Architecture
73
Computer
Design
Laboratory
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Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
RX OP RY → RY
ADD, SUB, AND
rx → a → alu
ry → b → alu
na
op-s
irf → ire
t1 → a → pc
na
x-n
oprr1
oprr2
edb → irf
pc → a → alu, ao
t1 → a → ry
+1 → alu
ir
add-n
oprr3
ib
oprr2
oprr3
Advance Computer Architecture
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Computer
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Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
RX → RY
edb → irf
pc → a → alu, ao
ry → a → rx, t2
+1 → alu
ldrr1
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
LOAD
ir
add-x
ldrr2
na
add-s
RX → RY
edb → irf
pc → a → alu, ao
rx → b → ry, t2
+1 → alu
strr1
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
STORE
ir
add-x
strr2
na
add-s
ldrr2 ib strr2 ib
Advance Computer Architecture
75
Computer
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Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
RY@ → RX
RY+1 → RY
edb → di
ry → a → alu, ao
+1 → alu POP
dr
add-n
edb → irf
pc → a → alu, ao
+1 → alu
ir
add-n
popr1 popr2 popr3 popr4
di → b → rx
t1 → a → ry
na
x-n
irf → ire
t1 → a → pc
popr2 popr3 popr4 ib
na
x-n
Advance Computer Architecture
76
Computer
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Merged Level 2 Flowchart:
Address Mode Sequences
Base Plus Displacement
(RY+d)@
edb → di
pc → a → alu, ao
+1 → alu
ir
add-n
di → b → alu
ry → a → alu
na
add-n
abdm1
t1 → a → pc
abdm2
na
x-n
abdm3
edb → di
t1 → b → ao, t2
abdm4
dr
x-n
abdm2
abdm3
abdm4
sb
Advance Computer Architecture
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Merged Level 2 Flowchart:
Address Mode Sequences
Register Indirect
RY@
edb → di
ry → b → ao, t2
adrm1
dr
x-n
sb
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Merged Level 2 Flowchart:
Address Mode Sequences
Branch Instruction
edb → irf
ry → a → alu, ao
+1 → alu
brzz1
ir
add-n
bc
Z = 0 (no branch)
Z = 1 (Branch)
na
irf → ire
x-n
t1 → b → pc
edb → irf
pc → a → alu, ao
+1 → alu
brzz3
ir
add-n
brzz2
brzz2
ib
Advance Computer Architecture
79
Computer
Design
Laboratory
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Merged Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
Mem → RX
di → b → rx, t2
edb → irf
pc → a → alu, ao
+1 → alu
LOAD
ir
add-x
Mem → RX
rx → a → alu, do
t2 → b → ao
0 → alu
STORE
dw
add-s
ldrm1
ldrm2
strm1
brzz3
irf → ire
t1 → b → pc
t2 → a → alu
0 → alu
na
add-s
ldrm2
ib
Advance Computer Architecture
80
Computer
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Merged Level 2 Flowchart:
Execution Sequences
Execution sequences with memory operand reference
RX OP Mem → Mem
di → b → alu
rx → a → alu
ADD, AND, SUB
na
op-s
oprm1
oprm2
t1 → a → do
t2 → b → ao
dw
x-s
Mem → ALU
di → b → t2
edb → irf
pc → a → alu, ao
+1 → alu
test1
TEST
ir
add-x
ldrm2
oprm2
brzz3
Advance Computer Architecture
81
Computer
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Merged Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
RX → RY
LOAD
RX OP RY → RY ADD, SUB, AND
edb → irf
ir
na
rx → a → alu
pc → a → alu, ao
add-x
op-s
ry → b → alu
ry → a → rx, t2
+1 → alu
oprr1 oprr2 ldrr1 ldrm2
edb → irf
pc → a → alu, ao
t1 → a → ry
+1 → alu
oprr2
ir
add-n
brzz2
RX → RY
edb → irf
pc → a → alu, ao
rx → b → ry, t2
+1 → alu
STORE
ir
add-x
strr1
ldrm2
Advance Computer Architecture
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Merged Level 2 Flowchart:
Execution Sequences
Execution sequences for Register-to-Register to and special instructions
RY@ → RX
RY+1 → RY
edb → di
ry → a → alu, ao
+1 → alu
POP
dr
add-n
RY-1 → RY
RY@ → RX
ry → a → alu
-1 → alu
PUSH
na
add-n
popr1
di → b → rx
t1 → a → ry
popr2
na
x-n
push1
rx → a → do
t1 → b → ao, ry
push2
dw
x-n
popr2 brzz3 push2 brzz3
Advance Computer Architecture
83
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Processor Block Diagram
Control
Store
Next
State
Control
IB
SB
BC
DB
Instruction
Decoder
Control Word
Register
OP TY NA
Control Fields (dynamic)
Branch
Control
Control word
Decoders
Control Fields
(Static)
IRE
Control lines
Condition
Codes
IRF
Datapath
Advance Computer Architecture
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& Test

Thank You
Advance Computer Architecture 85
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