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Introducing:<br />
The <strong>Calibre</strong> nm Platform and<br />
<strong>Calibre</strong> <strong>nmDRC</strong><br />
Joe Sawicki<br />
VP and GM, Design to Silicon Division<br />
June/July 2006
Yield Issues in Nanometer Technologies<br />
Random<br />
Systematic<br />
Parametric<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
2
The Wonderful and Frightening World of<br />
Physical Verification and DFM<br />
Additional DFM Rules<br />
Total Geometric Shape Count<br />
Critical Area Analysis<br />
Litho-friendly Design<br />
Recommended Rules<br />
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010<br />
100.00<br />
90.00<br />
80.00<br />
70.00<br />
60.00<br />
50.00<br />
40.00<br />
30.00<br />
20.00<br />
10.00<br />
-<br />
130nm 90nm 65nm<br />
45nm<br />
Rules with 3 metal layers<br />
Total DRC rules<br />
Additional metal rules<br />
Design Size<br />
(Geometry Count)<br />
700<br />
10<br />
600<br />
9<br />
500<br />
8<br />
400<br />
7<br />
300<br />
6<br />
Basic DRC Rules<br />
200<br />
100<br />
5<br />
4<br />
0<br />
3<br />
0.35um 0.25um 0.18um 0.13um 0.09um<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
3
Computational Complexity<br />
Additional DFM Rules<br />
90 nm<br />
Design Size<br />
(Geometry Count)<br />
Basic DRC Rules<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
4
Computational Complexity<br />
Additional DFM Rules<br />
90 nm<br />
65 nm<br />
Design Size<br />
(Geometry Count)<br />
Basic DRC Rules<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
5
Computational Complexity<br />
Additional DFM Rules<br />
45 nm<br />
90 nm<br />
65 nm<br />
Design Size<br />
(Geometry Count)<br />
Basic DRC Rules<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
6
Design: Seeing through the Fog<br />
Original Design Data<br />
Typical DRC Result<br />
Typical DFM Result<br />
DRC Rule<br />
DFM Rule<br />
130nm<br />
200nm<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
7
Complexity Drives a Change From Rules to<br />
Models<br />
• Major DFM capabilities are<br />
moving from a rules-based<br />
approach to a models-based<br />
Probability<br />
D(s):Defect Distribution<br />
C(s):Critical Area<br />
Yield=exp(-C(s)*D(s))<br />
approach<br />
Defect size<br />
— Critical Area Analysis (CAA)<br />
— Litho-friendly Design (LFD)<br />
pinching<br />
Increasing complexity and the rise in multiple<br />
issues will force this trend to continue.<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
8
Yesterday’s <strong>Calibre</strong> Platform<br />
Layout Data<br />
<strong>Calibre</strong> PVX<br />
Results Data<br />
Data Query<br />
Results Viewing<br />
Layout Update<br />
GDSII<br />
OASIS<br />
Schematic<br />
Netlist<br />
DRC/LVS<br />
xRC/xL<br />
SVRF/CAPI<br />
MTflex<br />
Derived Layout<br />
& Error Markers<br />
Devices &<br />
Parasitics<br />
Data Query<br />
Results<br />
Viewing<br />
GDSII<br />
OASIS<br />
Post Layout<br />
Netlist<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
9
The New <strong>Calibre</strong> nm Platform<br />
Layout Data<br />
<strong>Calibre</strong> PVX<br />
Results Data<br />
Data Query<br />
Results Viewing<br />
Layout Update<br />
GDSII<br />
OASIS<br />
Schematic<br />
Netlist<br />
DRC/LVS<br />
xRC/xL<br />
SVRF/CAPI<br />
MTflex<br />
Derived Layout<br />
& Error Markers<br />
Devices &<br />
Parasitics<br />
Data Query<br />
Results<br />
Viewing<br />
GDSII<br />
OASIS<br />
Post Layout<br />
Netlist<br />
Design and<br />
Mfg. Data<br />
LEF/DEF<br />
Milky Way<br />
Open Access<br />
Mfg Models &<br />
Parameters<br />
Performance<br />
Constraints<br />
<strong>Calibre</strong> Analysis<br />
& Enhancement<br />
Recommended<br />
Rules & CAA<br />
Litho Friendly<br />
Design<br />
Device and<br />
Interconnect<br />
Modeling<br />
Layout<br />
Modifications<br />
TVF (TCL)<br />
Hyperflex<br />
DFM Data<br />
Original<br />
Layout<br />
Hierarchy &<br />
Connectivity<br />
Analysis<br />
Results<br />
Enhancement<br />
Results<br />
Rule<br />
Derivations<br />
Optimization<br />
Constraint<br />
Based<br />
Filtering<br />
Incremental<br />
Analysis<br />
Incremental<br />
Enhancement<br />
Results Analysis<br />
Reports &<br />
Visualization<br />
Silicon<br />
DeBug<br />
Design DB<br />
Update<br />
Design Update<br />
LEF/DEF<br />
Milky Way<br />
Open Access<br />
Sensitivity<br />
Analysis<br />
Design Quality<br />
Assessment<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
10
<strong>Calibre</strong> nm Platform<br />
Layout Data<br />
<strong>Calibre</strong> PVX<br />
Results Data<br />
Data Query<br />
Results Viewing<br />
Layout Update<br />
GDSII<br />
OASIS<br />
Schematic<br />
Netlist<br />
DRC/LVS<br />
xRC/xL<br />
SVRF/CAPI<br />
MTflex<br />
Derived Layout<br />
& Error Markers<br />
Devices &<br />
Parasitics<br />
Data Query<br />
Results<br />
Viewing<br />
GDSII<br />
OASIS<br />
Post Layout<br />
Netlist<br />
Design and<br />
Mfg. Data<br />
LEF/DEF<br />
Milky Way<br />
Open Access<br />
Mfg Models &<br />
Parameters<br />
Performance<br />
Constraints<br />
<strong>Calibre</strong> Analysis<br />
& Enhancement<br />
Recommended<br />
Rules & CAA<br />
Litho Friendly<br />
Design<br />
Device and<br />
Interconnect<br />
Modeling<br />
Layout<br />
Modifications<br />
TVF (TCL)<br />
Hyperflex<br />
DFM Data<br />
Original<br />
Layout<br />
Hierarchy &<br />
Connectivity<br />
Analysis<br />
Results<br />
Enhancement<br />
Results<br />
Rule<br />
Derivations<br />
Optimization<br />
Constraint<br />
Based<br />
Filtering<br />
Incremental<br />
Analysis<br />
Incremental<br />
Enhancement<br />
Results Analysis<br />
Reports &<br />
Visualization<br />
Silicon<br />
DeBug<br />
Design DB<br />
Update<br />
Design Update<br />
LEF/DEF<br />
Milky Way<br />
Open Access<br />
Sensitivity<br />
Analysis<br />
Design Quality<br />
Assessment<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
11
Introducing <strong>Calibre</strong> <strong>nmDRC</strong><br />
Block & Cell<br />
Creation<br />
Place & Route<br />
Chip<br />
Assembly<br />
<strong>Calibre</strong><br />
DRC<br />
<strong>Calibre</strong> <strong>nmDRC</strong><br />
Tapeout<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
12
Achieving Faster Turn Around Times (TAT)<br />
Data Multi and CPU Operation Single Data CPU<br />
Partitioning<br />
Operations<br />
Operations<br />
Operations<br />
Thread Thread Scheduler Scheduler<br />
Data<br />
Data<br />
CPU<br />
CPU<br />
CPU<br />
CPU<br />
CPU<br />
CPU Utilization<br />
Cell/bin<br />
Operation<br />
Data<br />
CPU<br />
CPU<br />
Time<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
13
Multiprocessing Environment<br />
SMP Machine<br />
SMP<br />
Memory<br />
In-Memory<br />
Management<br />
Databse<br />
Single<br />
CPU<br />
Schedule<br />
Management<br />
Distributed<br />
SM Ext.<br />
Multi-Core Cluster<br />
Distributed Machines<br />
SMP<br />
CPU<br />
CPU<br />
CPU<br />
CPU<br />
CPU<br />
CPU<br />
CPU 1<br />
CPU 2<br />
CPU 1<br />
CPU 2<br />
Multi-Core<br />
Cluster<br />
Distributed<br />
MM Ext.<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
14
<strong>Calibre</strong> <strong>nmDRC</strong><br />
Performance Improvement<br />
• Hyperscaling provides a dramatic speed up<br />
• Excellent scaling over a<br />
range of job sizes and<br />
types<br />
Run Time ( hr )<br />
70<br />
60<br />
50<br />
40<br />
30<br />
20<br />
10<br />
0<br />
Customer<br />
DB Size,<br />
Design Node<br />
Single CPU vs. Hyperscaling - Distributed<br />
A<br />
Single CPU<br />
Hyperscaling - Distributed<br />
B<br />
C D E F<br />
1 2 Customer 3 Designs 4 5 6<br />
0.5GB, 90nm 6.8GB, 130nm 7GB 7.2GB, 90nm 11GB, 90nm 1.3GB, 90nm<br />
CPU's<br />
40 40 32 24 32 40<br />
Run Time 0:18 1:19 2:01 1:00<br />
2:18 0:48<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
15
<strong>Calibre</strong> <strong>nmDRC</strong><br />
Performance Improvement - SMP<br />
• Hyperscaling delivers improved TAT on existing CAPEX<br />
Traditional MT (SMP) vs. HyperScaling (SMP)<br />
— Extends life<br />
— Supports a wide range<br />
of H/W platforms<br />
— Does not require H/W<br />
investment<br />
Run Time ( hr )<br />
25<br />
20<br />
15<br />
10<br />
5<br />
-<br />
18GB,<br />
80nm Chip,<br />
16CPU<br />
1.2GHz<br />
1.3GB,<br />
90nm Chip,<br />
16CPU<br />
1.2GHz<br />
6.8GB,<br />
130nm Test,<br />
24CPU<br />
1.2GHz<br />
7.2GB,<br />
90nm Mask,<br />
24CPU<br />
1.2GHz<br />
Traditional MT<br />
Hyperscaling - SMP<br />
4.3GB,<br />
90nm Chip,<br />
4CPU<br />
2.8GHz<br />
10.2GB,<br />
90nm Chip,<br />
4CPU<br />
2.8GHz<br />
Customer Designs (Size, Node, Design Type, CPUs, Scaling, Utilization)<br />
• Average improvement 1.9x<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
16
<strong>Calibre</strong> <strong>nmDRC</strong><br />
Performance Improvement - Distributed<br />
• Hyperscaling provides fast TAT on distributed hardware<br />
Traditional Mtflex (Distributed) vs. Hyperscaling (Distributed)<br />
8<br />
7<br />
Traditional MTflex<br />
Run Time ( hr )<br />
6<br />
5<br />
4<br />
3<br />
2<br />
Hyperscaling - Distributed<br />
1<br />
-<br />
1.3GB,<br />
90nm<br />
Full_Chip,<br />
40CPU<br />
6.8GB, 130nm<br />
Test_Pat.,<br />
40CPU<br />
0.47GB,<br />
90nm<br />
Full_Chip,<br />
40CPU<br />
7.2GB,<br />
90nm<br />
Mask, 24CPU<br />
1.2GB,<br />
90nm<br />
Test_Pat.,<br />
40CPU<br />
2.8GB,<br />
90nm<br />
Full_Chip,<br />
40CPU<br />
4.0GB,<br />
90nm<br />
Full_Chip,<br />
8CPU<br />
0.6GB,<br />
90nm<br />
Memory,<br />
40CPU<br />
0.7GB,<br />
90nm<br />
Full_Chip,<br />
40CPU<br />
0.15GB, 70nm<br />
Memory,<br />
24CPU<br />
Customer Designs (Size, Node, Design Type, CPUs, Scaling, Utilization)<br />
• Average improvement 2.9x<br />
• 4 longest designs improved by 3.8x<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
17
Performance Scaling with Design Size<br />
Performance Impact with Design Size<br />
4<br />
3<br />
Run Time (hours)<br />
2<br />
1<br />
0<br />
32 CPU’s<br />
8 16 27<br />
GDS File Size (Gb)<br />
Performance insensitive to data volume<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
18
<strong>Calibre</strong> <strong>nmDRC</strong>: Drops Into Current CAD<br />
Environment Without Disruption<br />
Encryption<br />
Rule<br />
Files<br />
Design Environments<br />
Interactive,<br />
Batch<br />
Invocation,<br />
Control<br />
Modification<br />
Flows<br />
<strong>Calibre</strong><br />
DRC<br />
<strong>Calibre</strong> <strong>nmDRC</strong><br />
Reporting<br />
Formats<br />
Debug<br />
Methodologies<br />
Design<br />
Data<br />
Trained<br />
Users<br />
Flow<br />
Maintenance<br />
Configuration<br />
Management<br />
•Benefits<br />
— Realize new functionality and<br />
dramatic total cycle time<br />
improvement<br />
— Maintain existing infrastructure<br />
— Drop in, no risk<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
19
<strong>Calibre</strong> <strong>nmDRC</strong><br />
Dramatically Reduced Iteration Runtimes<br />
• Incremental DRC<br />
— Highlight errors as identified<br />
• Begin debug immediately -<br />
before job completion<br />
— Automatically identify<br />
changed regions<br />
• DB Diff<br />
— Minimize subsequent runtimes<br />
• Stream-out only changed areas<br />
• Run only affected checks<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
20
<strong>Calibre</strong> <strong>nmDRC</strong><br />
Dramatically Reduced Iteration Runtimes<br />
Traditional Serial DRC Verification<br />
Translation<br />
DRC Runtime<br />
Debug<br />
Days<br />
<strong>Calibre</strong> <strong>nmDRC</strong>: Dynamic Results Visualization and Incremental Verification<br />
Error #1<br />
• Benefits<br />
— Traditional serial verification process<br />
produces < PV iteration per shift<br />
Error #2<br />
Error #3<br />
Error #4<br />
Error #5<br />
— <strong>nmDRC</strong> revolutionizes the debugging process<br />
— Dramatically improves productivity<br />
2 hrs 4 hrs<br />
6 hrs<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
21
<strong>Calibre</strong> <strong>nmDRC</strong><br />
Modern Development Tools<br />
Traditional SVRF<br />
Recommended Rule Metal1<br />
METAL1.1.1R#rra#b0.28 = INT ame1 >=0.256 0=0.28 0=0.30 0=0.256=0<br />
[(COUNT(METAL1.1.1R#rra#b0.28))*1.0/AREA()]<br />
RDB ONLY "yield.rdb"<br />
}<br />
METAL1.1.1R#rra#b0.28_c {@ output RR yield prediction to RDB BY CELL<br />
@ check: METAL1.1.1R#rra<br />
DFM ANALYZE METAL1.1.1R#rra#b0.28 METAL1.1.1R#rra#b0.30 METAL1.1.1R#rra#b0.32 >= 0 BY CELL NOPSEUDO<br />
[(COUNT(METAL1.1.1R#rra#b0.28))*1.0/AREA()]<br />
RDB ONLY "yield.rdb"<br />
}<br />
METAL1.1.1R#rra#b0.28_ {@ {Minimum METAL1 width >=0.256=0.28=0<br />
[(COUNT(METAL1.1.1R#rra#b0.30))*0.8/AREA()]<br />
RDB ONLY "yield.rdb"<br />
}<br />
METAL1.1.1R#rra#b0.30_c {@ output RR yield prediction to RDB BY CELL<br />
@ check: METAL1.1.1R#rra<br />
DFM ANALYZE METAL1.1.1R#rra#b0.28 METAL1.1.1R#rra#b0.30 METAL1.1.1R#rra#b0.32 >= 0 BY CELL NOPSEUDO<br />
[(COUNT(METAL1.1.1R#rra#b0.30))*0.8/AREA()]<br />
RDB ONLY "yield.rdb"<br />
}<br />
METAL1.1.1R#rra#b0.30_ {@ {Minimum METAL1 width >=0.28=0.30=0<br />
[(COUNT(METAL1.1.1R#rra#b0.32))*0.6/AREA()]<br />
RDB ONLY "yield.rdb"<br />
}<br />
METAL1.1.1R#rra#b0.32_c {@ output RR yield prediction to RDB BY CELL<br />
@ check: METAL1.1.1R#rra<br />
DFM ANALYZE METAL1.1.1R#rra#b0.28 METAL1.1.1R#rra#b0.30 METAL1.1.1R#rra#b0.32 >= 0 BY CELL NOPSEUDO<br />
[(COUNT(METAL1.1.1R#rra#b0.32))*0.6/AREA()]<br />
RDB ONLY "yield.rdb"<br />
}<br />
METAL1.1.1R#rra#b0.32_ {@ {Minimum METAL1 width >=0.30=0<br />
[((COUNT(METAL1.1.1R#rra#b0.28))*1.0+(COUNT(METAL1.1.1R#rra#b0.30))*0.8+(COUNT(METAL1.1.1R#rra#b0.32))*0.6)/AREA()]<br />
RDB ONLY "yield.rdb"<br />
}<br />
METAL1.1.1R#rra#_c {@ output RR yield prediction to RDB BY CELL<br />
@ check: METAL1.1.1R#rra<br />
DFM ANALYZE METAL1.1.1R#rra#b0.28 METAL1.1.1R#rra#b0.30 METAL1.1.1R#rra#b0.32 >= 0 BY CELL NOPSEUDO<br />
[((COUNT(METAL1.1.1R#rra#b0.28))*1.0+(COUNT(METAL1.1.1R#rra#b0.30))*0.8+(COUNT(METAL1.1.1R#rra#b0.32))*0.6)/AREA()]<br />
RDB ONLY "yield.rdb"<br />
}<br />
Repeat For Metal2 through Metal9<br />
Total Lines of SVRF Code = 509<br />
<strong>Calibre</strong> TVF<br />
Recommended Rule Metal1<br />
set met111_bin {SLIST 0.256 0.28 0.30 0.32}<br />
Create_RRA_SVRF METAL1.1.1R {WID_MIN_L1 {ame1 ORTHO} "Minimum METAL1 width"} \<br />
$met111_bin {DLIST 1.0 0.8 0.6} {USER $lambda/AREA()}<br />
Call Template = 2 lines of TVF Code<br />
Library Template = 59 lines of TVF Code<br />
Forloop all metals = 3 lines of TVF Code<br />
Total lines of TVF Code = 64<br />
• High level programming language<br />
• Simplifies the development and maintenance<br />
of advanced rule files<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
22
<strong>Calibre</strong> Integrated into Design Platforms<br />
Mentor<br />
IC Station, DESIGNrev<br />
GDSII<br />
Cadence<br />
Virtuoso/ADE, Encounter<br />
Synopsys<br />
Astro<br />
Magma<br />
BlastFusion<br />
OASIS<br />
Milkyway<br />
OpenAccess<br />
LEF/DEF<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
23
Virtuoso Integration Example<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
24
BlastFusion Integration Example<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
25
Encounter Integration Example<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
26
OASIS: Tackling the Capacity Bottlenecks<br />
>10x!<br />
GDSII<br />
Reduction Amount (X)<br />
OASIS<br />
Original GDSII-to-OASIS<br />
File Size Reduction Distribution<br />
Evaluation of 5000 customer GDSII vs OASIS data files!<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
27
Statistical Analysis Augments Simple<br />
Error Markers<br />
Original Design Data<br />
Typical DRC Result<br />
Typical DFM Result<br />
<strong>Calibre</strong> YieldAnalyzer<br />
DRC Rule<br />
DFM Rule<br />
130nm<br />
200nm<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
28
Yield Analysis and Visualization<br />
YRC Rule Summary Table<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
29
Model Based Verification: From DRC to <strong>nmDRC</strong><br />
Rule Based<br />
Random<br />
<strong>Calibre</strong> YieldAnalyzer<br />
Recommended Rule Analysis<br />
Systematic<br />
<strong>Calibre</strong> YieldAnalyzer<br />
Recommended Rule Analysis<br />
Parametric<br />
<strong>Calibre</strong> YieldAnalyzer<br />
Recommended Rule Analysis<br />
Model Based<br />
<strong>Calibre</strong> YieldAnalyzer<br />
Critical Area Analysis<br />
<strong>Calibre</strong> LFD<br />
Litho Variation Analysis<br />
<strong>Calibre</strong> LVS/xRC/xL<br />
Mfg Aware Silicon Modeling<br />
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Solving the WHOLE Cycle Time Issue<br />
Classic Serial Verification<br />
Design<br />
Stream<br />
PV<br />
Debug<br />
PV<br />
Debug<br />
PV<br />
Debug<br />
Stream<br />
<strong>nmDRC</strong> Verification<br />
Direct Database<br />
Access Eliminates<br />
Stream-out<br />
Hyperscaling<br />
Dramatically Reduces<br />
Runtime<br />
Dynamic Results<br />
Visualization Enables<br />
Real-Time Debug<br />
Design<br />
Statistical Analysis<br />
Facilitates Pinpoint<br />
Debugging<br />
TVF Simplifies<br />
Rule Scripting &<br />
Maintenance<br />
Rule and<br />
Model-Based<br />
Verification<br />
Incremental DRC<br />
Dramatically Reduces<br />
Iteration Runtimes<br />
OASIS Format<br />
Significantly Reduces<br />
Stream-out Time<br />
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Summary<br />
• The <strong>Calibre</strong> nm Platform provides the industry’s<br />
most robust platform for design to silicon in the<br />
DFM era<br />
• With <strong>Calibre</strong> <strong>nmDRC</strong> we continue to provide best<br />
in class performance, improved total TAT and the<br />
design database integration required for<br />
nanometer design<br />
The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
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The <strong>Calibre</strong> nm Platform and <strong>Calibre</strong> <strong>nmDRC</strong>, JS, June/July 2006<br />
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Design Environment Integration: How It Works<br />
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Introducing the New <strong>Calibre</strong> nm Platform<br />
Layout Data<br />
<strong>Calibre</strong> PVX<br />
Results Data<br />
Data Query<br />
Results Viewing<br />
Layout Update<br />
GDSII<br />
OASIS<br />
Schematic<br />
Netlist<br />
DRC/LVS<br />
xRC/xL<br />
SVRF/CAPI<br />
MTflex<br />
Derived Layout<br />
& Error Markers<br />
Devices &<br />
Parasitics<br />
Data Query<br />
Results<br />
Viewing<br />
GDSII<br />
OASIS<br />
Post Layout<br />
Netlist<br />
Design and<br />
Mfg. Data<br />
LEF/DEF<br />
Milky Way<br />
Open Access<br />
Mfg Models &<br />
Parameters<br />
Performance<br />
Constraints<br />
<strong>Calibre</strong> Analysis<br />
& Enhancement<br />
Recommended<br />
Rules & CAA<br />
Litho Friendly<br />
Design<br />
Device and<br />
Interconnect<br />
Modeling<br />
Layout<br />
Modifications<br />
TVF (TCL)<br />
Hyperflex<br />
DFM Data<br />
Original<br />
Layout<br />
Hierarchy &<br />
Connectivity<br />
Analysis<br />
Results<br />
Enhancement<br />
Results<br />
Rule<br />
Derivations<br />
Optimization<br />
Constraint<br />
Based<br />
Filtering<br />
Incremental<br />
Analysis<br />
Incremental<br />
Enhancement<br />
Results Analysis<br />
Reports &<br />
Visualization<br />
Silicon<br />
DeBug<br />
Design DB<br />
Update<br />
Design Update<br />
LEF/DEF<br />
Milky Way<br />
Open Access<br />
Sensitivity<br />
Analysis<br />
Design Quality<br />
Assessment<br />
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Traditional DRC<br />
Layout Data<br />
<strong>Calibre</strong> PVX<br />
Results Data<br />
Data Query<br />
Results Viewing<br />
Layout Update<br />
GDSII<br />
OASIS<br />
Schematic<br />
Netlist<br />
DRC/LVS<br />
xRC/xL<br />
SVRF/CAPI<br />
MTflex<br />
Derived Layout<br />
& Error Markers<br />
Devices &<br />
Parasitics<br />
Data Query<br />
Results<br />
Viewing<br />
GDSII<br />
OASIS<br />
Post Layout<br />
Netlist<br />
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Introducing Next Generation DRC<br />
<strong>Calibre</strong> <strong>nmDRC</strong><br />
Layout Data<br />
<strong>Calibre</strong> PVX<br />
Results Data<br />
Data Query<br />
Results Viewing<br />
Layout Update<br />
GDSII<br />
OASIS<br />
Schematic<br />
Netlist<br />
DRC/LVS<br />
xRC/xL<br />
SVRF/CAPI<br />
MTflex<br />
Derived Layout<br />
& Error Markers<br />
Devices &<br />
Parasitics<br />
Data Query<br />
Results<br />
Viewing<br />
GDSII<br />
OASIS<br />
Post Layout<br />
Netlist<br />
Design and<br />
Mfg. Data<br />
LEF/DEF<br />
Milky Way<br />
Open Access<br />
Mfg Models &<br />
Parameters<br />
Performance<br />
Constraints<br />
<strong>Calibre</strong> Analysis<br />
& Enhancement<br />
Recommended<br />
Rules & CAA<br />
Litho Friendly<br />
Design<br />
Device and<br />
Interconnect<br />
Modeling<br />
Layout<br />
Modifications<br />
TVF (TCL)<br />
Hyperflex<br />
DFM Data<br />
Original<br />
Layout<br />
Hierarchy &<br />
Connectivity<br />
Analysis<br />
Results<br />
Enhancement<br />
Results<br />
Rule<br />
Derivations<br />
Optimization<br />
Constraint<br />
Based<br />
Filtering<br />
Incremental<br />
Analysis<br />
Incremental<br />
Enhancement<br />
Results Analysis<br />
Reports &<br />
Visualization<br />
Silicon<br />
DeBug<br />
Design DB<br />
Update<br />
Design Update<br />
LEF/DEF<br />
Milky Way<br />
Open Access<br />
Sensitivity<br />
Analysis<br />
Design Quality<br />
Assessment<br />
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<strong>Calibre</strong> <strong>nmDRC</strong>: Drops Into Current CAD<br />
Environment Without Disruption<br />
Encryption<br />
Rule<br />
Files<br />
Interactive,<br />
Batch<br />
Design<br />
Environments<br />
Invocation,<br />
Control<br />
Modification<br />
Flows<br />
Design<br />
Data<br />
<strong>Calibre</strong><br />
<strong>nmDRC</strong><br />
Reporting<br />
Formats<br />
Debug<br />
Methodologies<br />
Trained<br />
Users<br />
Flow<br />
Maintenance<br />
Configuration<br />
Management<br />
• Benefits<br />
— Realize new functionality and dramatic<br />
total cycle time improvement<br />
— Maintain existing infrastructure<br />
— Drop in, no risk<br />
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Advantages of <strong>Calibre</strong> <strong>nmDRC</strong><br />
• Faster Turn Around Time<br />
Computational<br />
Complexity<br />
Rules Moving to<br />
Models<br />
The Fog of DFM<br />
Issues<br />
Yield Is Hard<br />
To Do<br />
<strong>Calibre</strong> <strong>nmDRC</strong><br />
• Modern Development Tools<br />
• Model-Based Verification<br />
• Statistical Analysis to Augment<br />
Simple Error Markers<br />
• Integration that allows tight<br />
‘fix’ loops<br />
• Higher productivity<br />
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