HyperLynx SI GHz- Accurate, Easy-to-use, Multi-Gbps Solutions:0.qxd

White Paper
ACCURATE, MULTI-GBPS SERIAL CHANNEL DESIGN
SOLUTIONS FOR THE ENTIRE DESIGN TEAM
July 2009
ABSTRACT
The design of high performance multi-Gbps channels inevitably requires facing new challenges.
One possible approach is to attempt to blindly apply conservative layout guidelines that have been
established by the success of previous designs or have been provided in the form of reference
designs from an IC vendor. This methodology has merit, but will tend to result in designs that have
mediocre performance and require unnecessarily expensive PCB materials and manufacturing
processes and/or over-constrain the layout engineer placing components and routing the PCB. An
alternative approach that will reduce cost and allow maximum performance is to develop knowledge of
how physical design rules affect electrical performance so that appropriate tradeoffs can be applied.
HyperLynx GHz provides an intuitive but powerful suite of tools that allows every member of the high
speed serial channel design team to participate in creating the highest quality design while minimizing
manufacturing costs. HyperLynx GHz also provides the post layout analysis tools that allow the team
to ensure design goals have been met and that the product will operate reliably under field conditions.
This document describes of the advantages of deploying HyperLynx to meet the increasingly complex
challenges of high speed channel design. An overview is provided of the advanced analysis
technology. Finally two case studies are presented exploring the sensitivity of channel design to two
design trade-offs: via back-drilling and trace length imbalance.
Author:
Ian C. Dodd
Mentor Graphics Corporation
8005 SW Boeckman Road
Wilsonville, OR 97070 USA
Phone: +1 800-592-2210 or +1 503-685-7000
www.mentor.com/pcb

THE HYPERLYNX PRODUCT FAMILY
The HyperLynx product family provides comprehensive, easy to use solutions to today’s high speed PCB
analysis challenges. These solutions provide the flexibility and accuracy to meet the needs of whole electronic
design team including: electrical design engineers, signal integrity engineers, thermal and emc management
specialists.
HyperLynx Signal and Power Integrity
High-speed signal and power integrity analysis
at circuit, behavioral and system levels in both
the time and frequency domains
HyperLynx Thermal
Analyze board level thermal problems
throughout the design cycle
HyperLynx EMI
Check PCBs for incorrect or dangerous routing
structures that cause EMI problems
HyperLynx Analog/Mixed Signal
Board-level analog circuit simulation integrated
into the DxDesigner environment
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HYPERLYNX SI GHZ
The HyperLynx product suite from Mentor Graphics
leads the market in mainstream signal integrity tools
because of its intuitive and easy to use interface
combined with its accurate and robust simulation
technology. The HyperLynx SI GHz package offers
numerous capabilities specific to high performance
memory and multi-Gbps serial channel analysis.
HyperLynx SI GHz includes the tools needed to meet your current and future
multi-Gbps memory and serial channel design challenges
HyperLynx SI GHz applications include the design
and post layout validation of high performance
synchronous logic channels, source-synchronous
memory buses including DDR2 and DDR3 and all
popular multi-Gbps
serial channels.
• Consumer Audio/Video — high definition video
(HDMI)
• Computing — I/O buses (Hyper Transport, PCEe),
disk drive (SATA), external peripheral (USB)
• Telecommunications — Fibre Channel, Infiniband
and 10 Gigabit Ethernet
• Mobile phones — display (MIPI) and camera
(SMIA) interfaces.
HyperLynx SI GHz provides the depth of technology
needed to analyze the next
generation of high
performance serial
channels. The FastEye
tool provides a rich
environment for linear
channel analysis and
statistical post processing
of bit error rate
information. The
Eldo/ADVance MS
simulator uniquely offers
an efficient single kernel
circuit and system level
analysis capability. This provides the flexibility to
accurately analyze complex behaviors including driver
non-linearity due to output saturation, advanced
equalization or complex clock/data recovery.
HYPERLYNX SI
GHZ HIGH SPEED
HyperLynx SI GHz
provides the tools
needed to create and
validate designs
incorporating the high
speed serial channel
standards that are now
established in every
segment of the
HyperLynx SI GHz pre- and post-layout views of an SATA high speed serial channel
electronics industry:
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A single, integrated environment is provided for the
HyperLynx SI GHz and HyperLynx Power Integrity
(PI) tool suites. The combined power of the two tool
suites can be used to investigate the complexities
introduced when multi-Gbps channels are subject to
noisy planes and non-ideal return paths. Common
phenomena that can be investigated include:
• Jitter introduced into multi-Gbps channels when
differential trace layout asymmetries convert
common mode noise into differential noise.
• Characterization of coupled via pairs with nonideal
return paths.
THE HYPERLYNX SI GHZ ADVANTAGE
HyperLynx SI GHz offers numerous advantages for
users. These are summarized here.
HYPERLYNX INCREASES PRODUCTIVITY
HyperLynx is industry renowned for its intuitive user
interface. This combined with powerful analysis
features ensures increased productivity and faster time
to market.
The HyperLynx experience starts with a shorter
learning period. Customers report using the on-line
tutorial and examples to learn the basic skills needed
to prototype and analyze a representative high speed
serial channel in one day or less.
User interface wizards lead the user through the steps
needed to accurately set up the more advanced
analysis features.
The combination of ease of use and advanced analysis
in HyperLynx SI GHz ensures that every member of
the design team, including hardware design engineers,
PCB designers and signal integrity specialists, can
cooperate in using a single analysis environment.
Using consistent analysis at every stage of the design
process from concept through post-layout validation
ensures fast reliable results.
HYPERLYNX ENABLES OPTIMAL CHANNEL
PERFORMANCE
Thorough high speed channel analysis in HyperLynx
allows designs to be tuned for maximum performance
while providing adequate safety margins to
accommodate component and manufacturing
tolerances.
Tuning includes the optimal choice of components
including drivers, receivers, connectors and cables. It
also includes the appropriate choice of interconnect
characteristics including PCB stackup, trace widths,
routing rules and the appropriate via design.
HyperLynx LineSim provides a fast efficient virtual
prototyping environment to conduct pre-layout high
speed channel design tuning. The results of tuning can
be quickly appraised in both the time and frequency
domains.
HyperLynx BoardSim provides post-layout channel
analysis to ensure layout compromises have not
significantly impacted channel performance.
HYPERLYNX INCREASES PRODUCT
RELIABILITY
The design of a reliable product requires the
concerted effort of the whole design team. HyperLynx
SI GHz provides a powerful single high speed serial
channel analysis environment that can be shared and
understood by all members of the design team.
Reliable channel design requires paying attention to
detail at every step of the design process. Virtual
prototyping in HyperLynx ensures the choice of
components and layout guidelines that will meet and
exceed channel design requirements. Post-layout
channel validation allows the PCB designer and the
design engineer to work as a team to meet the
performance goals while minimizing the adverse
effects on other aspects of the layout.
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HYPERLYNX SI GHZ REDUCES PRODUCT
COST
Almost all high speed serial channel design choices
involve a trade-off between performance and cost. Just
the choice of PCB materials and technology requires
complex tradeoffs including:
• Consistency of physical dimensions and traces
impedance
• Roughness of trace surfaces.
• Choice of through-hole, blind and buried or backdrilled
vias
• PCB stack-up design including choice of dielectric
materials.
HyperLynx virtual prototypes allow the engineer to
quantifiably determine the performance impact of each
design choice. This together with material and process
cost information allows the choice of
design options that meet performance
standards at minimum cost.
Increased tool utilization
HyperLynx SI GHz provides value at every stage of
the design process, from sandbox through post-layout
reliability analysis.
Depth of technology
HyperLynx SI GHz provides the depth of technology
to address established and future high speed serial
channel challenges. The well established
Eldo/ADVance MS simulator distinguishes
HyperLynx SI GHz as the only signal integrity tool to
provide efficient single kernel, simultaneous circuit
and system level simulation. The single kernel
implementation avoids the major inter-process
communication overhead incurred in alternate
solutions. Eldo/ADVance MS is complemented by
HYPERLYNX SI GHZ MINIMIZES
OWNERSHIP COST
HyperLynx SI GHz offers full solutions
to the most challenging high speed
serial channel problems while
minimizing ownership cost and
investment risk. HyperLynx minimizes
ownership cost through:
Reducing training and support costs
HyperLynx SI GHz combines accurate
multi-Gbps channel analysis in an
intuitive environment that everyone can
use. It can meet all the routine and
advanced analysis needs of the design
team without resorting to complicated
point- solution tools. HyperLynx
technology is all internally developed
resulting in solid integration between
modules and has the advantage of a single point of
contact for training, support and licensing.
HyperLynx SI GHz LineSim
6.25 Gbps Serial Channel
Example
the FastEye linear channel analysis engine that can
simulate channel response at speeds approaching a
million bits per minute.
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HYPERLYNX VISUAL IBIS EDITOR
The first and most widely adopted interactive IBIS editor.
• IBIS creation wizard • IBIS file outline view • Initial switch time correction
• IV, VT curve plotting • Interactive syntax correction • Removal of non-monotonicity
HYPERLYNX TOUCHSTONE AND FITTED POLE VIEWER
A powerful S-parameter and complex pole residue file generation utility.
• Single-ended and Differential S-parameter
Plotting
• Non-Causality detection & correction
• S-parameter file conversion: differential,
single- ended, Y, Z, complex pole residue
• Non-Passivity detection & correction
• Remove unneeded ports
• Synthesize SPICE equivalent model
HYPERLYNX LINESIM INTERACTIVE TRANSMISSION LINE EDITOR
The LineSim Editor provides an intuitive Eldo/ADVance MS high speed serial channel virtual prototyping
environment. Applications include:
• Up front sandbox viability analysis
• Pre-layout solution space analysis and constraint generation
• Post layout trouble shooting or reliability analysis.
LineSim allows for flexible interactive time and frequency domain analysis of high speed serial channels. Analysis
at multiple levels of abstraction is fully supported:
• SPICE / circuit level channel analysis in the widely adopted Eldo simulator
• Linear channel analysis utilizing the HyperLynx FastEye Suite
• Simultaneous non-linear circuit and system level simulation with Eldo / ADVance MS.
Highlights of the LineSim Environment Include:
• Highly intuitive user interface with wizards guide the user through advanced operations such as via design,
DDR3 simulation and FastEye linear channel analysis
• Interconnects specified by physical (layer, width etc) or electrical (Vp, Z0 & delay) views.
• Parameter sweeping controlled through a centralized spreadsheet
• Full support for transistor level SPICE, IBIS, SPICE macro, and VHDL-AMS (analog-digital mixed mode)
behavioral device modeling
• Accurate modeling of individual and coupled via pairs
• Robust efficient S-parameter support with causality and passivity enforcement
• Accurate, causal trace modeling using frequency dependant multi-pole Debye modeling of dielectric loss.
• Support for third party SPICE simulators.
• Design kit support, including PCIe, SATA, Fibre Channel and FPGA partners.
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HyperLynx LineSim SI GHz provides a
comprehensive environment for high
speed parallel and high speed serial
channel analysis. LineSim also provides
the interactive focus for the HyperLynx
Power Integrity (PI) Suite. The
addition of HyperLynx PI allows the
high speed serial channel analysis to
incorporate the effects of non-ideal
power planes including plane noise and
couple vias with non-ideal return paths.
SATA HS Serial Channel Extracted from BoardSim
POST-LAYOUT VERIFICATION
HYPERLYNX BOARDSIM POST-LAYOUT
SIGNAL INTEGRITY EDITOR
The HyperLynx SI GHz BoardSim post-layout multiboard
editor allows the easy import of single or multiboard
layouts from Mentor Graphics Board Station,
Expedition, or PADS PCB.
PCB Designs can also be easily imported from many
third part PCB layout editors including Cadence
Allegro, or Orcad, Zuken Visula or CR-5000 and
Altium.
Off-board channel elements such as connectors and
cables can be quickly and easily added.
HyperLynx SI GHz BoardSim provides for post-layout
designs, the same powerful device modeling and high
speed serial channel simulation features as are
provided by LineSim pre-layout designs.
LineSim virtual prototypes can be automatically
extracted from routed nets in BoardSim for the
purposes of performance trouble shooting or reliability
analysis.
HYPERLYNX MULTI-GBPS ANALYSIS
TECHNOLOGY
HYPERLYNX FASTEYELINEAR CHANNEL
ANALYSIS SOLUTIONS
FastEyeprovides the fastest possible high speed serial
channel analysis, typically simulating millions of
transitions per minute.
HyperLynx FastEyeis available from an intuitive user
interface wizard that allows the user to go from a high
speed channel design prototype to
an (optionally worst case) eye
diagram and BER results in
minutes.
HyperLynx SI GHz BoardSim
Example of SATA high-speed serial channel layout
Highlights of the FastEye Suite
Include:
• Deterministic and random jitter
sources
• Support for Linear FFE and nonlinear
DFE equalization. Tap
settings can be optionally
automatically optimized.
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• Patent pending technology automatically calculates
the worst case channel stimulus subject to the
constraints of channel protocol (e.g. 8bit/10bit
encoding).
• Automatic detection of significant channel nonlinearity.
• Analysis may be based on channel impulse or
internally generated pole zero residue description.
Pole-zero descriptions are compact without
excluding critical low frequency resonance
information.
HYPERLYNX MULTI-GBPS ANALYSIS
TECHNOLOGY
HYPERLYNX FASTEYELINEAR CHANNEL
ANALYSIS SOLUTIONS
FastEyeprovides the fastest possible high speed serial
channel analysis, typically simulating millions of
transitions per minute. HyperLynx FastEyeis available
from an intuitive user interface wizard that allows the
user to go from a high speed channel design prototype
to an (optionally worst case) eye diagram and BER
results in minutes.
Highlights of the FastEye Suite Include:
• Deterministic and random jitter sources
• Support for Linear FFE and non-linear DFE
equalization. Tap settings can be optionally
automatically optimized.
• Patent pending technology automatically calculates
the worst case channel stimulus subject to the
constraints of channel protocol (e.g. 8bit/10bit
encoding).
• Automatic detection of significant channel nonlinearity.
• Analysis may be based on channel impulse or
internally generated pole zero residue description.
Pole-zero descriptions are compact without
excluding critical low frequency resonance
information.
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HYPERLYNX MIXED CIRCUIT AND SYSTEM
LEVEL SOLUTIONS
HyperLynx mixed circuit and system level simulation
provides the fastest possible analysis when drivers or
receivers exhibit significant non-linearity.
The Eldo/ADVance MS (ADMS) simulation engine
provides HyperLynx GHz with the ability to
simultaneously conduct full non-linear circuit analysis
and system level analog and digital behavioral
analysis. The single kernel implementation ensures
the highest simulation efficiency.
Highlights of the Mixed Circuit and System Level
Simulation technology include:
• Advanced Multi-Gbps drivers can be modeled
including the non-linear effects of transistor output
saturation. This is becoming increasingly common
as transistor geometries and supply voltages shrink.
• Complex behavior e.g. driver asymmetry or warm
up can be easily modeled.
• Simulation of traditional transistor level SPICE
models.
• Analog behavioral models e.g. IBIS, SPICE macro
or analog VHDL add few elements to the circuit
simulation matrix so typically simulate 10-100X
faster than transistor level equivalents.
• Complex pole fitting technology ensures fast,
reliable and accurate interconnect modeling (with
causality and passivity enforcement).
• Digital behavioral models e.g. digital VHDL or ‘C’
language are directly evaluated in an event driven
digital simulation module. Complex digital driver
and receiver modules, e.g. clock multipliers,
protocol encoding, filtering and clock/data recovery
are efficient processed. (Simulating these elements
in an analog circuit simulator would be impossibly
inefficient).
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CASE STUDY: IS BACK-DRILLING OF VIAS
NECESSARY AT 6.25GBPS?
The design of high performance multi-Gbps channels
inevitably requires facing new challenges. One
possible approach is to attempt to use blindly apply set
of conservative layout guidelines that have been
established by the success of previous designs or have
been provided in the form of reference designs from
an IC vendor. This methodology has merit, but will
tend to result in designs that have mediocre
performance and require un-necessity expensive PCB
materials and manufacturing processes and/or overconstrain
the layout engineer placing components and
affect electrical behavior. The virtual prototype for a
the 6.25Gbps serial channel to be used in this case
study is shown.
The example is representative of a system board with a
plug in card. The relatively short BGA breakout and
surface mount connector coupling traces have been
implemented as micro-strip on the top surface of the
PCB. The majority of the channel has been
implemented as strip-line on the first inner signal
layer. This minimizes EMC and cross-talk between the
channel and its neighboring nets. The Vcc plane
between the two routing layers, provides the critical
high frequency return path.
LineSim 6.25 Gbps Channel Example
routing the PCB. An alternative approach that will
reduce cost and allow maximum performance is to
develop knowledge of how physical design rules affect
electrical performance so that appropriate tradeoffs can
be applied.
HyperLynx SI GHz LineSim provides an efficient
environment in which virtual prototypes can be created
to gain knowledge of how physical design variations
This design requires vias. Conservative design
practices would require these vias to be implemented
using blind vias or as back-drilled through hole vias.
In this case study we will look at whether using plain
through-hole vias will significantly affect channel
performance.
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9

Through hole via models with and without backdrilling
were created in using the coupled via wizard.
The two via designs are shown in below:
HyperLynx Via Visualizer
To fully understand the influence of back-drilling
vias, it is necessary to look at its electrical effect in
both the frequency and time domains.
Frequency domain channel descriptions are created in
LineSim utilizing the well established Eldo/ADVance
MS simulator and viewed using the HyperLynx
Touchstone and Fitted Poles Viewer. Plots of
differential forward insertion loss versus frequency
and common mode to differential mode conversion
versus frequency for the
channel with and without via
back-drilling are shown below:
The differential insertion loss
plot shows that the channel
with through-hole vias has
substantial propagation losses.
The channel with through-hole
vias is free from significant
resonances which could
adversely affect channel reliability and make the
results of time domain analysis sensitive to small
changes in the fundamental frequency of the stimulus.
The plot for the channel with back-drilled vias shows a
decrease in propagation loss, but this decrease is not
substantial. As might be expected, it is also free from
significant resonances.
Frequency Domain Effect of Via Back Drilling at 6.25 Gbps
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FastEye Analysis of 6.25 Gbps Channel
Worst-case 8b10b constrained stimulus, back-drilled vias and 2-tap FFE equalizer
The common mode to differential mode plots shows
that both versions of the channel are highly insensitive
to common mode noise. This would be expected since
the differential interconnect in this example is highly
symmetric.
In this example all time domain results were generated
in a matter of minutes using the FastEyelinear channel
analysis tool. The figure on this page shows the highly
intuitive FastEyemulti-step wizard together with a
selection of analysis results.
In the FastEyeanalysis, the channel protocol was
specified as using 8b10b encoding. This allows
FastEyeto calculate the worst case stimulus that is
consistent with the protocol (patent pending). In the
example analysis, the worst case stimulus for the
channel, with and without back-drilling of vias was
used to create the worst case eye diagrams.
FastEyesupports the modeling and optimization
common forms of transmitter and receiver equalization.
Worst case eye measurements were made without
equalization and with an optimal 2 tap FFE equalizer.
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The results obtained are shown below:
No Equalization
Optimal 2-tap FFE Equalization
Eye Height Eye Width Eye Height Eye Width
Back-drilled vias 180 mV 98 ps (61% UI) 438 mV 145 ps (91% UI)
Through-hole vias 139 mV 88 ps (55%UI) 393 mV 135 ps (84% UI)
An analysis of the FastEyesimulation results indicate
that, in this example, leaving the stub on the throughhole
vias:
• Does not introduce significant resonances at the
signaling frequency.
• Increases channel propagation loss.
• Closes the eye at the receiver by a moderate
(5-10%) amount.
• Does not affect sensitivity to common mode
(e.g. plane) noise.
In order to make a definitive analysis of whether it is
possible to omit the back-drilling of vias in the
example layout further analysis is needed to study the
sensitivity to other factors that cause performance
degradation of the channel. In the next case study
sensitivity to trace length imbalance between the two
nets that make up a differential pair will be analyzed.
CASE STUDY: HOW CLOSELY MUST TRACE
LENGTHS BE MATCHED?
Layout engineers are provided
with complex constraints and
design rules for each type of net
in a layout. High frequency
differential pairs have some of
the most challenging
constraints, often including
length matching between the
traces that make up the pair to
+/- mil. They are faced with the
daunting task of meeting these
requirements whilst minimizing
production and material cost.
Trade-offs are usually required, including routing
multi-Gbps channels around obstacles such as areas of
split planes which will not provide an adequate high
frequency return path for the channels.
Good layout practices e.g. using 45 degree corners and
jogging around obstacles with turns in alternate
directions can minimize imbalance in the electrical
lengths of the legs of a differential pair. Practical
designs will inevitably have some imbalance as can be
seen in the layout shown previously in section
describing BoardSim. This case study will show that
HyperLynx LineSim provides an excellent
environment to investigate the sensitivity of multi-
Gbps channels to trace length imbalance. For
simplicity the analysis will be done using the same
LineSim example as was used to investigate the effect
of back-drilling-vias. Similar analysis can be carried
out on routed nets first using BoardSim to assemble
Adding Trace Length Imbalance in LineSim
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the channel from its component layouts, cables and
connectors. BoardSim can then be used to export a
LineSim virtual prototype.
As in the previous case study, to gain a full
understanding of the sensitivity of high speed serial
channel to a physical modification, it is necessary to
look at its electrical effect in both the frequency and
time domains.
Starting analysis in the frequency domain, differential
S-parameter plots were created using a range of trace
length imbalances from perfectly balanced to a 0.4
inch imbalance. The differential mode insertion loss
and common mode to differential mode conversion
plots are shown.
The differential insertion loss plots show that length
imbalances as small as 0.1 inch cause measureable
increase in channel attenuation. Attenuation increases
rapidly as the length imbalance increases due to
resonances. Significant low ‘Q’ resonances occur with
length imbalances over 0.1 inches. For imbalances of
0.3 inch or less the resonances are above the third
harmonic of the channel frequency (3.125GHz) and
may only have a minimal impact on channel
performance.
The common mode to differential mode conversion
plot indicates that trace length imbalances have a
dramatic effect on the conversion of common mode
signals to differential mode signals. The maximum
conversion ratio is plotted versus length imbalance in
the graph below. It can be seen that a length imbalance
of 0.2 inches causes close to 10% of the common
mode noise from plane resonances and other sources
to be converted into differential noise.
Conversion Ratio
Common to Differential
Mode Conversion
Length Imbalance (inches)
Common-to-Differential Mode Conversion
Ratio vs. Length Imbalance (inches)
HyperLynx FastEye linear
channel analysis was used to
characterize the channel in the
time domain using a similar
approach to that used in the
earlier case study. The results
are plotted below for the range
of imbalance lengths.
The eye plot results for the
example channel show that
after equalization with a
simple 2 tap FFE filter, trace
length imbalance of 0.2 inches
or less have a mildly adverse
effect on eye opening (3-4%).
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The conclusions drawn from this case study include:
• Trace length imbalances of 0.2 inches or less have a
relatively minor direct effect on eye opening after
simple equalization.
• Trace length imbalances of as small as 0.1 inch can
have a major indirect affect on eye opening by
causing the conversion of common mode noise into
differential mode noise. A PCB may have many
sources of common mode noise including that
induced by switching currents into the power
planes.
CONCLUSION
HyperLynx GHz provides the advantages needed to be
successful in the challenging arena of high speed serial
channel design. Its combination of intuitive user
interface, accuracy and powerful advanced analysis
features allow teams to meet their goals:
• Increased productivity
• Lowest overall cost of ownership
• Optimal channel performance
• Increased product reliability
• Reduced product cost
www.mentor.com/pcb
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For more information, call us or visit: www.mentor.com/pcb
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