System on Chip Design Space Exploration: Design Trotter Framework

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DSE Framework Introduction : motivations for DSE Target Architecture Model <strong>System</strong> modeling Task Level HCDFG level Exploration & Decision Tools : HCDFG-DT : Design Space Exploration & Characterization RT-DT : Exploration, Real Time Scheduling & Partitioning SÉMINAIRE SCEE SUPELEC, 21/10/2004 2
Introduction : Directions ☯ ☯ As automotive & avionics before, the issue of SOC design is turning into a question of knowledge management. "Customization and speed-to-market will drive the industry from the bottom up" [M.J.Bass, HP & M.Christensen, Harvard] Performances required by users are finally provided => Next challenge : fast design of customized reliable products 75% Reuse & 15% Innovation : 6 months design delay ☯ HW/SW On line Debugging and Update ☯ CAD Tools for Design Space Exploration & Synthesis ☯ RTOS considerations in the HW/SW codesign flow ☯ Flexible HW/SW Architectures SÉMINAIRE SCEE SUPELEC, 21/10/2004 3
Page 1: System on Chip Des
Page 5 and 6: Introduction : Objectives A <stron
Page 7 and 8: Target Architecture Model An examp
Page 9 and 10: System Modeling E
Page 11 and 12: System Modeling 2
Page 13 and 14: Exploration & Decision Tools I HCD
Page 15 and 16: Exploration & Decision Tools I B)
Page 17 and 18: Exploration & Decision Tools I D)
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Page 21 and 22: Exploration & Decision Tools I E)
Page 23 and 24: Exploration & Decision Tools I F)
Page 25 and 26: Exploration & Decision Tools II De
Page 27 and 28: Exploration & Decision Tools II Hi
Page 33 and 34: PhD Involved in the project Former

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